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"vtach.v" line 61 Connection to input port 'a' does not match port size
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"vtach.v" line 61 Connection to output port 'z' does not match port size
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"bcdneg.v" line 13 Connection to input port 'a' does not match port size
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"bcdneg.v" line 13 Connection to output port 'z' does not match port size
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"bcdneg.v" line 21 Connection to input port 'a' does not match port size
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"bcdneg.v" line 21 Connection to output port 'z' does not match port size
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"bcdneg.v" line 13 Connection to input port 'a' does not match port size
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"bcdneg.v" line 13 Connection to output port 'z' does not match port size
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"ipcore_dir/mainmem.v" line 18: Instantiating black box module <mainmem>.
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"io_output.v" line 14: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.
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"io_output.v" line 14: Comparisons to 'X' or 'Z' are treated as always false.
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Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Hierarchical block <add3> is unconnected in block <inc>.
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It will be removed from the design.
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Hierarchical block <add4> is unconnected in block <inc>.
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It will be removed from the design.
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Hierarchical block <add4> is unconnected in block <inc>.
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It will be removed from the design.
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The FF/Latch <v_8> in Unit <in> is equivalent to the following 4 FFs/Latches, which will be removed : <v_9> <v_10> <v_11> <v_12>
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FF/Latch <v_8> (without init value) has a constant value of 0 in block <in>. This FF/Latch will be trimmed during the optimization process.
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FFs/Latches <v<12:8>> (without init value) have a constant value of 0 in block <io_input>.
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Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram of type RAMB16_S36_S36 has been replaced by RAMB16
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Unit alu: 13 multi-source signals are replaced by logic (pull-up yes):
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Unit memory: 13 internal tristates are replaced by logic (pull-up yes):
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Unit io_input: 13 internal tristates are replaced by logic (pull-up yes):
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The FF/Latch <dbus<2>LogicTrst18_SW0_SW0_FRB> in Unit <top> is equivalent to the following 3 FFs/Latches : <dbus<1>LogicTrst18_SW0_SW0_FRB> <dbus<3>LogicTrst18_SW0_SW0_FRB> <dbus<1>LogicTrst181_SW0_SW0_FRB>
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The FF/Latch <dbus<2>LogicTrst18_SW0_SW0_FRB> in Unit <top> is equivalent to the following 3 FFs/Latches, which will be removed : <dbus<1>LogicTrst18_SW0_SW0_FRB> <dbus<3>LogicTrst18_SW0_SW0_FRB> <dbus<1>LogicTrst181_SW0_SW0_FRB>
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