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wd5gnr |
SET_FLAG DEBUG FALSE
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SET_FLAG MODE INTERACTIVE
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SET_FLAG STANDALONE_MODE FALSE
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SET_PREFERENCE devicefamily spartan3
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SET_PREFERENCE device xc3s1000
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SET_PREFERENCE speedgrade -4
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SET_PREFERENCE package ft256
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SET_PREFERENCE verilogsim true
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SET_PREFERENCE vhdlsim false
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SET_PREFERENCE simulationfiles Behavioral
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SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
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SET_PREFERENCE outputdirectory /home/alw/projects/vtachspartan/ipcore_dir/
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SET_PREFERENCE workingdirectory /home/alw/projects/vtachspartan/ipcore_dir/tmp/
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SET_PREFERENCE subworkingdirectory /home/alw/projects/vtachspartan/ipcore_dir/tmp/_cg/
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SET_PREFERENCE transientdirectory /home/alw/projects/vtachspartan/ipcore_dir/tmp/_cg/_dbg/
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SET_PREFERENCE designentry Verilog
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SET_PREFERENCE flowvendor Other
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SET_PREFERENCE addpads false
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SET_PREFERENCE projectname coregen
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SET_PREFERENCE formalverification false
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SET_PREFERENCE asysymbol false
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SET_PREFERENCE implementationfiletype Ngc
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SET_PREFERENCE foundationsym false
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SET_PREFERENCE createndf false
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SET_PREFERENCE removerpms false
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| 26 |
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SET_PARAMETER Component_Name mainmem
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| 27 |
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SET_PARAMETER Interface_Type Native
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| 28 |
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SET_PARAMETER AXI_Type AXI4_Full
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| 29 |
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SET_PARAMETER AXI_Slave_Type Memory_Slave
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SET_PARAMETER Use_AXI_ID false
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SET_PARAMETER AXI_ID_Width 4
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SET_PARAMETER Memory_Type Single_Port_RAM
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SET_PARAMETER ecctype No_ECC
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SET_PARAMETER ECC false
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SET_PARAMETER softecc false
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SET_PARAMETER Use_Error_Injection_Pins false
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SET_PARAMETER Error_Injection_Type Single_Bit_Error_Injection
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SET_PARAMETER Use_Byte_Write_Enable false
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SET_PARAMETER Byte_Size 9
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SET_PARAMETER Algorithm Minimum_Area
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SET_PARAMETER Primitive 8kx2
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SET_PARAMETER Assume_Synchronous_Clk false
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| 43 |
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SET_PARAMETER Write_Width_A 13
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SET_PARAMETER Write_Depth_A 100
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SET_PARAMETER Read_Width_A 13
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SET_PARAMETER Operating_Mode_A READ_FIRST
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SET_PARAMETER Enable_A Always_Enabled
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SET_PARAMETER Write_Width_B 13
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SET_PARAMETER Read_Width_B 13
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SET_PARAMETER Operating_Mode_B WRITE_FIRST
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SET_PARAMETER Enable_B Always_Enabled
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SET_PARAMETER Register_PortA_Output_of_Memory_Primitives false
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SET_PARAMETER Register_PortA_Output_of_Memory_Core false
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SET_PARAMETER Use_REGCEA_Pin false
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SET_PARAMETER Register_PortB_Output_of_Memory_Primitives false
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SET_PARAMETER Register_PortB_Output_of_Memory_Core false
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SET_PARAMETER Use_REGCEB_Pin false
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| 58 |
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SET_PARAMETER register_porta_input_of_softecc false
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SET_PARAMETER register_portb_output_of_softecc false
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SET_PARAMETER Pipeline_Stages 0
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SET_PARAMETER Load_Init_File true
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SET_PARAMETER Coe_File /home/alw/projects/vtachspartan/mainmemory.coe
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SET_PARAMETER Fill_Remaining_Memory_Locations false
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SET_PARAMETER Remaining_Memory_Locations 0
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SET_PARAMETER Use_RSTA_Pin false
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SET_PARAMETER Reset_Memory_Latch_A false
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SET_PARAMETER Reset_Priority_A CE
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SET_PARAMETER Output_Reset_Value_A 0
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SET_PARAMETER Use_RSTB_Pin false
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SET_PARAMETER Reset_Memory_Latch_B false
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SET_PARAMETER Reset_Priority_B CE
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SET_PARAMETER Output_Reset_Value_B 0
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SET_PARAMETER Reset_Type SYNC
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SET_PARAMETER Additional_Inputs_for_Power_Estimation false
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SET_PARAMETER Port_A_Clock 100
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SET_PARAMETER Port_A_Write_Rate 50
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SET_PARAMETER Port_B_Clock 100
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SET_PARAMETER Port_B_Write_Rate 50
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SET_PARAMETER Port_A_Enable_Rate 100
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SET_PARAMETER Port_B_Enable_Rate 100
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SET_PARAMETER Collision_Warnings ALL
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SET_PARAMETER Disable_Collision_Warnings false
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| 83 |
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SET_PARAMETER Disable_Out_of_Range_Warnings false
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| 84 |
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SET_CORE_NAME Block Memory Generator
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SET_CORE_VERSION 6.2
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SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2
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SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2
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SET_CORE_PATH /opt/Xilinx/13.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2
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SET_CORE_GUIPATH /opt/Xilinx/13.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tcl
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SET_CORE_DATASHEET /opt/Xilinx/13.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/doc/blk_mem_gen_ds512.pdf
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ADD_CORE_DOCUMENT
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ADD_CORE_DOCUMENT
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