| 1 |
2 |
wd5gnr |
SET_PARAMETER use_rstb_pin false
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| 2 |
|
|
SET_PARAMETER pipeline_stages 0
|
| 3 |
|
|
SET_PARAMETER assume_synchronous_clk false
|
| 4 |
|
|
SET_PARAMETER use_regcea_pin false
|
| 5 |
|
|
SET_PARAMETER axi_id_width 4
|
| 6 |
|
|
SET_PARAMETER softecc false
|
| 7 |
|
|
SET_PARAMETER load_init_file true
|
| 8 |
|
|
SET_PARAMETER port_a_write_rate 50
|
| 9 |
|
|
SET_PARAMETER disable_collision_warnings false
|
| 10 |
|
|
SET_PARAMETER use_byte_write_enable false
|
| 11 |
|
|
SET_PARAMETER ecc false
|
| 12 |
|
|
SET_PARAMETER primitive 8kx2
|
| 13 |
|
|
SET_PARAMETER port_b_clock 100
|
| 14 |
|
|
SET_PARAMETER remaining_memory_locations 0
|
| 15 |
|
|
SET_PARAMETER memory_type Single_Port_RAM
|
| 16 |
|
|
SET_PARAMETER register_porta_input_of_softecc false
|
| 17 |
|
|
SET_PARAMETER port_a_clock 100
|
| 18 |
|
|
SET_PARAMETER read_width_a 13
|
| 19 |
|
|
SET_PARAMETER disable_out_of_range_warnings false
|
| 20 |
|
|
SET_PARAMETER read_width_b 13
|
| 21 |
|
|
SET_PARAMETER register_portb_output_of_softecc false
|
| 22 |
|
|
SET_PARAMETER byte_size 9
|
| 23 |
|
|
SET_PARAMETER register_portb_output_of_memory_core false
|
| 24 |
|
|
SET_PARAMETER use_regceb_pin false
|
| 25 |
|
|
SET_PARAMETER register_porta_output_of_memory_core false
|
| 26 |
|
|
SET_PARAMETER reset_memory_latch_a false
|
| 27 |
|
|
SET_PARAMETER reset_memory_latch_b false
|
| 28 |
|
|
SET_PARAMETER register_porta_output_of_memory_primitives false
|
| 29 |
|
|
SET_PARAMETER use_error_injection_pins false
|
| 30 |
|
|
SET_PARAMETER enable_a Always_Enabled
|
| 31 |
|
|
SET_PARAMETER enable_b Always_Enabled
|
| 32 |
|
|
SET_PARAMETER port_a_enable_rate 100
|
| 33 |
|
|
SET_PARAMETER use_axi_id false
|
| 34 |
|
|
SET_PARAMETER write_depth_a 100
|
| 35 |
|
|
SET_PARAMETER algorithm Minimum_Area
|
| 36 |
|
|
SET_PARAMETER output_reset_value_a 0
|
| 37 |
|
|
SET_PARAMETER output_reset_value_b 0
|
| 38 |
|
|
SET_PARAMETER error_injection_type Single_Bit_Error_Injection
|
| 39 |
|
|
SET_PARAMETER port_b_write_rate 50
|
| 40 |
|
|
SET_PARAMETER ecctype No_ECC
|
| 41 |
|
|
SET_PARAMETER write_width_a 13
|
| 42 |
|
|
SET_PARAMETER write_width_b 13
|
| 43 |
|
|
SET_PARAMETER component_name mainmem
|
| 44 |
|
|
SET_PARAMETER reset_priority_a CE
|
| 45 |
|
|
SET_PARAMETER reset_priority_b CE
|
| 46 |
|
|
SET_PARAMETER operating_mode_a READ_FIRST
|
| 47 |
|
|
SET_PARAMETER additional_inputs_for_power_estimation false
|
| 48 |
|
|
SET_PARAMETER operating_mode_b WRITE_FIRST
|
| 49 |
|
|
SET_PARAMETER interface_type Native
|
| 50 |
|
|
SET_PARAMETER reset_type SYNC
|
| 51 |
|
|
SET_PARAMETER register_portb_output_of_memory_primitives false
|
| 52 |
|
|
SET_PARAMETER use_rsta_pin false
|
| 53 |
|
|
SET_PARAMETER port_b_enable_rate 100
|
| 54 |
|
|
SET_PARAMETER coe_file /home/alw/projects/vtachspartan/mainmemory.coe
|
| 55 |
|
|
SET_PARAMETER fill_remaining_memory_locations false
|
| 56 |
|
|
SET_PARAMETER axi_slave_type Memory_Slave
|
| 57 |
|
|
SET_PARAMETER axi_type AXI4_Full
|
| 58 |
|
|
SET_PARAMETER collision_warnings ALL
|
| 59 |
|
|
SET_ERROR_CODE 2
|
| 60 |
|
|
SET_ERROR_MSG CANCEL: Customization cancelled.
|
| 61 |
|
|
SET_ERROR_TEXT Finished initializing IP model.
|
