1 |
2 |
wd5gnr |
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2 |
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7 |
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8 |
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Message file "usenglish/ip.msg" wasn't found.
|
9 |
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10 |
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11 |
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0: (0,0) : 72x256 u:13
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12 |
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13 |
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14 |
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0: (0,0) : 72x256 u:13
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15 |
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16 |
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17 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_input_block.vhd" line 88: Size of operands are different : result is <false>.
|
18 |
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19 |
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20 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_input_block.vhd" line 88: Size of operands are different : result is <false>.
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21 |
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22 |
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23 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 91: Size of operands are different : result is <false>.
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24 |
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25 |
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26 |
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Reading MIF file at /home/alw/projects/vtachspartan/ipcore_dir/tmp/_cg/mainmem.mif
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27 |
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28 |
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29 |
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Memory initialization file (mainmem.mif) depth is smaller than memory depth.
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30 |
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31 |
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32 |
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Memory initialization file (mainmem.mif) has words wider than 13 bits, right-aligning.
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33 |
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34 |
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35 |
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Default data (0 hex) will persist where not overwritten by MIF file.
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36 |
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37 |
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38 |
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$Id: get_init_bmg_v6_2.c,v 1.1 2011/02/07 06:43:48 muruga Exp $
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39 |
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40 |
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41 |
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Reading MIF file at /home/alw/projects/vtachspartan/ipcore_dir/tmp/_cg/mainmem.mif
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42 |
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43 |
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44 |
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Memory initialization file (mainmem.mif) depth is smaller than memory depth.
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45 |
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46 |
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47 |
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Memory initialization file (mainmem.mif) has words wider than 13 bits, right-aligning.
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48 |
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49 |
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50 |
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Default data (0 hex) will persist where not overwritten by MIF file.
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51 |
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52 |
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53 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'rsta' of component 'blk_mem_gen_v6_2' is tied to default value.
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54 |
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55 |
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56 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'ena' of component 'blk_mem_gen_v6_2' is tied to default value.
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57 |
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58 |
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59 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'regcea' of component 'blk_mem_gen_v6_2' is tied to default value.
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60 |
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61 |
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62 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'clkb' of component 'blk_mem_gen_v6_2' is tied to default value.
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63 |
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64 |
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65 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'rstb' of component 'blk_mem_gen_v6_2' is tied to default value.
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66 |
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67 |
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68 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'enb' of component 'blk_mem_gen_v6_2' is tied to default value.
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69 |
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70 |
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71 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'regceb' of component 'blk_mem_gen_v6_2' is tied to default value.
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72 |
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73 |
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74 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'web' of component 'blk_mem_gen_v6_2' is tied to default value.
|
75 |
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76 |
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77 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'addrb' of component 'blk_mem_gen_v6_2' is tied to default value.
|
78 |
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79 |
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80 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'dinb' of component 'blk_mem_gen_v6_2' is tied to default value.
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81 |
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82 |
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83 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 'doutb' of component 'blk_mem_gen_v6_2'.
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84 |
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85 |
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86 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'injectsbiterr' of component 'blk_mem_gen_v6_2' is tied to default value.
|
87 |
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88 |
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89 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 'injectdbiterr' of component 'blk_mem_gen_v6_2' is tied to default value.
|
90 |
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91 |
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92 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 'sbiterr' of component 'blk_mem_gen_v6_2'.
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93 |
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94 |
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95 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 'dbiterr' of component 'blk_mem_gen_v6_2'.
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96 |
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97 |
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98 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 'rdaddrecc' of component 'blk_mem_gen_v6_2'.
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99 |
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100 |
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101 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_aclk' of component 'blk_mem_gen_v6_2' is tied to default value.
|
102 |
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103 |
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104 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_aresetn' of component 'blk_mem_gen_v6_2' is tied to default value.
|
105 |
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106 |
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107 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_awid' of component 'blk_mem_gen_v6_2' is tied to default value.
|
108 |
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109 |
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110 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_awaddr' of component 'blk_mem_gen_v6_2' is tied to default value.
|
111 |
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112 |
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113 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_awlen' of component 'blk_mem_gen_v6_2' is tied to default value.
|
114 |
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115 |
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116 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_awsize' of component 'blk_mem_gen_v6_2' is tied to default value.
|
117 |
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118 |
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119 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_awburst' of component 'blk_mem_gen_v6_2' is tied to default value.
|
120 |
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121 |
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122 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_awvalid' of component 'blk_mem_gen_v6_2' is tied to default value.
|
123 |
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124 |
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125 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_awready' of component 'blk_mem_gen_v6_2'.
|
126 |
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127 |
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128 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_wdata' of component 'blk_mem_gen_v6_2' is tied to default value.
|
129 |
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130 |
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131 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_wstrb' of component 'blk_mem_gen_v6_2' is tied to default value.
|
132 |
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133 |
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134 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_wlast' of component 'blk_mem_gen_v6_2' is tied to default value.
|
135 |
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136 |
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137 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_wvalid' of component 'blk_mem_gen_v6_2' is tied to default value.
|
138 |
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139 |
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140 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_wready' of component 'blk_mem_gen_v6_2'.
|
141 |
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142 |
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143 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_bid' of component 'blk_mem_gen_v6_2'.
|
144 |
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145 |
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146 |
|
|
"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_bresp' of component 'blk_mem_gen_v6_2'.
|
147 |
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148 |
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149 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_bvalid' of component 'blk_mem_gen_v6_2'.
|
150 |
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151 |
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152 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_bready' of component 'blk_mem_gen_v6_2' is tied to default value.
|
153 |
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154 |
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155 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_arid' of component 'blk_mem_gen_v6_2' is tied to default value.
|
156 |
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157 |
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158 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_araddr' of component 'blk_mem_gen_v6_2' is tied to default value.
|
159 |
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160 |
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161 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_arlen' of component 'blk_mem_gen_v6_2' is tied to default value.
|
162 |
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163 |
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164 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_arsize' of component 'blk_mem_gen_v6_2' is tied to default value.
|
165 |
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166 |
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167 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_arburst' of component 'blk_mem_gen_v6_2' is tied to default value.
|
168 |
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169 |
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170 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_arvalid' of component 'blk_mem_gen_v6_2' is tied to default value.
|
171 |
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172 |
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173 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_arready' of component 'blk_mem_gen_v6_2'.
|
174 |
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175 |
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176 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_rid' of component 'blk_mem_gen_v6_2'.
|
177 |
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178 |
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179 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_rdata' of component 'blk_mem_gen_v6_2'.
|
180 |
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181 |
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182 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_rresp' of component 'blk_mem_gen_v6_2'.
|
183 |
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184 |
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185 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_rlast' of component 'blk_mem_gen_v6_2'.
|
186 |
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187 |
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188 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_rvalid' of component 'blk_mem_gen_v6_2'.
|
189 |
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190 |
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191 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_rready' of component 'blk_mem_gen_v6_2' is tied to default value.
|
192 |
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193 |
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194 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_injectsbiterr' of component 'blk_mem_gen_v6_2' is tied to default value.
|
195 |
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196 |
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197 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected input port 's_axi_injectdbiterr' of component 'blk_mem_gen_v6_2' is tied to default value.
|
198 |
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199 |
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200 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_sbiterr' of component 'blk_mem_gen_v6_2'.
|
201 |
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202 |
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203 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_dbiterr' of component 'blk_mem_gen_v6_2'.
|
204 |
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205 |
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206 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/mainmem.vhd" line 152: Unconnected output port 's_axi_rdaddrecc' of component 'blk_mem_gen_v6_2'.
|
207 |
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208 |
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209 |
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0: (0,0) : 72x256 u:13
|
210 |
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211 |
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212 |
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0: (0,0) : 72x256 u:13
|
213 |
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214 |
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215 |
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_input_block.vhd" line 691: Size of operands are different : result is <false>.
|
216 |
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|
217 |
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218 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_input_block.vhd" line 707: Size of operands are different : result is <false>.
|
219 |
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220 |
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221 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1544: Size of operands are different : result is <false>.
|
222 |
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223 |
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224 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1557: Size of operands are different : result is <false>.
|
225 |
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226 |
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227 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_gen_prim_wrapper_s3_init.vhd" line 4239: Use of null array slice on signal <pad_addr_a9> is not supported.
|
228 |
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229 |
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230 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_gen_prim_wrapper_s3_init.vhd" line 4246: Use of null array slice on signal <pad_addr_b9> is not supported.
|
231 |
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232 |
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233 |
|
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"/home/alw/projects/vtachspartan/ipcore_dir/tmp/./_cg/_dbg/./blk_mem_gen_v6_2/blk_mem_gen_prim_wrapper_s3_init.vhd" line 4253: Use of null array slice on signal <full_din_a72> is not supported.
|
234 |
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|
235 |
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|
236 |
|
|
Input <ENA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
237 |
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|
238 |
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|
239 |
|
|
Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
240 |
|
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|
241 |
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|
242 |
|
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Output <INJECTSBITERR_I> is never assigned. Tied to value 0.
|
243 |
|
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|
244 |
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|
245 |
|
|
Input <RSTA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
246 |
|
|
|
247 |
|
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|
248 |
|
|
Input <RSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
249 |
|
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|
250 |
|
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|
251 |
|
|
Input <WEB<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
252 |
|
|
|
253 |
|
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|
254 |
|
|
Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
255 |
|
|
|
256 |
|
|
|
257 |
|
|
Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
258 |
|
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|
259 |
|
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|
260 |
|
|
Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
261 |
|
|
|
262 |
|
|
|
263 |
|
|
Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
264 |
|
|
|
265 |
|
|
|
266 |
|
|
Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
Output <INJECTDBITERR_I> is never assigned. Tied to value 0.
|
270 |
|
|
|
271 |
|
|
|
272 |
|
|
Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
273 |
|
|
|
274 |
|
|
|
275 |
|
|
Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
276 |
|
|
|
277 |
|
|
|
278 |
|
|
Output <DBITERR> is never assigned. Tied to value 0.
|
279 |
|
|
|
280 |
|
|
|
281 |
|
|
Input <RDADDRECC_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
282 |
|
|
|
283 |
|
|
|
284 |
|
|
Input <DOUTB_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
285 |
|
|
|
286 |
|
|
|
287 |
|
|
Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
288 |
|
|
|
289 |
|
|
|
290 |
|
|
Output <SBITERR> is never assigned. Tied to value 0.
|
291 |
|
|
|
292 |
|
|
|
293 |
|
|
Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
Output <RDADDRECC> is never assigned. Tied to value 0000000.
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
300 |
|
|
|
301 |
|
|
|
302 |
|
|
Signal <ERROR_INTERNAL> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
303 |
|
|
|
304 |
|
|
|
305 |
|
|
Signal <DECODER_DOUTB> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
306 |
|
|
|
307 |
|
|
|
308 |
|
|
Signal <DECODER_DOUTA> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
309 |
|
|
|
310 |
|
|
|
311 |
|
|
Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
327 |
|
|
|
328 |
|
|
|
329 |
|
|
Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
Signal <ram_ssrb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
333 |
|
|
|
334 |
|
|
|
335 |
|
|
Signal <pad_doutp_b> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
336 |
|
|
|
337 |
|
|
|
338 |
|
|
Signal <pad_doutp_a> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
339 |
|
|
|
340 |
|
|
|
341 |
|
|
Signal <pad_dout_b> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
Signal <pad_dout_a> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
Signal <pad_dinp_b> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
Signal <pad_dinp_a> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
351 |
|
|
|
352 |
|
|
|
353 |
|
|
Signal <pad_din_b> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
Signal <pad_din_a> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
Signal <full_dout_b> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
Signal <full_dout_a> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
Signal <full_din_b> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
Signal <full_din_a> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
Signal <doutb_i> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000000000000000000000000000000000000000000000.
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
Output <DBITERR> is never assigned. Tied to value 0.
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
Output <SBITERR> is never assigned. Tied to value 0.
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
384 |
|
|
|
385 |
|
|
|
386 |
|
|
Signal <doutb_pad<71:64>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
Signal <doutb_pad<62:56>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
Signal <doutb_pad<53:46>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
393 |
|
|
|
394 |
|
|
|
395 |
|
|
Signal <doutb_pad<44:38>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
Signal <doutb_pad<35:28>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
399 |
|
|
|
400 |
|
|
|
401 |
|
|
Signal <doutb_pad<26:20>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
Signal <doutb_pad<17:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
Signal <doutb_pad<8:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
408 |
|
|
|
409 |
|
|
|
410 |
|
|
Signal <douta_pad<71:64>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
411 |
|
|
|
412 |
|
|
|
413 |
|
|
Signal <douta_pad<62:56>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
Signal <douta_pad<53:46>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
Signal <douta_pad<44:38>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
420 |
|
|
|
421 |
|
|
|
422 |
|
|
Signal <douta_pad<35:28>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
Signal <douta_pad<26:20>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
Signal <douta_pad<17:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
Signal <douta_pad<8:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
Signal <dinb_pad<71:64>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
435 |
|
|
|
436 |
|
|
|
437 |
|
|
Signal <dinb_pad<62:56>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
Signal <dinb_pad<53:46>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
441 |
|
|
|
442 |
|
|
|
443 |
|
|
Signal <dinb_pad<44:38>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
444 |
|
|
|
445 |
|
|
|
446 |
|
|
Signal <dinb_pad<35:28>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
Signal <dinb_pad<26:20>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
450 |
|
|
|
451 |
|
|
|
452 |
|
|
Signal <dinb_pad<17:11>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
453 |
|
|
|
454 |
|
|
|
455 |
|
|
Signal <dinb_pad<8:2>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
456 |
|
|
|
457 |
|
|
|
458 |
|
|
Signal <dina_pad<71:64>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
459 |
|
|
|
460 |
|
|
|
461 |
|
|
Signal <dina_pad<62:56>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
462 |
|
|
|
463 |
|
|
|
464 |
|
|
Signal <dina_pad<53:46>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
Signal <dina_pad<44:38>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
468 |
|
|
|
469 |
|
|
|
470 |
|
|
Signal <dina_pad<35:28>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
Signal <dina_pad<26:20>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
Signal <dina_pad<17:11>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
477 |
|
|
|
478 |
|
|
|
479 |
|
|
Signal <dina_pad<8:2>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
|
480 |
|
|
|
481 |
|
|
|
482 |
|
|
Output <DBITERR> is never assigned. Tied to value 0.
|
483 |
|
|
|
484 |
|
|
|
485 |
|
|
Input <WEA<1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
Input <WEB<1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
489 |
|
|
|
490 |
|
|
|
491 |
|
|
Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
492 |
|
|
|
493 |
|
|
|
494 |
|
|
Output <SBITERR> is never assigned. Tied to value 0.
|
495 |
|
|
|
496 |
|
|
|
497 |
|
|
Output <RDADDRECC> is never assigned. Tied to value 0000000.
|
498 |
|
|
|
499 |
|
|
|
500 |
|
|
Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
501 |
|
|
|
502 |
|
|
|
503 |
|
|
Signal <sbiterr_sdp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
504 |
|
|
|
505 |
|
|
|
506 |
|
|
Signal <sbiterr_array> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
507 |
|
|
|
508 |
|
|
|
509 |
|
|
Signal <rst_enb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
510 |
|
|
|
511 |
|
|
|
512 |
|
|
Signal <rst_ena> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
513 |
|
|
|
514 |
|
|
|
515 |
|
|
Signal <rdaddrecc_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
516 |
|
|
|
517 |
|
|
|
518 |
|
|
Signal <rdaddrecc_out> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
Signal <rdaddrecc_lat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
Signal <rdaddrecc_last> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
525 |
|
|
|
526 |
|
|
|
527 |
|
|
Signal <rdaddrecc_in> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
528 |
|
|
|
529 |
|
|
|
530 |
|
|
Signal <ram_sbiterr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
531 |
|
|
|
532 |
|
|
|
533 |
|
|
Signal <ram_dbiterr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
534 |
|
|
|
535 |
|
|
|
536 |
|
|
Signal <mux_rstb<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
537 |
|
|
|
538 |
|
|
|
539 |
|
|
Signal <mux_rsta<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
540 |
|
|
|
541 |
|
|
|
542 |
|
|
Signal <mem_reg_rstb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
543 |
|
|
|
544 |
|
|
|
545 |
|
|
Signal <mem_reg_rsta> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
546 |
|
|
|
547 |
|
|
|
548 |
|
|
Signal <mem_lat_rstb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
549 |
|
|
|
550 |
|
|
|
551 |
|
|
Signal <mem_lat_rsta> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
552 |
|
|
|
553 |
|
|
|
554 |
|
|
Signal <dbiterr_sdp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
555 |
|
|
|
556 |
|
|
|
557 |
|
|
Signal <dbiterr_array> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
558 |
|
|
|
559 |
|
|
|
560 |
|
|
Signal <addrb_in> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
561 |
|
|
|
562 |
|
|
|
563 |
|
|
Output <S_AXI_RDADDRECC> is never assigned. Tied to value 0000000.
|
564 |
|
|
|
565 |
|
|
|
566 |
|
|
Input <S_ARESETN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
567 |
|
|
|
568 |
|
|
|
569 |
|
|
Input <S_AXI_AWSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
570 |
|
|
|
571 |
|
|
|
572 |
|
|
Input <S_AXI_ARADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
573 |
|
|
|
574 |
|
|
|
575 |
|
|
Input <S_AXI_WLAST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
576 |
|
|
|
577 |
|
|
|
578 |
|
|
Output <S_AXI_BID> is never assigned. Tied to value 0000.
|
579 |
|
|
|
580 |
|
|
|
581 |
|
|
Input <S_AXI_AWADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
582 |
|
|
|
583 |
|
|
|
584 |
|
|
Output <S_AXI_RRESP> is never assigned. Tied to value 00.
|
585 |
|
|
|
586 |
|
|
|
587 |
|
|
Output <S_AXI_RID> is never assigned. Tied to value 0000.
|
588 |
|
|
|
589 |
|
|
|
590 |
|
|
Output <S_AXI_SBITERR> is never assigned. Tied to value 0.
|
591 |
|
|
|
592 |
|
|
|
593 |
|
|
Output <S_AXI_BVALID> is never assigned. Tied to value 0.
|
594 |
|
|
|
595 |
|
|
|
596 |
|
|
Input <S_AXI_WVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
597 |
|
|
|
598 |
|
|
|
599 |
|
|
Output <S_AXI_RVALID> is never assigned. Tied to value 0.
|
600 |
|
|
|
601 |
|
|
|
602 |
|
|
Output <S_AXI_BRESP> is never assigned. Tied to value 00.
|
603 |
|
|
|
604 |
|
|
|
605 |
|
|
Input <S_AXI_AWVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
606 |
|
|
|
607 |
|
|
|
608 |
|
|
Input <S_AXI_BREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
609 |
|
|
|
610 |
|
|
|
611 |
|
|
Input <S_AXI_ARVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
612 |
|
|
|
613 |
|
|
|
614 |
|
|
Output <S_AXI_WREADY> is never assigned. Tied to value 0.
|
615 |
|
|
|
616 |
|
|
|
617 |
|
|
Input <S_AXI_INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
618 |
|
|
|
619 |
|
|
|
620 |
|
|
Input <S_AXI_RREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
621 |
|
|
|
622 |
|
|
|
623 |
|
|
Output <S_AXI_RDATA> is never assigned. Tied to value 0000000000000.
|
624 |
|
|
|
625 |
|
|
|
626 |
|
|
Input <S_AXI_AWID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
627 |
|
|
|
628 |
|
|
|
629 |
|
|
Output <S_AXI_AWREADY> is never assigned. Tied to value 0.
|
630 |
|
|
|
631 |
|
|
|
632 |
|
|
Input <S_AClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
633 |
|
|
|
634 |
|
|
|
635 |
|
|
Output <S_AXI_ARREADY> is never assigned. Tied to value 0.
|
636 |
|
|
|
637 |
|
|
|
638 |
|
|
Input <S_AXI_ARLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
639 |
|
|
|
640 |
|
|
|
641 |
|
|
Input <S_AXI_AWBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
642 |
|
|
|
643 |
|
|
|
644 |
|
|
Input <S_AXI_ARBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
645 |
|
|
|
646 |
|
|
|
647 |
|
|
Input <S_AXI_WDATA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
648 |
|
|
|
649 |
|
|
|
650 |
|
|
Input <S_AXI_ARSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
651 |
|
|
|
652 |
|
|
|
653 |
|
|
Output <S_AXI_RLAST> is never assigned. Tied to value 0.
|
654 |
|
|
|
655 |
|
|
|
656 |
|
|
Input <S_AXI_INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
657 |
|
|
|
658 |
|
|
|
659 |
|
|
Output <S_AXI_DBITERR> is never assigned. Tied to value 0.
|
660 |
|
|
|
661 |
|
|
|
662 |
|
|
Input <S_AXI_WSTRB<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
663 |
|
|
|
664 |
|
|
|
665 |
|
|
Input <S_AXI_AWLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
666 |
|
|
|
667 |
|
|
|
668 |
|
|
Input <S_AXI_ARID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
669 |
|
|
|
670 |
|
|
|
671 |
|
|
Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram of type RAMB16_S36_S36 has been replaced by RAMB16
|
672 |
|
|
|
673 |
|
|
|
674 |
|
|
HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
675 |
|
|
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
|