Running: /home/alw/projects/vtachspartan/bcdadd_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/alw/projects/vtachspartan/bcdadd_tb_isim_beh.wdb
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ISim O.61xd (signature 0xb4d1ced7)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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WARNING: For instance aneg/negplus/, width 17 of formal port a is not equal to width 16 of actual constant.
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WARNING: File "/home/alw/projects/vtachspartan/bcdadd.v" Line 3. For instance aneg/negplus/, width 17 of formal port z is not equal to width 16 of actual signal yn.
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WARNING: For instance bneg/negplus/, width 17 of formal port a is not equal to width 12 of actual constant.
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WARNING: File "/home/alw/projects/vtachspartan/bcdadd.v" Line 10. For instance bneg/negplus/, width 17 of formal port z is not equal to width 12 of actual signal yn.
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WARNING: For instance zneg/negplus/, width 17 of formal port a is not equal to width 16 of actual constant.
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WARNING: File "/home/alw/projects/vtachspartan/bcdadd.v" Line 3. For instance zneg/negplus/, width 17 of formal port z is not equal to width 16 of actual signal yn.
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Time resolution is 1 ps
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# onerror resume
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# wave add /
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# run 10000 us
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Simulator is doing circuit initialization process.
