| 1 |
2 |
wd5gnr |
Release 13.2 par O.61xd (lin64)
|
| 2 |
|
|
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
|
| 3 |
|
|
|
| 4 |
|
|
enterprise:: Sat May 25 07:43:38 2013
|
| 5 |
|
|
|
| 6 |
|
|
par -filter iseconfig/filter.filter -w -intstyle ise -pl high -rl high -xe n -t
|
| 7 |
|
|
1 top_map.ncd top.ncd top.pcf
|
| 8 |
|
|
|
| 9 |
|
|
|
| 10 |
|
|
Constraints file: top.pcf.
|
| 11 |
|
|
Loading device for application Rf_Device from file '3s1000.nph' in environment /opt/Xilinx/13.2/ISE_DS/ISE/.
|
| 12 |
|
|
"top" is an NCD, version 3.2, device xc3s1000, package ft256, speed -4
|
| 13 |
|
|
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
|
| 14 |
|
|
INFO:Security:54 - 'xc3s1000' is a WebPack part.
|
| 15 |
|
|
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
|
| 16 |
|
|
to function, but you no longer qualify for Xilinx software updates or new releases.
|
| 17 |
|
|
|
| 18 |
|
|
----------------------------------------------------------------------
|
| 19 |
|
|
|
| 20 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
|
| 21 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 22 |
|
|
|
| 23 |
|
|
|
| 24 |
|
|
Device speed data version: "PRODUCTION 1.39 2011-06-20".
|
| 25 |
|
|
|
| 26 |
|
|
|
| 27 |
|
|
|
| 28 |
|
|
Device Utilization Summary:
|
| 29 |
|
|
|
| 30 |
|
|
Number of BUFGMUXs 3 out of 8 37%
|
| 31 |
|
|
Number of DCMs 1 out of 4 25%
|
| 32 |
|
|
Number of External IOBs 32 out of 173 18%
|
| 33 |
|
|
Number of LOCed IOBs 32 out of 32 100%
|
| 34 |
|
|
|
| 35 |
|
|
Number of RAMB16s 1 out of 24 4%
|
| 36 |
|
|
Number of Slices 347 out of 7680 4%
|
| 37 |
|
|
Number of SLICEMs 0 out of 3840 0%
|
| 38 |
|
|
|
| 39 |
|
|
|
| 40 |
|
|
|
| 41 |
|
|
Overall effort level (-ol): Not applicable because -pl and -rl switches are used
|
| 42 |
|
|
Router effort level (-rl): High
|
| 43 |
|
|
|
| 44 |
|
|
Starting initial Timing Analysis. REAL time: 3 secs
|
| 45 |
|
|
Finished initial Timing Analysis. REAL time: 3 secs
|
| 46 |
|
|
|
| 47 |
|
|
Starting Router
|
| 48 |
|
|
|
| 49 |
|
|
|
| 50 |
|
|
Phase 1 : 2570 unrouted; REAL time: 3 secs
|
| 51 |
|
|
|
| 52 |
|
|
Phase 2 : 2338 unrouted; REAL time: 3 secs
|
| 53 |
|
|
|
| 54 |
|
|
Phase 3 : 500 unrouted; REAL time: 3 secs
|
| 55 |
|
|
|
| 56 |
|
|
Phase 4 : 500 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
| 57 |
|
|
|
| 58 |
|
|
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
| 59 |
|
|
|
| 60 |
|
|
Updating file: top.ncd with current fully routed design.
|
| 61 |
|
|
|
| 62 |
|
|
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
| 63 |
|
|
|
| 64 |
|
|
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
| 65 |
|
|
|
| 66 |
|
|
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
|
| 67 |
|
|
|
| 68 |
|
|
Total REAL time to Router completion: 4 secs
|
| 69 |
|
|
Total CPU time to Router completion: 4 secs
|
| 70 |
|
|
|
| 71 |
|
|
Partition Implementation Status
|
| 72 |
|
|
-------------------------------
|
| 73 |
|
|
|
| 74 |
|
|
No Partitions were found in this design.
|
| 75 |
|
|
|
| 76 |
|
|
-------------------------------
|
| 77 |
|
|
|
| 78 |
|
|
Generating "PAR" statistics.
|
| 79 |
|
|
|
| 80 |
|
|
**************************
|
| 81 |
|
|
Generating Clock Report
|
| 82 |
|
|
**************************
|
| 83 |
|
|
|
| 84 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 85 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 86 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 87 |
|
|
| clkdiv | BUFGMUX4| No | 177 | 0.380 | 1.131 |
|
| 88 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 89 |
|
|
| clkls | BUFGMUX0| No | 3 | 0.014 | 0.846 |
|
| 90 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 91 |
|
|
|
| 92 |
|
|
* Net Skew is the difference between the minimum and maximum routing
|
| 93 |
|
|
only delays for the net. Note this is different from Clock Skew which
|
| 94 |
|
|
is reported in TRCE timing report. Clock Skew is the difference between
|
| 95 |
|
|
the minimum and maximum path delays which includes logic delays.
|
| 96 |
|
|
|
| 97 |
|
|
* The fanout is the number of component pins not the individual BEL loads,
|
| 98 |
|
|
for example SLICE loads not FF loads.
|
| 99 |
|
|
|
| 100 |
|
|
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
|
| 101 |
|
|
|
| 102 |
|
|
Number of Timing Constraints that were not applied: 1
|
| 103 |
|
|
|
| 104 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 105 |
|
|
This may be due to a setup or hold violation.
|
| 106 |
|
|
|
| 107 |
|
|
----------------------------------------------------------------------------------------------------------
|
| 108 |
|
|
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
| 109 |
|
|
| | Slack | Achievable | Errors | Score
|
| 110 |
|
|
----------------------------------------------------------------------------------------------------------
|
| 111 |
|
|
TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH | MINLOWPULSE | 14.000ns| 6.000ns| 0| 0
|
| 112 |
|
|
50% | | | | |
|
| 113 |
|
|
----------------------------------------------------------------------------------------------------------
|
| 114 |
|
|
TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "c | SETUP | 23.477ns| 7.773ns| 0| 0
|
| 115 |
|
|
lockdll_CLKFX_BUF" TS_clk * 0.64 HIGH | HOLD | 1.282ns| | 0| 0
|
| 116 |
|
|
50% | | | | |
|
| 117 |
|
|
----------------------------------------------------------------------------------------------------------
|
| 118 |
|
|
|
| 119 |
|
|
|
| 120 |
|
|
Derived Constraint Report
|
| 121 |
|
|
Review Timing Report for more details on the following derived constraints.
|
| 122 |
|
|
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
|
| 123 |
|
|
or "Run Timing Analysis" from Timing Analyzer (timingan).
|
| 124 |
|
|
Derived Constraints for TS_clk
|
| 125 |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
| 126 |
|
|
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
| 127 |
|
|
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
| 128 |
|
|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
| 129 |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
| 130 |
|
|
|TS_clk | 20.000ns| 6.000ns| 4.975ns| 0| 0| 0| 14|
|
| 131 |
|
|
| TS_clockdll_CLKFX_BUF | 31.250ns| 7.773ns| N/A| 0| 0| 14| 0|
|
| 132 |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
| 133 |
|
|
|
| 134 |
|
|
All constraints were met.
|
| 135 |
|
|
|
| 136 |
|
|
|
| 137 |
|
|
Generating Pad Report.
|
| 138 |
|
|
|
| 139 |
|
|
All signals are completely routed.
|
| 140 |
|
|
|
| 141 |
|
|
Total REAL time to PAR completion: 4 secs
|
| 142 |
|
|
Total CPU time to PAR completion: 4 secs
|
| 143 |
|
|
|
| 144 |
|
|
Peak Memory Usage: 336 MB
|
| 145 |
|
|
|
| 146 |
|
|
Placer: Placement generated during map.
|
| 147 |
|
|
Routing: Completed - No errors found.
|
| 148 |
|
|
Timing: Completed - No errors found.
|
| 149 |
|
|
|
| 150 |
|
|
Number of error messages: 0
|
| 151 |
|
|
Number of warning messages: 0
|
| 152 |
|
|
Number of info messages: 0
|
| 153 |
|
|
|
| 154 |
|
|
Writing design to file top.ncd
|
| 155 |
|
|
|
| 156 |
|
|
|
| 157 |
|
|
|
| 158 |
|
|
PAR done!
|
