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wd5gnr |
Release 13.2 - xst O.61xd (lin64)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Reading design: top.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "top.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "top"
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Output Format : NGC
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Target Device : xc3s1000-4-ft256
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---- Source Options
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Top Module Name : top
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : Yes
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Move First FlipFlop Stage : YES
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Move Last FlipFlop Stage : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : False
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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---- Other Options
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Cores Search Directories : {"ipcore_dir" }
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "digitadd.v" in library work
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Compiling verilog file "usum.v" in library work
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Module compiled
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Compiling verilog file "bcdincr.v" in library work
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Module compiled
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Compiling verilog file "display.v" in library work
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Module compiled
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Compiling verilog file "bcdneg.v" in library work
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Module compiled
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Module compiled
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Compiling verilog file "ipcore_dir/mainmem.v" in library work
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Module compiled
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Compiling verilog file "io_output.v" in library work
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Module compiled
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Compiling verilog file "io_input.v" in library work
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Module compiled
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Compiling verilog file "debounce.v" in library work
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Module compiled
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Compiling verilog file "bcdadd.v" in library work
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Module compiled
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Compiling verilog file "memory.v" in library work
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Module compiled
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Compiling verilog file "mainclock.v" in library work
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Module compiled
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Compiling verilog file "alu.v" in library work
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Module compiled
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Compiling verilog file "vtach.v" in library work
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"top.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library with parameters.
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inittimer = "0011000011010100000"
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initval = "00000000000000000000000000000000"
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timerwidth = "00000000000000000000000000010011"
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library with parameters.
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clkfreq = "00000000000000000000000000010000"
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ctrbits = "00000000000000000000000000011000"
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dispfreq = "00000000000000000000000001100100"
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uplimit = "00000000000000001001110001000000"
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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Analyzing module in library .
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WARNING:Xst:2211 - "ipcore_dir/mainmem.v" line 18: Instantiating black box module .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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WARNING:Xst:1464 - "io_output.v" line 14: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.
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WARNING:Xst:864 - "io_output.v" line 14: Comparisons to 'X' or 'Z' are treated as always false.
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Module is correct for synthesis.
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Analyzing module in library .
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clkfreq = 32'sb00000000000000000000000000010000
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ctrbits = 32'sb00000000000000000000000000011000
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dispfreq = 32'sb00000000000000000000000001100100
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uplimit = 32'sb00000000000000001001110001000000
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Module is correct for synthesis.
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Analyzing module in library .
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inittimer = 19'b0011000011010100000
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initval = 32'sb00000000000000000000000000000000
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timerwidth = 32'sb00000000000000000000000000010011
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
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Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
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Set user-defined property "IBUF_LOW_PWR = TRUE" for instance in unit .
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Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
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Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
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Set user-defined property "CLKFX_DIVIDE = 25" for instance in unit .
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Set user-defined property "CLKFX_MULTIPLY = 16" for instance in unit .
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Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
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Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
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Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
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Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
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Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
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Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
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Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
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Set user-defined property "DSS_MODE = NONE" for instance in unit .
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Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
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Set user-defined property "FACTORY_JF = 8080" for instance in unit .
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Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
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Set user-defined property "SIM_MODE = SAFE" for instance in unit .
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Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit .
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "digitadd.v".
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Found 5-bit adder for signal .
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Found 5-bit adder for signal created at line 6.
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Summary:
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inferred 2 Adder/Subtractor(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "io_input.v".
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WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 13-bit tristate buffer for signal .
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Found 13-bit register for signal .
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Summary:
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inferred 13 D-type flip-flop(s).
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inferred 13 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "debounce.v".
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Found 1-bit register for signal .
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| 316 |
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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| 318 |
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Found 1-bit register for signal .
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Found 19-bit down counter for signal .
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Found 1-bit register for signal .
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Found 1-bit xor2 for signal .
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Summary:
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| 323 |
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inferred 1 Counter(s).
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inferred 5 D-type flip-flop(s).
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| 325 |
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Unit synthesized.
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| 326 |
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| 327 |
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| 328 |
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Synthesizing Unit .
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| 329 |
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Related source file is "display.v".
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| 330 |
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Found 1-bit register for signal .
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| 331 |
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Found 1-bit register for signal .
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| 332 |
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Found 1-bit register for signal .
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| 333 |
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Found 1-bit register for signal .
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| 334 |
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Found 1-bit register for signal .
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| 335 |
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Found 1-bit register for signal .
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| 336 |
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Found 1-bit register for signal .
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| 337 |
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Found 1-bit register for signal .
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| 338 |
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Found 1-bit register for signal .
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| 339 |
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 24-bit up counter for signal .
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Found 1-of-4 decoder for signal .
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Found 2-bit down counter for signal .
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Found 4-bit 4-to-1 multiplexer for signal .
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Summary:
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inferred 2 Counter(s).
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inferred 11 D-type flip-flop(s).
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inferred 4 Multiplexer(s).
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inferred 1 Decoder(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "memory.v".
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Found 13-bit tristate buffer for signal .
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Found 7-bit adder for signal .
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| 357 |
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Found 7-bit adder for signal created at line 16.
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| 358 |
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Summary:
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| 359 |
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inferred 2 Adder/Subtractor(s).
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| 360 |
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inferred 13 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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| 365 |
|
|
Related source file is "mainclock.v".
|
| 366 |
|
|
Unit synthesized.
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
Synthesizing Unit .
|
| 370 |
|
|
Related source file is "usum.v".
|
| 371 |
|
|
Found 1-bit adder for signal >.
|
| 372 |
|
|
Found 1-bit adder for signal created at line 10.
|
| 373 |
|
|
Summary:
|
| 374 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 375 |
|
|
Unit synthesized.
|
| 376 |
|
|
|
| 377 |
|
|
|
| 378 |
|
|
Synthesizing Unit .
|
| 379 |
|
|
Related source file is "io_output.v".
|
| 380 |
|
|
Found 13-bit register for signal .
|
| 381 |
|
|
Summary:
|
| 382 |
|
|
inferred 13 D-type flip-flop(s).
|
| 383 |
|
|
Unit synthesized.
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
Synthesizing Unit .
|
| 387 |
|
|
Related source file is "bcdincr.v".
|
| 388 |
|
|
Unit synthesized.
|
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
|
|
Synthesizing Unit .
|
| 392 |
|
|
Related source file is "bcdneg.v".
|
| 393 |
|
|
Found 4-bit adder for signal <$sub0000> created at line 13.
|
| 394 |
|
|
Found 4-bit adder for signal <$sub0001> created at line 13.
|
| 395 |
|
|
Found 4-bit adder for signal <$sub0002> created at line 13.
|
| 396 |
|
|
Found 4-bit adder for signal <$sub0003> created at line 13.
|
| 397 |
|
|
Summary:
|
| 398 |
|
|
inferred 4 Adder/Subtractor(s).
|
| 399 |
|
|
Unit synthesized.
|
| 400 |
|
|
|
| 401 |
|
|
|
| 402 |
|
|
Synthesizing Unit .
|
| 403 |
|
|
Related source file is "bcdneg.v".
|
| 404 |
|
|
Found 4-bit adder for signal <$sub0000> created at line 21.
|
| 405 |
|
|
Found 4-bit adder for signal <$sub0001> created at line 21.
|
| 406 |
|
|
Found 4-bit adder for signal <$sub0002> created at line 21.
|
| 407 |
|
|
Summary:
|
| 408 |
|
|
inferred 3 Adder/Subtractor(s).
|
| 409 |
|
|
Unit synthesized.
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
Synthesizing Unit .
|
| 413 |
|
|
Related source file is "bcdadd.v".
|
| 414 |
|
|
Unit synthesized.
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
Synthesizing Unit .
|
| 418 |
|
|
Related source file is "alu.v".
|
| 419 |
|
|
Found 13-bit tristate buffer for signal .
|
| 420 |
|
|
Found 1-bit register for signal .
|
| 421 |
|
|
Found 1-bit register for signal .
|
| 422 |
|
|
Found 17-bit register for signal .
|
| 423 |
|
|
Found 1-bit register for signal .
|
| 424 |
|
|
Found 1-bit register for signal .
|
| 425 |
|
|
Summary:
|
| 426 |
|
|
inferred 21 D-type flip-flop(s).
|
| 427 |
|
|
inferred 26 Tristate(s).
|
| 428 |
|
|
Unit synthesized.
|
| 429 |
|
|
|
| 430 |
|
|
|
| 431 |
|
|
Synthesizing Unit .
|
| 432 |
|
|
Related source file is "vtach.v".
|
| 433 |
|
|
Found 1-bit register for signal .
|
| 434 |
|
|
Found 8-bit register for signal .
|
| 435 |
|
|
Found 1-bit register for signal .
|
| 436 |
|
|
Found 4-bit register for signal .
|
| 437 |
|
|
Found 12-bit register for signal .
|
| 438 |
|
|
Found 1-bit register for signal .
|
| 439 |
|
|
Found 1-bit register for signal .
|
| 440 |
|
|
Summary:
|
| 441 |
|
|
inferred 28 D-type flip-flop(s).
|
| 442 |
|
|
Unit synthesized.
|
| 443 |
|
|
|
| 444 |
|
|
|
| 445 |
|
|
=========================================================================
|
| 446 |
|
|
HDL Synthesis Report
|
| 447 |
|
|
|
| 448 |
|
|
Macro Statistics
|
| 449 |
|
|
# Adders/Subtractors : 63
|
| 450 |
|
|
1-bit adder : 10
|
| 451 |
|
|
4-bit adder : 11
|
| 452 |
|
|
5-bit adder : 40
|
| 453 |
|
|
7-bit adder : 2
|
| 454 |
|
|
# Counters : 5
|
| 455 |
|
|
19-bit down counter : 3
|
| 456 |
|
|
2-bit down counter : 1
|
| 457 |
|
|
24-bit up counter : 1
|
| 458 |
|
|
# Registers : 40
|
| 459 |
|
|
1-bit register : 34
|
| 460 |
|
|
12-bit register : 1
|
| 461 |
|
|
13-bit register : 2
|
| 462 |
|
|
17-bit register : 1
|
| 463 |
|
|
4-bit register : 1
|
| 464 |
|
|
8-bit register : 1
|
| 465 |
|
|
# Multiplexers : 1
|
| 466 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 467 |
|
|
# Decoders : 1
|
| 468 |
|
|
1-of-4 decoder : 1
|
| 469 |
|
|
# Tristates : 4
|
| 470 |
|
|
13-bit tristate buffer : 4
|
| 471 |
|
|
# Xors : 3
|
| 472 |
|
|
1-bit xor2 : 3
|
| 473 |
|
|
|
| 474 |
|
|
=========================================================================
|
| 475 |
|
|
|
| 476 |
|
|
=========================================================================
|
| 477 |
|
|
* Advanced HDL Synthesis *
|
| 478 |
|
|
=========================================================================
|
| 479 |
|
|
|
| 480 |
|
|
Reading core .
|
| 481 |
|
|
Loading core for timing and area information for instance .
|
| 482 |
|
|
WARNING:Xst:1290 - Hierarchical block is unconnected in block .
|
| 483 |
|
|
It will be removed from the design.
|
| 484 |
|
|
WARNING:Xst:1290 - Hierarchical block is unconnected in block .
|
| 485 |
|
|
It will be removed from the design.
|
| 486 |
|
|
WARNING:Xst:1290 - Hierarchical block is unconnected in block .
|
| 487 |
|
|
It will be removed from the design.
|
| 488 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed :
|
| 489 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
| 490 |
|
|
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
|
| 491 |
|
|
|
| 492 |
|
|
=========================================================================
|
| 493 |
|
|
Advanced HDL Synthesis Report
|
| 494 |
|
|
|
| 495 |
|
|
Macro Statistics
|
| 496 |
|
|
# Adders/Subtractors : 38
|
| 497 |
|
|
1-bit adder carry in : 5
|
| 498 |
|
|
4-bit adder : 11
|
| 499 |
|
|
5-bit adder carry in : 20
|
| 500 |
|
|
7-bit adder : 2
|
| 501 |
|
|
# Counters : 5
|
| 502 |
|
|
19-bit down counter : 3
|
| 503 |
|
|
2-bit down counter : 1
|
| 504 |
|
|
24-bit up counter : 1
|
| 505 |
|
|
# Registers : 96
|
| 506 |
|
|
Flip-Flops : 96
|
| 507 |
|
|
# Multiplexers : 1
|
| 508 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 509 |
|
|
# Decoders : 1
|
| 510 |
|
|
1-of-4 decoder : 1
|
| 511 |
|
|
# Xors : 3
|
| 512 |
|
|
1-bit xor2 : 3
|
| 513 |
|
|
|
| 514 |
|
|
=========================================================================
|
| 515 |
|
|
|
| 516 |
|
|
=========================================================================
|
| 517 |
|
|
* Low Level Synthesis *
|
| 518 |
|
|
=========================================================================
|
| 519 |
|
|
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram of type RAMB16_S36_S36 has been replaced by RAMB16
|
| 520 |
|
|
WARNING:Xst:2040 - Unit alu: 13 multi-source signals are replaced by logic (pull-up yes): dbus<0>, dbus<10>, dbus<11>, dbus<12>, dbus<1>, dbus<2>, dbus<3>, dbus<4>, dbus<5>, dbus<6>, dbus<7>, dbus<8>, dbus<9>.
|
| 521 |
|
|
WARNING:Xst:2042 - Unit memory: 13 internal tristates are replaced by logic (pull-up yes): dbus<0>, dbus<10>, dbus<11>, dbus<12>, dbus<1>, dbus<2>, dbus<3>, dbus<4>, dbus<5>, dbus<6>, dbus<7>, dbus<8>, dbus<9>.
|
| 522 |
|
|
WARNING:Xst:2042 - Unit io_input: 13 internal tristates are replaced by logic (pull-up yes): value<0>, value<10>, value<11>, value<12>, value<1>, value<2>, value<3>, value<4>, value<5>, value<6>, value<7>, value<8>, value<9>.
|
| 523 |
|
|
|
| 524 |
|
|
Optimizing unit ...
|
| 525 |
|
|
|
| 526 |
|
|
Optimizing unit ...
|
| 527 |
|
|
|
| 528 |
|
|
Optimizing unit ...
|
| 529 |
|
|
|
| 530 |
|
|
Optimizing unit ...
|
| 531 |
|
|
|
| 532 |
|
|
Optimizing unit ...
|
| 533 |
|
|
|
| 534 |
|
|
Optimizing unit ...
|
| 535 |
|
|
|
| 536 |
|
|
Optimizing unit ...
|
| 537 |
|
|
|
| 538 |
|
|
Optimizing unit ...
|
| 539 |
|
|
|
| 540 |
|
|
Mapping all equations...
|
| 541 |
|
|
Building and optimizing final netlist ...
|
| 542 |
|
|
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 4.
|
| 543 |
|
|
INFO:Xst:2260 - The FF/Latch LogicTrst18_SW0_SW0_FRB> in Unit is equivalent to the following 3 FFs/Latches : LogicTrst18_SW0_SW0_FRB> LogicTrst18_SW0_SW0_FRB> LogicTrst181_SW0_SW0_FRB>
|
| 544 |
|
|
INFO:Xst:2261 - The FF/Latch LogicTrst18_SW0_SW0_FRB> in Unit is equivalent to the following 3 FFs/Latches, which will be removed : LogicTrst18_SW0_SW0_FRB> LogicTrst18_SW0_SW0_FRB> LogicTrst181_SW0_SW0_FRB>
|
| 545 |
|
|
|
| 546 |
|
|
Pipelining and Register Balancing Report ...
|
| 547 |
|
|
|
| 548 |
|
|
Processing Unit :
|
| 549 |
|
|
Register(s) execunit/acc_0 has(ve) been forward balanced into : execunit/adder/aneg/Madd__not0003<0>1_FRB.
|
| 550 |
|
|
Register(s) execunit/halt_not000111_FRB ir_8 execunit/memwrite_or000011_FRB ir_11 has(ve) been forward balanced into : dbus<2>LogicTrst18_SW0_SW0_FRB.
|
| 551 |
|
|
Register(s) execunit/memwrite_or000011_FRB ir_8 ir_11 execunit/halt_not000111_FRB has(ve) been forward balanced into : dbus<0>LogicTrst11_SW0_SW0_FRB.
|
| 552 |
|
|
Register(s) ir_9 ir_10 ir_11 has(ve) been forward balanced into : execunit/memwrite_or000011_FRB.
|
| 553 |
|
|
Register(s) ir_9 ir_10 ir_8 has(ve) been forward balanced into : execunit/halt_not000111_FRB.
|
| 554 |
|
|
Register(s) execunit/acc_10 has(ve) been backward balanced into : execunit/acc_10_BRB0 execunit/acc_10_BRB3 execunit/acc_10_BRB4 execunit/acc_10_BRB5.
|
| 555 |
|
|
Register(s) execunit/acc_11 has(ve) been backward balanced into : execunit/acc_11_BRB0 execunit/acc_11_BRB1 execunit/acc_11_BRB2 execunit/acc_11_BRB3 execunit/acc_11_BRB4 execunit/acc_11_BRB6 execunit/acc_11_BRB7.
|
| 556 |
|
|
Register(s) execunit/acc_12 has(ve) been backward balanced into : execunit/acc_12_BRB0 execunit/acc_12_BRB2 execunit/acc_12_BRB3 execunit/acc_12_BRB4 execunit/acc_12_BRB5 execunit/acc_12_BRB6.
|
| 557 |
|
|
Register(s) execunit/acc_13 has(ve) been backward balanced into : execunit/acc_13_BRB0 execunit/acc_13_BRB1 execunit/acc_13_BRB2 execunit/acc_13_BRB3 execunit/acc_13_BRB4 execunit/acc_13_BRB7 .
|
| 558 |
|
|
Register(s) execunit/acc_14 has(ve) been backward balanced into : execunit/acc_14_BRB3 execunit/acc_14_BRB6 execunit/acc_14_BRB7 .
|
| 559 |
|
|
Register(s) execunit/acc_15 has(ve) been backward balanced into : execunit/acc_15_BRB2 execunit/acc_15_BRB3 execunit/acc_15_BRB6 execunit/acc_15_BRB7 execunit/acc_15_BRB11 execunit/acc_15_BRB12 execunit/acc_15_BRB13.
|
| 560 |
|
|
Register(s) execunit/acc_16 has(ve) been backward balanced into : execunit/acc_16_BRB1 execunit/acc_16_BRB3 execunit/acc_16_BRB4 execunit/acc_16_BRB5 execunit/acc_16_BRB8 execunit/acc_16_BRB10 execunit/acc_16_BRB11 execunit/acc_16_BRB16 execunit/acc_16_BRB17.
|
| 561 |
|
|
Register(s) execunit/acc_4 has(ve) been backward balanced into : execunit/acc_4_BRB0 execunit/acc_4_BRB3 execunit/acc_4_BRB4 execunit/acc_4_BRB5.
|
| 562 |
|
|
Register(s) execunit/acc_5 has(ve) been backward balanced into : execunit/acc_5_BRB0 execunit/acc_5_BRB3 execunit/acc_5_BRB4 execunit/acc_5_BRB5.
|
| 563 |
|
|
Register(s) execunit/acc_6 has(ve) been backward balanced into : execunit/acc_6_BRB0 execunit/acc_6_BRB3 execunit/acc_6_BRB4 execunit/acc_6_BRB5.
|
| 564 |
|
|
Register(s) execunit/acc_7 has(ve) been backward balanced into : execunit/acc_7_BRB0 execunit/acc_7_BRB3 execunit/acc_7_BRB4 execunit/acc_7_BRB5.
|
| 565 |
|
|
Register(s) execunit/acc_8 has(ve) been backward balanced into : execunit/acc_8_BRB0 execunit/acc_8_BRB3 execunit/acc_8_BRB4 execunit/acc_8_BRB5.
|
| 566 |
|
|
Register(s) execunit/acc_9 has(ve) been backward balanced into : execunit/acc_9_BRB0 execunit/acc_9_BRB3 execunit/acc_9_BRB4 .
|
| 567 |
|
|
Unit processed.
|
| 568 |
|
|
FlipFlop ir_11 has been replicated 1 time(s)
|
| 569 |
|
|
|
| 570 |
|
|
Final Macro Processing ...
|
| 571 |
|
|
|
| 572 |
|
|
=========================================================================
|
| 573 |
|
|
Final Register Report
|
| 574 |
|
|
|
| 575 |
|
|
Macro Statistics
|
| 576 |
|
|
# Registers : 237
|
| 577 |
|
|
Flip-Flops : 237
|
| 578 |
|
|
|
| 579 |
|
|
=========================================================================
|
| 580 |
|
|
|
| 581 |
|
|
=========================================================================
|
| 582 |
|
|
* Partition Report *
|
| 583 |
|
|
=========================================================================
|
| 584 |
|
|
|
| 585 |
|
|
Partition Implementation Status
|
| 586 |
|
|
-------------------------------
|
| 587 |
|
|
|
| 588 |
|
|
No Partitions were found in this design.
|
| 589 |
|
|
|
| 590 |
|
|
-------------------------------
|
| 591 |
|
|
|
| 592 |
|
|
=========================================================================
|
| 593 |
|
|
* Final Report *
|
| 594 |
|
|
=========================================================================
|
| 595 |
|
|
Final Results
|
| 596 |
|
|
RTL Top Level Output File Name : top.ngr
|
| 597 |
|
|
Top Level Output File Name : top
|
| 598 |
|
|
Output Format : NGC
|
| 599 |
|
|
Optimization Goal : Speed
|
| 600 |
|
|
Keep Hierarchy : No
|
| 601 |
|
|
|
| 602 |
|
|
Design Statistics
|
| 603 |
|
|
# IOs : 32
|
| 604 |
|
|
|
| 605 |
|
|
Cell Usage :
|
| 606 |
|
|
# BELS : 952
|
| 607 |
|
|
# GND : 3
|
| 608 |
|
|
# INV : 11
|
| 609 |
|
|
# LUT1 : 34
|
| 610 |
|
|
# LUT2 : 59
|
| 611 |
|
|
# LUT2_L : 1
|
| 612 |
|
|
# LUT3 : 135
|
| 613 |
|
|
# LUT3_D : 4
|
| 614 |
|
|
# LUT3_L : 2
|
| 615 |
|
|
# LUT4 : 312
|
| 616 |
|
|
# LUT4_D : 18
|
| 617 |
|
|
# LUT4_L : 8
|
| 618 |
|
|
# MUXCY : 166
|
| 619 |
|
|
# MUXF5 : 48
|
| 620 |
|
|
# VCC : 2
|
| 621 |
|
|
# XORCY : 149
|
| 622 |
|
|
# FlipFlops/Latches : 237
|
| 623 |
|
|
# FD : 11
|
| 624 |
|
|
# FDC : 79
|
| 625 |
|
|
# FDCE : 3
|
| 626 |
|
|
# FDE : 83
|
| 627 |
|
|
# FDP : 25
|
| 628 |
|
|
# FDPE : 2
|
| 629 |
|
|
# FDR : 1
|
| 630 |
|
|
# FDRE : 18
|
| 631 |
|
|
# FDRS : 10
|
| 632 |
|
|
# FDS : 1
|
| 633 |
|
|
# FDSE : 4
|
| 634 |
|
|
# RAMS : 1
|
| 635 |
|
|
# RAMB16 : 1
|
| 636 |
|
|
# Clock Buffers : 3
|
| 637 |
|
|
# BUFG : 3
|
| 638 |
|
|
# IO Buffers : 32
|
| 639 |
|
|
# IBUF : 12
|
| 640 |
|
|
# IBUFG : 1
|
| 641 |
|
|
# OBUF : 19
|
| 642 |
|
|
# DCMs : 1
|
| 643 |
|
|
# DCM : 1
|
| 644 |
|
|
=========================================================================
|
| 645 |
|
|
|
| 646 |
|
|
Device utilization summary:
|
| 647 |
|
|
---------------------------
|
| 648 |
|
|
|
| 649 |
|
|
Selected Device : 3s1000ft256-4
|
| 650 |
|
|
|
| 651 |
|
|
Number of Slices: 317 out of 7680 4%
|
| 652 |
|
|
Number of Slice Flip Flops: 237 out of 15360 1%
|
| 653 |
|
|
Number of 4 input LUTs: 584 out of 15360 3%
|
| 654 |
|
|
Number of IOs: 32
|
| 655 |
|
|
Number of bonded IOBs: 32 out of 173 18%
|
| 656 |
|
|
Number of BRAMs: 1 out of 24 4%
|
| 657 |
|
|
Number of GCLKs: 3 out of 8 37%
|
| 658 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 659 |
|
|
|
| 660 |
|
|
---------------------------
|
| 661 |
|
|
Partition Resource Summary:
|
| 662 |
|
|
---------------------------
|
| 663 |
|
|
|
| 664 |
|
|
No Partitions were found in this design.
|
| 665 |
|
|
|
| 666 |
|
|
---------------------------
|
| 667 |
|
|
|
| 668 |
|
|
|
| 669 |
|
|
=========================================================================
|
| 670 |
|
|
TIMING REPORT
|
| 671 |
|
|
|
| 672 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
| 673 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
| 674 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
| 675 |
|
|
|
| 676 |
|
|
Clock Information:
|
| 677 |
|
|
------------------
|
| 678 |
|
|
-----------------------------------+------------------------+-------+
|
| 679 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 680 |
|
|
-----------------------------------+------------------------+-------+
|
| 681 |
|
|
clk | clockdll/DCM_INST:CLKFX| 2 |
|
| 682 |
|
|
clkdiv1 | BUFG | 236 |
|
| 683 |
|
|
-----------------------------------+------------------------+-------+
|
| 684 |
|
|
|
| 685 |
|
|
Asynchronous Control Signals Information:
|
| 686 |
|
|
----------------------------------------
|
| 687 |
|
|
-----------------------------------+-----------------------------------+-------+
|
| 688 |
|
|
Control Signal | Buffer(FF name) | Load |
|
| 689 |
|
|
-----------------------------------+-----------------------------------+-------+
|
| 690 |
|
|
reset(reset:Q) | NONE(execunit/out/leds/oDigitLeft)| 109 |
|
| 691 |
|
|
-----------------------------------+-----------------------------------+-------+
|
| 692 |
|
|
|
| 693 |
|
|
Timing Summary:
|
| 694 |
|
|
---------------
|
| 695 |
|
|
Speed Grade: -4
|
| 696 |
|
|
|
| 697 |
|
|
Minimum period: 29.957ns (Maximum Frequency: 33.381MHz)
|
| 698 |
|
|
Minimum input arrival time before clock: 10.357ns
|
| 699 |
|
|
Maximum output required time after clock: 11.416ns
|
| 700 |
|
|
Maximum combinational path delay: No path found
|
| 701 |
|
|
|
| 702 |
|
|
Timing Detail:
|
| 703 |
|
|
--------------
|
| 704 |
|
|
All values displayed in nanoseconds (ns)
|
| 705 |
|
|
|
| 706 |
|
|
=========================================================================
|
| 707 |
|
|
Timing constraint: Default period analysis for Clock 'clk'
|
| 708 |
|
|
Clock period: 1.679ns (frequency: 595.692MHz)
|
| 709 |
|
|
Total number of paths / destination ports: 1 / 1
|
| 710 |
|
|
-------------------------------------------------------------------------
|
| 711 |
|
|
Delay: 2.623ns (Levels of Logic = 0)
|
| 712 |
|
|
Source: clkdiv (FF)
|
| 713 |
|
|
Destination: clkdiv (FF)
|
| 714 |
|
|
Source Clock: clk rising 0.6X
|
| 715 |
|
|
Destination Clock: clk rising 0.6X
|
| 716 |
|
|
|
| 717 |
|
|
Data Path: clkdiv to clkdiv
|
| 718 |
|
|
Gate Net
|
| 719 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 720 |
|
|
---------------------------------------- ------------
|
| 721 |
|
|
FDR:C->Q 2 0.720 0.877 clkdiv (clkdiv1)
|
| 722 |
|
|
FDR:R 1.026 clkdiv
|
| 723 |
|
|
----------------------------------------
|
| 724 |
|
|
Total 2.623ns (1.746ns logic, 0.877ns route)
|
| 725 |
|
|
(66.6% logic, 33.4% route)
|
| 726 |
|
|
|
| 727 |
|
|
=========================================================================
|
| 728 |
|
|
Timing constraint: Default period analysis for Clock 'clkdiv1'
|
| 729 |
|
|
Clock period: 29.957ns (frequency: 33.381MHz)
|
| 730 |
|
|
Total number of paths / destination ports: 206561462 / 375
|
| 731 |
|
|
-------------------------------------------------------------------------
|
| 732 |
|
|
Delay: 29.957ns (Levels of Logic = 24)
|
| 733 |
|
|
Source: clkphase_0 (FF)
|
| 734 |
|
|
Destination: execunit/acc_3 (FF)
|
| 735 |
|
|
Source Clock: clkdiv1 rising
|
| 736 |
|
|
Destination Clock: clkdiv1 rising
|
| 737 |
|
|
|
| 738 |
|
|
Data Path: clkphase_0 to execunit/acc_3
|
| 739 |
|
|
Gate Net
|
| 740 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 741 |
|
|
---------------------------------------- ------------
|
| 742 |
|
|
FDS:C->Q 13 0.720 1.509 clkphase_0 (clkphase_0)
|
| 743 |
|
|
LUT4:I0->O 15 0.551 1.256 ir_cmp_eq00001_1 (ir_cmp_eq00001)
|
| 744 |
|
|
LUT3:I2->O 18 0.551 1.443 xmemoe1 (xmemoe)
|
| 745 |
|
|
LUT4:I3->O 7 0.551 1.405 dbus<2>LogicTrst18 (dbus<2>)
|
| 746 |
|
|
LUT2:I0->O 1 0.551 0.000 execunit/adder/bneg/Madd__sub0002_xor<2>11 (execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_lut<2>)
|
| 747 |
|
|
MUXCY:S->O 1 0.500 0.000 execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_cy<2> (execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_cy<2>)
|
| 748 |
|
|
XORCY:CI->O 4 0.904 0.943 execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_xor<3> (execunit/adder/bneg/negplus/inc/add1/temp<3>)
|
| 749 |
|
|
LUT4:I3->O 1 0.551 0.827 execunit/adder/bneg/y_1_mux000066 (execunit/adder/bneg/y_1_mux000066)
|
| 750 |
|
|
LUT4:I3->O 1 0.551 0.000 execunit/adder/adder/add1/Madd_temp_Madd_lut<1> (execunit/adder/adder/add1/Madd_temp_Madd_lut<1>)
|
| 751 |
|
|
MUXCY:S->O 1 0.500 0.000 execunit/adder/adder/add1/Madd_temp_Madd_cy<1> (execunit/adder/adder/add1/Madd_temp_Madd_cy<1>)
|
| 752 |
|
|
MUXCY:CI->O 1 0.064 0.000 execunit/adder/adder/add1/Madd_temp_Madd_cy<2> (execunit/adder/adder/add1/Madd_temp_Madd_cy<2>)
|
| 753 |
|
|
XORCY:CI->O 7 0.904 1.092 execunit/adder/adder/add1/Madd_temp_Madd_xor<3> (execunit/adder/adder/add1/temp<3>)
|
| 754 |
|
|
LUT4:I3->O 1 0.551 0.801 execunit/adder/adder/add1/cyout1 (execunit/adder/adder/c0)
|
| 755 |
|
|
MUXCY:CI->O 1 0.064 0.000 execunit/adder/adder/add2/Madd_temp_Madd_cy<0> (execunit/adder/adder/add2/Madd_temp_Madd_cy<0>)
|
| 756 |
|
|
XORCY:CI->O 7 0.904 1.261 execunit/adder/adder/add2/Madd_temp_Madd_xor<1> (execunit/adder/adder/add2/temp<1>)
|
| 757 |
|
|
LUT4:I1->O 1 0.551 0.801 execunit/adder/adder/add2/cyout1 (execunit/adder/adder/c1)
|
| 758 |
|
|
MUXCY:CI->O 1 0.064 0.000 execunit/adder/adder/add3/Madd_temp_Madd_cy<0> (execunit/adder/adder/add3/Madd_temp_Madd_cy<0>)
|
| 759 |
|
|
XORCY:CI->O 7 0.904 1.261 execunit/adder/adder/add3/Madd_temp_Madd_xor<1> (execunit/adder/adder/add3/temp<1>)
|
| 760 |
|
|
LUT4:I1->O 1 0.551 0.801 execunit/adder/adder/add3/cyout1 (execunit/adder/adder/c2)
|
| 761 |
|
|
MUXCY:CI->O 1 0.064 0.000 execunit/adder/adder/add4/Madd_temp_Madd_cy<0> (execunit/adder/adder/add4/Madd_temp_Madd_cy<0>)
|
| 762 |
|
|
MUXCY:CI->O 1 0.064 0.000 execunit/adder/adder/add4/Madd_temp_Madd_cy<1> (execunit/adder/adder/add4/Madd_temp_Madd_cy<1>)
|
| 763 |
|
|
XORCY:CI->O 8 0.904 1.151 execunit/adder/adder/add4/Madd_temp_Madd_xor<2> (execunit/adder/adder/add4/temp<2>)
|
| 764 |
|
|
LUT3:I2->O 1 0.551 0.827 execunit/adder/adder/add4/cyout1_SW0 (N108)
|
| 765 |
|
|
LUT4:I3->O 10 0.551 1.134 execunit/adder/adder/Madd_z<16>_Madd_xor<0>11 (execunit/adder/zout<16>)
|
| 766 |
|
|
MUXF5:S->O 1 0.621 0.000 execunit/acc_mux0000<3>107 (execunit/acc_mux0000<3>)
|
| 767 |
|
|
FDE:D 0.203 execunit/acc_3
|
| 768 |
|
|
----------------------------------------
|
| 769 |
|
|
Total 29.957ns (13.445ns logic, 16.512ns route)
|
| 770 |
|
|
(44.9% logic, 55.1% route)
|
| 771 |
|
|
|
| 772 |
|
|
=========================================================================
|
| 773 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkdiv1'
|
| 774 |
|
|
Total number of paths / destination ports: 29 / 26
|
| 775 |
|
|
-------------------------------------------------------------------------
|
| 776 |
|
|
Offset: 10.357ns (Levels of Logic = 7)
|
| 777 |
|
|
Source: sw<0> (PAD)
|
| 778 |
|
|
Destination: execunit/acc_0 (FF)
|
| 779 |
|
|
Destination Clock: clkdiv1 rising
|
| 780 |
|
|
|
| 781 |
|
|
Data Path: sw<0> to execunit/acc_0
|
| 782 |
|
|
Gate Net
|
| 783 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 784 |
|
|
---------------------------------------- ------------
|
| 785 |
|
|
IBUF:I->O 2 0.821 1.216 sw_0_IBUF (sw_0_IBUF)
|
| 786 |
|
|
LUT4:I0->O 1 0.551 1.140 execunit/acc_mux0000<0>8 (execunit/acc_mux0000<0>8)
|
| 787 |
|
|
LUT4:I0->O 1 0.551 0.827 execunit/acc_mux0000<0>52_SW0 (N340)
|
| 788 |
|
|
LUT4:I3->O 1 0.551 0.869 execunit/acc_mux0000<0>52 (execunit/acc_mux0000<0>52)
|
| 789 |
|
|
LUT4:I2->O 2 0.551 0.903 execunit/acc_mux0000<0>84 (execunit/acc_mux0000<0>84)
|
| 790 |
|
|
LUT4:I3->O 2 0.551 1.072 execunit/adder/zneg/y_0_mux00001_SW0 (N260)
|
| 791 |
|
|
LUT4:I1->O 1 0.551 0.000 execunit/acc_mux0000<0>112 (execunit/acc_mux0000<0>)
|
| 792 |
|
|
FDE:D 0.203 execunit/acc_0
|
| 793 |
|
|
----------------------------------------
|
| 794 |
|
|
Total 10.357ns (4.330ns logic, 6.027ns route)
|
| 795 |
|
|
(41.8% logic, 58.2% route)
|
| 796 |
|
|
|
| 797 |
|
|
=========================================================================
|
| 798 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv1'
|
| 799 |
|
|
Total number of paths / destination ports: 59 / 19
|
| 800 |
|
|
-------------------------------------------------------------------------
|
| 801 |
|
|
Offset: 11.416ns (Levels of Logic = 3)
|
| 802 |
|
|
Source: execunit/memwrite (FF)
|
| 803 |
|
|
Destination: led<4> (PAD)
|
| 804 |
|
|
Source Clock: clkdiv1 rising
|
| 805 |
|
|
|
| 806 |
|
|
Data Path: execunit/memwrite to led<4>
|
| 807 |
|
|
Gate Net
|
| 808 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 809 |
|
|
---------------------------------------- ------------
|
| 810 |
|
|
FDRS:C->Q 14 0.720 1.255 execunit/memwrite (execunit/memwrite)
|
| 811 |
|
|
LUT3_D:I2->O 18 0.551 1.612 execunit/dbus_and00001 (execunit/dbus_and0000)
|
| 812 |
|
|
LUT4:I1->O 8 0.551 1.083 memaddr<4>1 (led_4_OBUF)
|
| 813 |
|
|
OBUF:I->O 5.644 led_4_OBUF (led<4>)
|
| 814 |
|
|
----------------------------------------
|
| 815 |
|
|
Total 11.416ns (7.466ns logic, 3.950ns route)
|
| 816 |
|
|
(65.4% logic, 34.6% route)
|
| 817 |
|
|
|
| 818 |
|
|
=========================================================================
|
| 819 |
|
|
|
| 820 |
|
|
|
| 821 |
|
|
Total REAL time to Xst completion: 11.00 secs
|
| 822 |
|
|
Total CPU time to Xst completion: 11.44 secs
|
| 823 |
|
|
|
| 824 |
|
|
-->
|
| 825 |
|
|
|
| 826 |
|
|
|
| 827 |
|
|
Total memory usage is 371320 kilobytes
|
| 828 |
|
|
|
| 829 |
|
|
Number of errors : 0 ( 0 filtered)
|
| 830 |
|
|
Number of warnings : 20 ( 0 filtered)
|
| 831 |
|
|
Number of infos : 4 ( 0 filtered)
|
| 832 |
|
|
|
