| 1 |
2 |
wd5gnr |
--------------------------------------------------------------------------------
|
| 2 |
|
|
Release 13.2 Trace (lin64)
|
| 3 |
|
|
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
|
| 4 |
|
|
|
| 5 |
|
|
/opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -filter
|
| 6 |
|
|
/home/alw/projects/vtachspartan/iseconfig/filter.filter -intstyle ise -v 3 -s 4
|
| 7 |
|
|
-n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf vtach.ucf
|
| 8 |
|
|
|
| 9 |
|
|
Design file: top.ncd
|
| 10 |
|
|
Physical constraint file: top.pcf
|
| 11 |
|
|
Device,package,speed: xc3s1000,ft256,-4 (PRODUCTION 1.39 2011-06-20)
|
| 12 |
|
|
Report level: verbose report
|
| 13 |
|
|
|
| 14 |
|
|
Environment Variable Effect
|
| 15 |
|
|
-------------------- ------
|
| 16 |
|
|
NONE No environment variables were set
|
| 17 |
|
|
--------------------------------------------------------------------------------
|
| 18 |
|
|
|
| 19 |
|
|
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
| 20 |
|
|
option. All paths that are not constrained will be reported in the
|
| 21 |
|
|
unconstrained paths section(s) of the report.
|
| 22 |
|
|
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
| 23 |
|
|
a 50 Ohm transmission line loading model. For the details of this model,
|
| 24 |
|
|
and for more information on accounting for different loading conditions,
|
| 25 |
|
|
please see the device datasheet.
|
| 26 |
|
|
INFO:Timing:3390 - This architecture does not support a default System Jitter
|
| 27 |
|
|
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
|
| 28 |
|
|
Uncertainty calculation.
|
| 29 |
|
|
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
|
| 30 |
|
|
'Phase Error' calculations, these terms will be zero in the Clock
|
| 31 |
|
|
Uncertainty calculation. Please make appropriate modification to
|
| 32 |
|
|
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
|
| 33 |
|
|
Error.
|
| 34 |
|
|
|
| 35 |
|
|
================================================================================
|
| 36 |
|
|
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;
|
| 37 |
|
|
|
| 38 |
|
|
|
| 39 |
|
|
|
| 40 |
|
|
Minimum period is 6.000ns.
|
| 41 |
|
|
--------------------------------------------------------------------------------
|
| 42 |
|
|
|
| 43 |
|
|
Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;
|
| 44 |
|
|
--------------------------------------------------------------------------------
|
| 45 |
|
|
Slack: 14.000ns (period - (min low pulse limit / (low pulse / period)))
|
| 46 |
|
|
Period: 20.000ns
|
| 47 |
|
|
Low pulse: 10.000ns
|
| 48 |
|
|
Low pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)
|
| 49 |
|
|
Physical resource: clockdll/DCM_INST/CLKIN
|
| 50 |
|
|
Logical resource: clockdll/DCM_INST/CLKIN
|
| 51 |
|
|
Location pin: DCM_X0Y0.CLKIN
|
| 52 |
|
|
Clock network: clockdll/CLKIN_IBUFG
|
| 53 |
|
|
--------------------------------------------------------------------------------
|
| 54 |
|
|
Slack: 14.000ns (period - (min high pulse limit / (high pulse / period)))
|
| 55 |
|
|
Period: 20.000ns
|
| 56 |
|
|
High pulse: 10.000ns
|
| 57 |
|
|
High pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)
|
| 58 |
|
|
Physical resource: clockdll/DCM_INST/CLKIN
|
| 59 |
|
|
Logical resource: clockdll/DCM_INST/CLKIN
|
| 60 |
|
|
Location pin: DCM_X0Y0.CLKIN
|
| 61 |
|
|
Clock network: clockdll/CLKIN_IBUFG
|
| 62 |
|
|
--------------------------------------------------------------------------------
|
| 63 |
|
|
Slack: 14.013ns (period - min period limit)
|
| 64 |
|
|
Period: 20.000ns
|
| 65 |
|
|
Min period limit: 5.987ns (167.029MHz) (Tdcmpc)
|
| 66 |
|
|
Physical resource: clockdll/DCM_INST/CLKIN
|
| 67 |
|
|
Logical resource: clockdll/DCM_INST/CLKIN
|
| 68 |
|
|
Location pin: DCM_X0Y0.CLKIN
|
| 69 |
|
|
Clock network: clockdll/CLKIN_IBUFG
|
| 70 |
|
|
--------------------------------------------------------------------------------
|
| 71 |
|
|
|
| 72 |
|
|
================================================================================
|
| 73 |
|
|
Timing constraint: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF"
|
| 74 |
|
|
TS_clk * 0.64 HIGH 50%;
|
| 75 |
|
|
|
| 76 |
|
|
14 paths analyzed, 14 endpoints analyzed, 0 failing endpoints
|
| 77 |
|
|
|
| 78 |
|
|
Minimum period is 7.773ns.
|
| 79 |
|
|
--------------------------------------------------------------------------------
|
| 80 |
|
|
|
| 81 |
|
|
Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA0), 1 path
|
| 82 |
|
|
--------------------------------------------------------------------------------
|
| 83 |
|
|
Slack (setup path): 23.477ns (requirement - (data path - clock path skew + uncertainty))
|
| 84 |
|
|
Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 85 |
|
|
Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 86 |
|
|
Requirement: 31.250ns
|
| 87 |
|
|
Data Path Delay: 7.773ns (Levels of Logic = 3)
|
| 88 |
|
|
Clock Path Skew: 0.000ns
|
| 89 |
|
|
Source Clock: clkls rising at 0.000ns
|
| 90 |
|
|
Destination Clock: clkls rising at 31.250ns
|
| 91 |
|
|
Clock Uncertainty: 0.000ns
|
| 92 |
|
|
|
| 93 |
|
|
Maximum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 94 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 95 |
|
|
Logical Resource(s)
|
| 96 |
|
|
------------------------------------------------- -------------------
|
| 97 |
|
|
RAMB16_X1Y4.DOA0 Tbcko 2.394 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 98 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 99 |
|
|
SLICE_X75Y36.F4 net (fanout=1) 0.695 mem/outdata<0>
|
| 100 |
|
|
SLICE_X75Y36.X Tilo 0.551 execunit/out/val<1>
|
| 101 |
|
|
xmemoe1_SW0
|
| 102 |
|
|
SLICE_X75Y42.G2 net (fanout=1) 1.006 N103
|
| 103 |
|
|
SLICE_X75Y42.Y Tilo 0.551 execunit/adder/bneg/Madd__not0002<0>
|
| 104 |
|
|
dbus<0>LogicTrst4
|
| 105 |
|
|
SLICE_X74Y43.F2 net (fanout=3) 0.212 dbus<0>LogicTrst4
|
| 106 |
|
|
SLICE_X74Y43.X Tilo 0.608 ir<0>
|
| 107 |
|
|
dbus<0>LogicTrst18
|
| 108 |
|
|
RAMB16_X1Y4.DIA0 net (fanout=3) 1.272 dbus<0>
|
| 109 |
|
|
RAMB16_X1Y4.CLKA Tbdck 0.484 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 110 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 111 |
|
|
------------------------------------------------- ---------------------------
|
| 112 |
|
|
Total 7.773ns (4.588ns logic, 3.185ns route)
|
| 113 |
|
|
(59.0% logic, 41.0% route)
|
| 114 |
|
|
|
| 115 |
|
|
--------------------------------------------------------------------------------
|
| 116 |
|
|
|
| 117 |
|
|
Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAMB16_X1Y4.DIB8), 1 path
|
| 118 |
|
|
--------------------------------------------------------------------------------
|
| 119 |
|
|
Slack (setup path): 24.498ns (requirement - (data path - clock path skew + uncertainty))
|
| 120 |
|
|
Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAM)
|
| 121 |
|
|
Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAM)
|
| 122 |
|
|
Requirement: 31.250ns
|
| 123 |
|
|
Data Path Delay: 6.752ns (Levels of Logic = 1)
|
| 124 |
|
|
Clock Path Skew: 0.000ns
|
| 125 |
|
|
Source Clock: clkls rising at 0.000ns
|
| 126 |
|
|
Destination Clock: clkls rising at 31.250ns
|
| 127 |
|
|
Clock Uncertainty: 0.000ns
|
| 128 |
|
|
|
| 129 |
|
|
Maximum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B
|
| 130 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 131 |
|
|
Logical Resource(s)
|
| 132 |
|
|
------------------------------------------------- -------------------
|
| 133 |
|
|
RAMB16_X1Y4.DOB8 Tbcko 2.394 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 134 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B
|
| 135 |
|
|
SLICE_X69Y39.F3 net (fanout=2) 1.163 mem/outdata<9>
|
| 136 |
|
|
SLICE_X69Y39.X Tilo 0.551 ir<9>
|
| 137 |
|
|
dbus<9>LogicTrst
|
| 138 |
|
|
RAMB16_X1Y4.DIB8 net (fanout=10) 2.160 dbus<9>
|
| 139 |
|
|
RAMB16_X1Y4.CLKB Tbdck 0.484 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 140 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B
|
| 141 |
|
|
------------------------------------------------- ---------------------------
|
| 142 |
|
|
Total 6.752ns (3.429ns logic, 3.323ns route)
|
| 143 |
|
|
(50.8% logic, 49.2% route)
|
| 144 |
|
|
|
| 145 |
|
|
--------------------------------------------------------------------------------
|
| 146 |
|
|
|
| 147 |
|
|
Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA1), 1 path
|
| 148 |
|
|
--------------------------------------------------------------------------------
|
| 149 |
|
|
Slack (setup path): 24.512ns (requirement - (data path - clock path skew + uncertainty))
|
| 150 |
|
|
Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 151 |
|
|
Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 152 |
|
|
Requirement: 31.250ns
|
| 153 |
|
|
Data Path Delay: 6.738ns (Levels of Logic = 2)
|
| 154 |
|
|
Clock Path Skew: 0.000ns
|
| 155 |
|
|
Source Clock: clkls rising at 0.000ns
|
| 156 |
|
|
Destination Clock: clkls rising at 31.250ns
|
| 157 |
|
|
Clock Uncertainty: 0.000ns
|
| 158 |
|
|
|
| 159 |
|
|
Maximum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 160 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 161 |
|
|
Logical Resource(s)
|
| 162 |
|
|
------------------------------------------------- -------------------
|
| 163 |
|
|
RAMB16_X1Y4.DOA1 Tbcko 2.394 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 164 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 165 |
|
|
SLICE_X74Y43.G3 net (fanout=1) 1.156 mem/outdata<1>
|
| 166 |
|
|
SLICE_X74Y43.Y Tilo 0.608 ir<0>
|
| 167 |
|
|
dbus<1>LogicTrst18_SW1
|
| 168 |
|
|
SLICE_X74Y42.F3 net (fanout=2) 0.027 N101
|
| 169 |
|
|
SLICE_X74Y42.X Tilo 0.608 ir<1>
|
| 170 |
|
|
dbus<1>LogicTrst18
|
| 171 |
|
|
RAMB16_X1Y4.DIA1 net (fanout=6) 1.461 dbus<1>
|
| 172 |
|
|
RAMB16_X1Y4.CLKA Tbdck 0.484 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 173 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 174 |
|
|
------------------------------------------------- ---------------------------
|
| 175 |
|
|
Total 6.738ns (4.094ns logic, 2.644ns route)
|
| 176 |
|
|
(60.8% logic, 39.2% route)
|
| 177 |
|
|
|
| 178 |
|
|
--------------------------------------------------------------------------------
|
| 179 |
|
|
|
| 180 |
|
|
Hold Paths: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH
|
| 181 |
|
|
50%;
|
| 182 |
|
|
--------------------------------------------------------------------------------
|
| 183 |
|
|
|
| 184 |
|
|
Paths for end point clkdiv (SLICE_X40Y95.SR), 1 path
|
| 185 |
|
|
--------------------------------------------------------------------------------
|
| 186 |
|
|
Slack (hold path): 1.282ns (requirement - (clock path skew + uncertainty - data path))
|
| 187 |
|
|
Source: clkdiv (FF)
|
| 188 |
|
|
Destination: clkdiv (FF)
|
| 189 |
|
|
Requirement: 0.000ns
|
| 190 |
|
|
Data Path Delay: 1.282ns (Levels of Logic = 0)
|
| 191 |
|
|
Clock Path Skew: 0.000ns
|
| 192 |
|
|
Source Clock: clkls rising at 31.250ns
|
| 193 |
|
|
Destination Clock: clkls rising at 31.250ns
|
| 194 |
|
|
Clock Uncertainty: 0.000ns
|
| 195 |
|
|
|
| 196 |
|
|
Minimum Data Path: clkdiv to clkdiv
|
| 197 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 198 |
|
|
Logical Resource(s)
|
| 199 |
|
|
------------------------------------------------- -------------------
|
| 200 |
|
|
SLICE_X40Y95.YQ Tcko 0.576 clkdiv1
|
| 201 |
|
|
clkdiv
|
| 202 |
|
|
SLICE_X40Y95.SR net (fanout=2) 0.677 clkdiv1
|
| 203 |
|
|
SLICE_X40Y95.CLK Tcksr (-Th) -0.029 clkdiv1
|
| 204 |
|
|
clkdiv
|
| 205 |
|
|
------------------------------------------------- ---------------------------
|
| 206 |
|
|
Total 1.282ns (0.605ns logic, 0.677ns route)
|
| 207 |
|
|
(47.2% logic, 52.8% route)
|
| 208 |
|
|
|
| 209 |
|
|
--------------------------------------------------------------------------------
|
| 210 |
|
|
|
| 211 |
|
|
Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA24), 1 path
|
| 212 |
|
|
--------------------------------------------------------------------------------
|
| 213 |
|
|
Slack (hold path): 3.739ns (requirement - (clock path skew + uncertainty - data path))
|
| 214 |
|
|
Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 215 |
|
|
Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 216 |
|
|
Requirement: 0.000ns
|
| 217 |
|
|
Data Path Delay: 3.739ns (Levels of Logic = 2)
|
| 218 |
|
|
Clock Path Skew: 0.000ns
|
| 219 |
|
|
Source Clock: clkls rising at 31.250ns
|
| 220 |
|
|
Destination Clock: clkls rising at 31.250ns
|
| 221 |
|
|
Clock Uncertainty: 0.000ns
|
| 222 |
|
|
|
| 223 |
|
|
Minimum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 224 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 225 |
|
|
Logical Resource(s)
|
| 226 |
|
|
------------------------------------------------- -------------------
|
| 227 |
|
|
RAMB16_X1Y4.DOA24 Tbcko 1.915 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 228 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 229 |
|
|
SLICE_X74Y37.G2 net (fanout=1) 0.482 mem/outdata<6>
|
| 230 |
|
|
SLICE_X74Y37.Y Tilo 0.486 ir<6>
|
| 231 |
|
|
dbus<6>LogicTrst4
|
| 232 |
|
|
SLICE_X74Y37.F3 net (fanout=3) 0.029 dbus<6>LogicTrst4
|
| 233 |
|
|
SLICE_X74Y37.X Tilo 0.486 ir<6>
|
| 234 |
|
|
dbus<6>LogicTrst18
|
| 235 |
|
|
RAMB16_X1Y4.DIA24 net (fanout=4) 0.341 dbus<6>
|
| 236 |
|
|
RAMB16_X1Y4.CLKA Tbckd (-Th) 0.000 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 237 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 238 |
|
|
------------------------------------------------- ---------------------------
|
| 239 |
|
|
Total 3.739ns (2.887ns logic, 0.852ns route)
|
| 240 |
|
|
(77.2% logic, 22.8% route)
|
| 241 |
|
|
|
| 242 |
|
|
--------------------------------------------------------------------------------
|
| 243 |
|
|
|
| 244 |
|
|
Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA9), 1 path
|
| 245 |
|
|
--------------------------------------------------------------------------------
|
| 246 |
|
|
Slack (hold path): 3.846ns (requirement - (clock path skew + uncertainty - data path))
|
| 247 |
|
|
Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 248 |
|
|
Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)
|
| 249 |
|
|
Requirement: 0.000ns
|
| 250 |
|
|
Data Path Delay: 3.846ns (Levels of Logic = 2)
|
| 251 |
|
|
Clock Path Skew: 0.000ns
|
| 252 |
|
|
Source Clock: clkls rising at 31.250ns
|
| 253 |
|
|
Destination Clock: clkls rising at 31.250ns
|
| 254 |
|
|
Clock Uncertainty: 0.000ns
|
| 255 |
|
|
|
| 256 |
|
|
Minimum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 257 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 258 |
|
|
Logical Resource(s)
|
| 259 |
|
|
------------------------------------------------- -------------------
|
| 260 |
|
|
RAMB16_X1Y4.DOA9 Tbcko 1.915 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 261 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 262 |
|
|
SLICE_X75Y35.G4 net (fanout=1) 0.279 mem/outdata<3>
|
| 263 |
|
|
SLICE_X75Y35.Y Tilo 0.441 execunit/halt_not000111_FRB
|
| 264 |
|
|
dbus<3>LogicTrst18_SW1
|
| 265 |
|
|
SLICE_X74Y34.F1 net (fanout=1) 0.194 N92
|
| 266 |
|
|
SLICE_X74Y34.X Tilo 0.486 ir<3>
|
| 267 |
|
|
dbus<3>LogicTrst18
|
| 268 |
|
|
RAMB16_X1Y4.DIA9 net (fanout=5) 0.531 dbus<3>
|
| 269 |
|
|
RAMB16_X1Y4.CLKA Tbckd (-Th) 0.000 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram
|
| 270 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A
|
| 271 |
|
|
------------------------------------------------- ---------------------------
|
| 272 |
|
|
Total 3.846ns (2.842ns logic, 1.004ns route)
|
| 273 |
|
|
(73.9% logic, 26.1% route)
|
| 274 |
|
|
|
| 275 |
|
|
--------------------------------------------------------------------------------
|
| 276 |
|
|
|
| 277 |
|
|
Component Switching Limit Checks: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH
|
| 278 |
|
|
50%;
|
| 279 |
|
|
--------------------------------------------------------------------------------
|
| 280 |
|
|
Slack: 28.518ns (period - (min low pulse limit / (low pulse / period)))
|
| 281 |
|
|
Period: 31.250ns
|
| 282 |
|
|
Low pulse: 15.625ns
|
| 283 |
|
|
Low pulse limit: 1.366ns (Tbpwl)
|
| 284 |
|
|
Physical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKA
|
| 285 |
|
|
Logical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKA
|
| 286 |
|
|
Location pin: RAMB16_X1Y4.CLKA
|
| 287 |
|
|
Clock network: clkls
|
| 288 |
|
|
--------------------------------------------------------------------------------
|
| 289 |
|
|
Slack: 28.518ns (period - (min high pulse limit / (high pulse / period)))
|
| 290 |
|
|
Period: 31.250ns
|
| 291 |
|
|
High pulse: 15.625ns
|
| 292 |
|
|
High pulse limit: 1.366ns (Tbpwh)
|
| 293 |
|
|
Physical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKA
|
| 294 |
|
|
Logical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKA
|
| 295 |
|
|
Location pin: RAMB16_X1Y4.CLKA
|
| 296 |
|
|
Clock network: clkls
|
| 297 |
|
|
--------------------------------------------------------------------------------
|
| 298 |
|
|
Slack: 28.518ns (period - min period limit)
|
| 299 |
|
|
Period: 31.250ns
|
| 300 |
|
|
Min period limit: 2.732ns (366.032MHz) (Tbp)
|
| 301 |
|
|
Physical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKA
|
| 302 |
|
|
Logical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKA
|
| 303 |
|
|
Location pin: RAMB16_X1Y4.CLKA
|
| 304 |
|
|
Clock network: clkls
|
| 305 |
|
|
--------------------------------------------------------------------------------
|
| 306 |
|
|
|
| 307 |
|
|
|
| 308 |
|
|
Derived Constraint Report
|
| 309 |
|
|
Derived Constraints for TS_clk
|
| 310 |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
| 311 |
|
|
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
| 312 |
|
|
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
| 313 |
|
|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
| 314 |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
| 315 |
|
|
|TS_clk | 20.000ns| 6.000ns| 4.975ns| 0| 0| 0| 14|
|
| 316 |
|
|
| TS_clockdll_CLKFX_BUF | 31.250ns| 7.773ns| N/A| 0| 0| 14| 0|
|
| 317 |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
| 318 |
|
|
|
| 319 |
|
|
All constraints were met.
|
| 320 |
|
|
|
| 321 |
|
|
|
| 322 |
|
|
Data Sheet report:
|
| 323 |
|
|
-----------------
|
| 324 |
|
|
All values displayed in nanoseconds (ns)
|
| 325 |
|
|
|
| 326 |
|
|
Clock to Setup on destination clock clk
|
| 327 |
|
|
---------------+---------+---------+---------+---------+
|
| 328 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 329 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 330 |
|
|
---------------+---------+---------+---------+---------+
|
| 331 |
|
|
clk | 7.773| | | |
|
| 332 |
|
|
---------------+---------+---------+---------+---------+
|
| 333 |
|
|
|
| 334 |
|
|
|
| 335 |
|
|
Timing summary:
|
| 336 |
|
|
---------------
|
| 337 |
|
|
|
| 338 |
|
|
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
|
| 339 |
|
|
|
| 340 |
|
|
Constraints cover 14 paths, 0 nets, and 43 connections
|
| 341 |
|
|
|
| 342 |
|
|
Design statistics:
|
| 343 |
|
|
Minimum period: 7.773ns{1} (Maximum frequency: 128.650MHz)
|
| 344 |
|
|
|
| 345 |
|
|
|
| 346 |
|
|
------------------------------------Footnotes-----------------------------------
|
| 347 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
| 348 |
|
|
|
| 349 |
|
|
Analysis completed Sat May 25 07:43:45 2013
|
| 350 |
|
|
--------------------------------------------------------------------------------
|
| 351 |
|
|
|
| 352 |
|
|
Trace Settings:
|
| 353 |
|
|
-------------------------
|
| 354 |
|
|
Trace Settings
|
| 355 |
|
|
|
| 356 |
|
|
Peak Memory Usage: 246 MB
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
|
