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twDebug*, twFoot?, twClientInfo?)>
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UNCONSTPATH |
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OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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twSimpleMinPath CDATA #IMPLIED>
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fDCMJit CDATA #IMPLIED
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fPhaseErr CDATA #IMPLIED
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sEqu CDATA #IMPLIED>
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arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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best CDATA #IMPLIED requested CDATA #IMPLIED
|
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errors CDATA #IMPLIED
|
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score CDATA #IMPLIED>
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]>
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Release 13.2 Trace (lin64)Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved./opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -filter
|
333 |
|
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/home/alw/projects/vtachspartan/iseconfig/filter.filter -intstyle ise -v 3 -s 4
|
334 |
|
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-n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf vtach.ucf
|
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336 |
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top.ncdtop.ncdtop.pcftop.pcfxc3s1000-4PRODUCTION 1.39 2011-06-203INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;00000006.000Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH 50%;1400001407.773Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA0), 1 path
|
337 |
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23.477mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A7.7730.00031.2500.000mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A3RAMB16_X1Y4.CLKAclklsRAMB16_X1Y4.DOA0Tbcko2.394mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X75Y36.F4net10.695mem/outdata<0>SLICE_X75Y36.XTilo0.551execunit/out/val<1>xmemoe1_SW0SLICE_X75Y42.G2net11.006N103SLICE_X75Y42.YTilo0.551execunit/adder/bneg/Madd__not0002<0>dbus<0>LogicTrst4SLICE_X74Y43.F2net30.212dbus<0>LogicTrst4SLICE_X74Y43.XTilo0.608ir<0>dbus<0>LogicTrst18RAMB16_X1Y4.DIA0net31.272dbus<0>RAMB16_X1Y4.CLKATbdck0.484mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A4.5883.1857.773clkls59.041.0Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAMB16_X1Y4.DIB8), 1 path
|
338 |
|
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24.498mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Bmem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B6.7520.00031.2500.000mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Bmem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B1RAMB16_X1Y4.CLKBclklsRAMB16_X1Y4.DOB8Tbcko2.394mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.BSLICE_X69Y39.F3net21.163mem/outdata<9>SLICE_X69Y39.XTilo0.551ir<9>dbus<9>LogicTrstRAMB16_X1Y4.DIB8net102.160dbus<9>RAMB16_X1Y4.CLKBTbdck0.484mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B3.4293.3236.752clkls50.849.2Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA1), 1 path
|
339 |
|
|
24.512mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A6.7380.00031.2500.000mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A2RAMB16_X1Y4.CLKAclklsRAMB16_X1Y4.DOA1Tbcko2.394mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X74Y43.G3net11.156mem/outdata<1>SLICE_X74Y43.YTilo0.608ir<0>dbus<1>LogicTrst18_SW1SLICE_X74Y42.F3net20.027N101SLICE_X74Y42.XTilo0.608ir<1>dbus<1>LogicTrst18RAMB16_X1Y4.DIA1net61.461dbus<1>RAMB16_X1Y4.CLKATbdck0.484mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A4.0942.6446.738clkls60.839.2Hold Paths: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH
|
340 |
|
|
50%;
|
341 |
|
|
Paths for end point clkdiv (SLICE_X40Y95.SR), 1 path
|
342 |
|
|
1.282clkdivclkdiv1.2820.0000.0000.000clkdivclkdiv0SLICE_X40Y95.CLKclklsSLICE_X40Y95.YQTcko0.576clkdiv1clkdivSLICE_X40Y95.SRnet20.677clkdiv1SLICE_X40Y95.CLKTcksr0.029clkdiv1clkdiv0.6050.6771.282clkls47.252.8Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA24), 1 path
|
343 |
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3.739mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A3.7390.0000.0000.000mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A2RAMB16_X1Y4.CLKAclklsRAMB16_X1Y4.DOA24Tbcko1.915mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X74Y37.G2net10.482mem/outdata<6>SLICE_X74Y37.YTilo0.486ir<6>dbus<6>LogicTrst4SLICE_X74Y37.F3net30.029dbus<6>LogicTrst4SLICE_X74Y37.XTilo0.486ir<6>dbus<6>LogicTrst18RAMB16_X1Y4.DIA24net40.341dbus<6>RAMB16_X1Y4.CLKATbckd0.000mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A2.8870.8523.739clkls77.222.8Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA9), 1 path
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3.846mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A3.8460.0000.0000.000mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.Amem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A2RAMB16_X1Y4.CLKAclklsRAMB16_X1Y4.DOA9Tbcko1.915mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X75Y35.G4net10.279mem/outdata<3>SLICE_X75Y35.YTilo0.441execunit/halt_not000111_FRBdbus<3>LogicTrst18_SW1SLICE_X74Y34.F1net10.194N92SLICE_X74Y34.XTilo0.486ir<3>dbus<3>LogicTrst18RAMB16_X1Y4.DIA9net50.531dbus<3>RAMB16_X1Y4.CLKATbckd0.000mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A2.8421.0043.846clkls73.926.1Component Switching Limit Checks: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH
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50%;0clkclk7.7730000140437.773128.650Sat May 25 07:43:45 2013 TraceTrace Settings
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Peak Memory Usage: 246 MB
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