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wd5gnr |
Release 13.2 Map O.61xd (lin64)
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Xilinx Map Application Log File for Design 'top'
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Design Information
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------------------
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Command Line : map -filter iseconfig/filter.filter -intstyle ise -p
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xc3s1000-ft256-4 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication
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on -cm speed -ir off -ignore_keep_hierarchy -pr off -power off -o top_map.ncd
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top.ngd top.pcf
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Target Device : xc3s1000
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Target Package : ft256
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Target Speed : -4
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Mapper Version : spartan3 -- $Revision: 1.55 $
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Mapped Date : Sat May 25 07:43:29 2013
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vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
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INFO:Security:54 - 'xc3s1000' is a WebPack part.
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WARNING:Security:42 - Your software subscription period has lapsed. Your current
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version of Xilinx tools will continue to function, but you no longer qualify for
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Xilinx software updates or new releases.
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----------------------------------------------------------------------
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Updating timing models...
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Running timing-driven placement...
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Total REAL time at the beginning of Placer: 1 secs
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Total CPU time at the beginning of Placer: 1 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:c52ab1c9) REAL time: 2 secs
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Phase 2.7 Design Feasibility Check
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Phase 2.7 Design Feasibility Check (Checksum:c52ab1c9) REAL time: 2 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:c52ab1c9) REAL time: 2 secs
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Phase 4.2 Initial Clock and IO Placement
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Phase 4.2 Initial Clock and IO Placement (Checksum:f596ddcc) REAL time: 2 secs
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Phase 5.36 Local Placement Optimization
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Phase 5.36 Local Placement Optimization (Checksum:f596ddcc) REAL time: 2 secs
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Phase 6.4 Local Placement Optimization
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.................
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Phase 6.4 Local Placement Optimization (Checksum:f596ddcc) REAL time: 3 secs
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Phase 7.28 Local Placement Optimization
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Phase 7.28 Local Placement Optimization (Checksum:f596ddcc) REAL time: 3 secs
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Phase 8.8 Global Placement
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...................
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....
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Phase 8.8 Global Placement (Checksum:ba84736) REAL time: 4 secs
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Phase 9.29 Local Placement Optimization
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Phase 9.29 Local Placement Optimization (Checksum:ba84736) REAL time: 4 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:ba84736) REAL time: 4 secs
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Phase 11.18 Placement Optimization
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Phase 11.18 Placement Optimization (Checksum:645c87d2) REAL time: 4 secs
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Phase 12.5 Local Placement Optimization
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Phase 12.5 Local Placement Optimization (Checksum:645c87d2) REAL time: 4 secs
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Total REAL time to Placer completion: 4 secs
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Total CPU time to Placer completion: 4 secs
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Running physical synthesis...
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Physical synthesis completed.
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Running post-placement packing...
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block:
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str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 51
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Logic Utilization:
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Number of Slice Flip Flops: 237 out of 15,360 1%
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Number of 4 input LUTs: 557 out of 15,360 3%
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Logic Distribution:
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Number of occupied Slices: 347 out of 7,680 4%
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Number of Slices containing only related logic: 347 out of 347 100%
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Number of Slices containing unrelated logic: 0 out of 347 0%
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*See NOTES below for an explanation of the effects of unrelated logic.
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Total Number of 4 input LUTs: 597 out of 15,360 3%
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Number used as logic: 557
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Number used as a route-thru: 40
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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Number of bonded IOBs: 32 out of 173 18%
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Number of RAMB16s: 1 out of 24 4%
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Number of BUFGMUXs: 3 out of 8 37%
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Number of DCMs: 1 out of 4 25%
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Average Fanout of Non-Clock Nets: 3.29
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Peak Memory Usage: 429 MB
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Total REAL time to MAP completion: 7 secs
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Total CPU time to MAP completion: 7 secs
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Mapping completed.
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See MAP report file "top_map.mrp" for details.
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