OpenCores
URL https://opencores.org/ocsvn/vtach/vtach/trunk

Subversion Repositories vtach

[/] [vtach/] [trunk/] [top_map.psr] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 wd5gnr
Release 13.2 Physical Synthesis Report O.61xd (lin64)
2
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
3
 
4
TABLE OF CONTENTS
5
  1) Physical Synthesis Options Summary
6
  2) Optimizations statistics and details
7
 
8
 
9
=========================================================================
10
*                 Physical Synthesis Options Summary                    *
11
=========================================================================
12
---- Options
13
Global Optimization                 : OFF
14
    Retiming                        : OFF
15
    Equivalent Register Removal     : OFF
16
Timing-Driven Packing and Placement : ON
17
    Logic Optimization              : ON
18
    Register Duplication            : ON
19
 
20
---- Intelligent clock gating       : OFF
21
 
22
---- Target Parameters
23
Target Device                       : 3s1000ft256-4
24
 
25
=========================================================================
26
 
27
 
28
=========================================================================
29
*                        Optimizations                                  *
30
=========================================================================
31
---- Statistics
32
No sequential optimizations have been performed.
33
 
34
   Flops added for Enable Generation
35
-------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.