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-- $Id: s3_dispdrv.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: s3_dispdrv - syn
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-- Description: s3board: 7 segment display driver
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-04-17 278 1.1.1 renamed from dispdrv
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-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
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-- delay and to avoid cross talk between digits
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-- 2007-12-16 101 1.0.1 use _N for active low
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-- 2007-09-16 83 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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entity s3_dispdrv is -- 7 segment display driver
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generic (
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CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
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port (
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CLK : in slbit; -- clock
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DIN : in slv16; -- data
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DP : in slv4; -- decimal points
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ANO_N : out slv4; -- anodes (act.low)
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SEG_N : out slv8 -- segements (act.low)
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);
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end s3_dispdrv;
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architecture syn of s3_dispdrv is
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type regs_type is record
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cdiv : std_logic_vector(CDWIDTH-1 downto 0); -- clock divider counter
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dcnt : slv2; -- digit counter
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end record regs_type;
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constant regs_init : regs_type := (
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conv_std_logic_vector(0,CDWIDTH),
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(others=>'0')
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);
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type hex2segtbl_type is array (0 to 15) of slv7;
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constant hex2segtbl : hex2segtbl_type :=
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("0111111", -- 0: "0000"
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"0000110", -- 1: "0001"
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"1011011", -- 2: "0010"
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"1001111", -- 3: "0011"
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"1100110", -- 4: "0100"
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"1101101", -- 5: "0101"
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"1111101", -- 6: "0110"
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"0000111", -- 7: "0111"
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"1111111", -- 8: "1000"
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"1101111", -- 9: "1001"
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"1110111", -- a: "1010"
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"1111100", -- b: "1011"
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"0111001", -- c: "1100"
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"1011110", -- d: "1101"
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"1111001", -- e: "1110"
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"1110001" -- f: "1111"
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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assert CDWIDTH >= 5
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report "assert(CDWIDTH >= 5): CDWIDTH too small"
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severity FAILURE;
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proc_regs: process (CLK)
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begin
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if CLK'event and CLK='1' then
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R_REGS <= N_REGS;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, DIN, DP)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable cano : slv4 := "0000";
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variable chex : slv4 := "0000";
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variable cdp : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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n.cdiv := unsigned(r.cdiv) - 1;
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if unsigned(r.cdiv) = 0 then
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n.dcnt := unsigned(r.dcnt) + 1;
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end if;
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chex := "0000";
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cdp := '0';
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case r.dcnt is
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when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
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when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
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when "10" => chex := DIN(11 downto 8); cdp := DP(2);
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when "11" => chex := DIN(15 downto 12); cdp := DP(3);
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when others => chex := "----"; cdp := '-';
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end case;
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-- the logic below ensures that the anode PNP driver transistor is switched
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-- off 16 cycles before the cathode drivers change. This prevents 'cross
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-- talk' between digits due to transistor turn off delays. With no or 4
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-- cycles gap one gets well visible cross talk, with 8 cycles still some
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-- weak cross talk. With 16 cycles (at 50MHz) none is visible. The
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-- turn-off delay of the anode driver PNP's this therefore larger 160 ns
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-- and below 320 ns.
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-- As consquence CDWIDTH should be at least 5, better 6.
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cano := "1111";
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if unsigned(r.cdiv) >= 16 then
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cano(conv_integer(unsigned(r.dcnt))) := '0';
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end if;
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N_REGS <= n;
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ANO_N <= cano;
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SEG_N <= not (cdp & hex2segtbl(conv_integer(unsigned(chex))));
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end process proc_next;
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end syn;
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