1 |
2 |
wfjm |
-- $Id: s3_sram_memctl.vhd 314 2010-07-09 17:38:41Z mueller $
|
2 |
|
|
--
|
3 |
|
|
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Module Name: s3_sram_memctl - syn
|
16 |
|
|
-- Description: s3board: SRAM driver
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: vlib/xlib/iob_reg_o
|
19 |
|
|
-- vlib/xlib/iob_reg_o_gen
|
20 |
|
|
-- vlib/xlib/iob_reg_io_gen
|
21 |
|
|
-- Test bench: tb/tb_s3_sram_memctl
|
22 |
|
|
-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
|
23 |
|
|
-- Target Devices: generic
|
24 |
|
|
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
25 |
|
|
--
|
26 |
|
|
-- Synthesized (xst):
|
27 |
|
|
-- Date Rev ise Target flop lutl lutm slic t peri
|
28 |
|
|
-- 2010-05-23 293 11.4 L68 xc3s1000-4 7 22 0 14 s 8.5
|
29 |
|
|
-- 2008-02-16 116 8.2.03 I34 xc3s1000-4 5 30 0 17 s 7.0
|
30 |
|
|
--
|
31 |
|
|
-- Revision History:
|
32 |
|
|
-- Date Rev Version Comment
|
33 |
|
|
-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
|
34 |
|
|
-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
|
35 |
|
|
-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface
|
36 |
|
|
-- 2008-01-20 113 1.0.2 rename memdrv -> memctl_s3sram
|
37 |
|
|
-- 2007-12-15 101 1.0.1 use _N for active low; get ce/we clocking right
|
38 |
|
|
-- 2007-12-08 100 1.0 Initial version
|
39 |
|
|
--
|
40 |
|
|
-- Timing of some signals:
|
41 |
|
|
--
|
42 |
|
|
-- single read request:
|
43 |
|
|
--
|
44 |
|
|
-- state |_idle |_read |_idle |
|
45 |
|
|
--
|
46 |
|
|
-- CLK __|^^^|___|^^^|___|^^^|___|^
|
47 |
|
|
--
|
48 |
|
|
-- REQ _______|^^^^^|______________
|
49 |
|
|
-- WE ____________________________
|
50 |
|
|
--
|
51 |
|
|
-- IOB_CE __________|^^^^^^^|_________
|
52 |
|
|
-- IOB_OE __________|^^^^^^^|_________
|
53 |
|
|
--
|
54 |
|
|
-- DO oooooooooooooooooo|ddddddd|d
|
55 |
|
|
-- BUSY ____________________________
|
56 |
|
|
-- ACK_R __________________|^^^^^^^|_
|
57 |
|
|
--
|
58 |
|
|
-- single write request:
|
59 |
|
|
--
|
60 |
|
|
-- state |_idle |_write1|_write2|_idle |
|
61 |
|
|
--
|
62 |
|
|
-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^
|
63 |
|
|
--
|
64 |
|
|
-- REQ _______|^^^^^|______________
|
65 |
|
|
-- WE _______|^^^^^|______________
|
66 |
|
|
--
|
67 |
|
|
-- IOB_CE __________|^^^^^^^^^^^^^^^|_________
|
68 |
|
|
-- IOB_BE __________|^^^^^^^^^^^^^^^|_________
|
69 |
|
|
-- IOB_OE ____________________________________
|
70 |
|
|
-- IOB_WE ______________|^^^^^^^|_____________
|
71 |
|
|
--
|
72 |
|
|
-- BUSY __________|^^^^^^^|_________________
|
73 |
|
|
-- ACK_W __________________|^^^^^^^|_________
|
74 |
|
|
--
|
75 |
|
|
------------------------------------------------------------------------------
|
76 |
|
|
|
77 |
|
|
library ieee;
|
78 |
|
|
use ieee.std_logic_1164.all;
|
79 |
|
|
use ieee.std_logic_arith.all;
|
80 |
|
|
|
81 |
|
|
use work.slvtypes.all;
|
82 |
|
|
use work.xlib.all;
|
83 |
|
|
|
84 |
|
|
entity s3_sram_memctl is -- SRAM driver for S3BOARD
|
85 |
|
|
port (
|
86 |
|
|
CLK : in slbit; -- clock
|
87 |
|
|
RESET : in slbit; -- reset
|
88 |
|
|
REQ : in slbit; -- request
|
89 |
|
|
WE : in slbit; -- write enable
|
90 |
|
|
BUSY : out slbit; -- controller busy
|
91 |
|
|
ACK_R : out slbit; -- acknowledge read
|
92 |
|
|
ACK_W : out slbit; -- acknowledge write
|
93 |
|
|
ACT_R : out slbit; -- signal active read
|
94 |
|
|
ACT_W : out slbit; -- signal active write
|
95 |
|
|
ADDR : in slv18; -- address
|
96 |
|
|
BE : in slv4; -- byte enable
|
97 |
|
|
DI : in slv32; -- data in (memory view)
|
98 |
|
|
DO : out slv32; -- data out (memory view)
|
99 |
|
|
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
|
100 |
|
|
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
|
101 |
|
|
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
|
102 |
|
|
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
|
103 |
|
|
O_MEM_ADDR : out slv18; -- sram: address lines
|
104 |
|
|
IO_MEM_DATA : inout slv32 -- sram: data lines
|
105 |
|
|
);
|
106 |
|
|
end s3_sram_memctl;
|
107 |
|
|
|
108 |
|
|
|
109 |
|
|
architecture syn of s3_sram_memctl is
|
110 |
|
|
|
111 |
|
|
type state_type is (
|
112 |
|
|
s_idle, -- s_idle: wait for req
|
113 |
|
|
s_read, -- s_read: read cycle
|
114 |
|
|
s_write1, -- s_write1: write cycle, 1st half
|
115 |
|
|
s_write2, -- s_write2: write cycle, 2nd half
|
116 |
|
|
s_bta_r2w, -- s_bta_r2w: bus turn around: r->w
|
117 |
|
|
s_bta_w2r -- s_bta_w2r: bus turn around: w->r
|
118 |
|
|
);
|
119 |
|
|
|
120 |
|
|
type regs_type is record
|
121 |
|
|
state : state_type; -- state
|
122 |
|
|
ackr : slbit; -- signal ack_r
|
123 |
|
|
end record regs_type;
|
124 |
|
|
|
125 |
|
|
constant regs_init : regs_type := (
|
126 |
|
|
s_idle,
|
127 |
|
|
'0' -- ackr
|
128 |
|
|
);
|
129 |
|
|
|
130 |
|
|
signal R_REGS : regs_type := regs_init; -- state registers
|
131 |
|
|
signal N_REGS : regs_type := regs_init; -- next value state regs
|
132 |
|
|
|
133 |
|
|
signal CLK_180 : slbit := '0';
|
134 |
|
|
signal MEM_CE_N : slv2 := "00";
|
135 |
|
|
signal MEM_BE_N : slv4 := "0000";
|
136 |
|
|
signal MEM_WE_N : slbit := '0';
|
137 |
|
|
signal MEM_OE_N : slbit := '0';
|
138 |
|
|
signal ADDR_CE : slbit := '0';
|
139 |
|
|
signal DATA_CEI : slbit := '0';
|
140 |
|
|
signal DATA_CEO : slbit := '0';
|
141 |
|
|
signal DATA_OE : slbit := '0';
|
142 |
|
|
|
143 |
|
|
begin
|
144 |
|
|
|
145 |
|
|
CLK_180 <= not CLK;
|
146 |
|
|
|
147 |
|
|
IOB_MEM_CE : iob_reg_o_gen
|
148 |
|
|
generic map (
|
149 |
|
|
DWIDTH => 2,
|
150 |
|
|
INIT => '1')
|
151 |
|
|
port map (
|
152 |
|
|
CLK => CLK,
|
153 |
|
|
CE => '1',
|
154 |
|
|
DO => MEM_CE_N,
|
155 |
|
|
PAD => O_MEM_CE_N
|
156 |
|
|
);
|
157 |
|
|
|
158 |
|
|
IOB_MEM_BE : iob_reg_o_gen
|
159 |
|
|
generic map (
|
160 |
|
|
DWIDTH => 4,
|
161 |
|
|
INIT => '1')
|
162 |
|
|
port map (
|
163 |
|
|
CLK => CLK,
|
164 |
|
|
CE => ADDR_CE,
|
165 |
|
|
DO => MEM_BE_N,
|
166 |
|
|
PAD => O_MEM_BE_N
|
167 |
|
|
);
|
168 |
|
|
|
169 |
|
|
IOB_MEM_WE : iob_reg_o
|
170 |
|
|
generic map (
|
171 |
|
|
INIT => '1')
|
172 |
|
|
port map (
|
173 |
|
|
CLK => CLK_180,
|
174 |
|
|
CE => '1',
|
175 |
|
|
DO => MEM_WE_N,
|
176 |
|
|
PAD => O_MEM_WE_N
|
177 |
|
|
);
|
178 |
|
|
|
179 |
|
|
IOB_MEM_OE : iob_reg_o
|
180 |
|
|
generic map (
|
181 |
|
|
INIT => '1')
|
182 |
|
|
port map (
|
183 |
|
|
CLK => CLK,
|
184 |
|
|
CE => '1',
|
185 |
|
|
DO => MEM_OE_N,
|
186 |
|
|
PAD => O_MEM_OE_N
|
187 |
|
|
);
|
188 |
|
|
|
189 |
|
|
IOB_MEM_ADDR : iob_reg_o_gen
|
190 |
|
|
generic map (
|
191 |
|
|
DWIDTH => 18)
|
192 |
|
|
port map (
|
193 |
|
|
CLK => CLK,
|
194 |
|
|
CE => ADDR_CE,
|
195 |
|
|
DO => ADDR,
|
196 |
|
|
PAD => O_MEM_ADDR
|
197 |
|
|
);
|
198 |
|
|
|
199 |
|
|
IOB_MEM_DATA : iob_reg_io_gen
|
200 |
|
|
generic map (
|
201 |
|
|
DWIDTH => 32,
|
202 |
|
|
PULL => "KEEP")
|
203 |
|
|
port map (
|
204 |
|
|
CLK => CLK,
|
205 |
|
|
CEI => DATA_CEI,
|
206 |
|
|
CEO => DATA_CEO,
|
207 |
|
|
OE => DATA_OE,
|
208 |
|
|
DI => DO,
|
209 |
|
|
DO => DI,
|
210 |
|
|
PAD => IO_MEM_DATA
|
211 |
|
|
);
|
212 |
|
|
|
213 |
|
|
proc_regs: process (CLK)
|
214 |
|
|
begin
|
215 |
|
|
|
216 |
|
|
if CLK'event and CLK='1' then
|
217 |
|
|
if RESET = '1' then
|
218 |
|
|
R_REGS <= regs_init;
|
219 |
|
|
else
|
220 |
|
|
R_REGS <= N_REGS;
|
221 |
|
|
end if;
|
222 |
|
|
end if;
|
223 |
|
|
|
224 |
|
|
end process proc_regs;
|
225 |
|
|
|
226 |
|
|
proc_next: process (R_REGS, REQ, WE, BE)
|
227 |
|
|
|
228 |
|
|
variable r : regs_type := regs_init;
|
229 |
|
|
variable n : regs_type := regs_init;
|
230 |
|
|
variable ibusy : slbit := '0';
|
231 |
|
|
variable iackw : slbit := '0';
|
232 |
|
|
variable iactr : slbit := '0';
|
233 |
|
|
variable iactw : slbit := '0';
|
234 |
|
|
variable imem_ce : slv2 := "00";
|
235 |
|
|
variable imem_be : slv4 := "0000";
|
236 |
|
|
variable imem_we : slbit := '0';
|
237 |
|
|
variable imem_oe : slbit := '0';
|
238 |
|
|
variable iaddr_ce : slbit := '0';
|
239 |
|
|
variable idata_cei : slbit := '0';
|
240 |
|
|
variable idata_ceo : slbit := '0';
|
241 |
|
|
variable idata_oe : slbit := '0';
|
242 |
|
|
|
243 |
|
|
begin
|
244 |
|
|
|
245 |
|
|
r := R_REGS;
|
246 |
|
|
n := R_REGS;
|
247 |
|
|
n.ackr := '0';
|
248 |
|
|
|
249 |
|
|
ibusy := '0';
|
250 |
|
|
iackw := '0';
|
251 |
|
|
iactr := '0';
|
252 |
|
|
iactw := '0';
|
253 |
|
|
|
254 |
|
|
imem_ce := "00";
|
255 |
|
|
imem_be := "1111";
|
256 |
|
|
imem_we := '0';
|
257 |
|
|
imem_oe := '0';
|
258 |
|
|
iaddr_ce := '0';
|
259 |
|
|
idata_cei := '0';
|
260 |
|
|
idata_ceo := '0';
|
261 |
|
|
idata_oe := '0';
|
262 |
|
|
|
263 |
|
|
case r.state is
|
264 |
|
|
when s_idle => -- s_idle: wait for req
|
265 |
|
|
if REQ = '1' then -- if IO requested
|
266 |
|
|
if WE = '0' then -- if READ requested
|
267 |
|
|
iaddr_ce := '1'; -- latch address and be's
|
268 |
|
|
imem_ce := "11"; -- ce SRAM next cycle
|
269 |
|
|
imem_oe := '1'; -- oe SRAM next cycle
|
270 |
|
|
n.state := s_read; -- next: read
|
271 |
|
|
else -- if WRITE requested
|
272 |
|
|
iaddr_ce := '1'; -- latch address and be's
|
273 |
|
|
idata_ceo := '1'; -- latch output data
|
274 |
|
|
idata_oe := '1'; -- oe FPGA next cycle
|
275 |
|
|
imem_ce := "11"; -- ce SRAM next cycle
|
276 |
|
|
imem_be := BE; -- use request BE's
|
277 |
|
|
n.state := s_write1; -- next: write 1st part
|
278 |
|
|
end if;
|
279 |
|
|
end if;
|
280 |
|
|
|
281 |
|
|
when s_read => -- s_read: read cycle
|
282 |
|
|
idata_cei := '1'; -- latch input data
|
283 |
|
|
iactr := '1'; -- signal mem read
|
284 |
|
|
n.ackr := '1'; -- ACK_R next cycle
|
285 |
|
|
if REQ = '1' then -- if IO requested
|
286 |
|
|
if WE = '0' then -- if READ requested
|
287 |
|
|
iaddr_ce := '1'; -- latch address and be's
|
288 |
|
|
imem_ce := "11"; -- ce SRAM next cycle
|
289 |
|
|
imem_oe := '1'; -- oe SRAM next cycle
|
290 |
|
|
n.state := s_read; -- next: continue read
|
291 |
|
|
else -- if WRITE requested
|
292 |
|
|
iaddr_ce := '1'; -- latch address and be's
|
293 |
|
|
idata_ceo := '1'; -- latch output data
|
294 |
|
|
imem_be := BE; -- use request BE's
|
295 |
|
|
n.state := s_bta_r2w; -- next: bus turn around cycle
|
296 |
|
|
end if;
|
297 |
|
|
else
|
298 |
|
|
n.state := s_idle; -- next: idle if nothing to do
|
299 |
|
|
end if;
|
300 |
|
|
|
301 |
|
|
when s_write1 => -- s_write1: write cycle, 1st half
|
302 |
|
|
ibusy := '1'; -- signal busy, unable to handle req
|
303 |
|
|
iactw := '1'; -- signal mem write
|
304 |
|
|
idata_oe := '1'; -- oe FPGA next cycle
|
305 |
|
|
imem_ce := "11"; -- ce SRAM next cycle
|
306 |
|
|
imem_we := '1'; -- we SRAM next shifted cycle
|
307 |
|
|
n.state := s_write2; -- next: write cycle, 2nd half
|
308 |
|
|
|
309 |
|
|
when s_write2 => -- s_write2: write cycle, 2nd half
|
310 |
|
|
iactw := '1'; -- signal mem write
|
311 |
|
|
iackw := '1'; -- signal write acknowledge
|
312 |
|
|
idata_cei := '1'; -- latch input data (from SRAM)
|
313 |
|
|
if REQ = '1' then -- if IO requested
|
314 |
|
|
if WE = '1' then -- if WRITE requested
|
315 |
|
|
iaddr_ce := '1'; -- latch address and be's
|
316 |
|
|
idata_ceo := '1'; -- latch output data
|
317 |
|
|
idata_oe := '1'; -- oe FPGA next cycle
|
318 |
|
|
imem_ce := "11"; -- ce SRAM next cycle
|
319 |
|
|
imem_be := BE; -- use request BE's
|
320 |
|
|
n.state := s_write1; -- next: continue read
|
321 |
|
|
else -- if READ requested
|
322 |
|
|
iaddr_ce := '1'; -- latch address and be's
|
323 |
|
|
n.state := s_bta_w2r; -- next: bus turn around cycle
|
324 |
|
|
end if;
|
325 |
|
|
else
|
326 |
|
|
n.state := s_idle; -- next: idle if nothing to do
|
327 |
|
|
end if;
|
328 |
|
|
|
329 |
|
|
when s_bta_r2w => -- s_bta_r2w: bus turn around: r->w
|
330 |
|
|
ibusy := '1'; -- signal busy, unable to handle req
|
331 |
|
|
iactw := '1'; -- signal mem write
|
332 |
|
|
imem_ce := "11"; -- ce SRAM next cycle
|
333 |
|
|
idata_oe := '1'; -- oe FPGA next cycle
|
334 |
|
|
n.state := s_write1; -- next: start write
|
335 |
|
|
|
336 |
|
|
when s_bta_w2r => -- s_bta_w2r: bus turn around: w->r
|
337 |
|
|
ibusy := '1'; -- signal busy, unable to handle req
|
338 |
|
|
iactr := '1'; -- signal mem read
|
339 |
|
|
imem_ce := "11"; -- ce SRAM next cycle
|
340 |
|
|
imem_oe := '1'; -- oe SRAM next cycle
|
341 |
|
|
n.state := s_read; -- next: start read
|
342 |
|
|
|
343 |
|
|
when others => null;
|
344 |
|
|
end case;
|
345 |
|
|
|
346 |
|
|
N_REGS <= n;
|
347 |
|
|
|
348 |
|
|
MEM_CE_N <= not imem_ce;
|
349 |
|
|
MEM_WE_N <= not imem_we;
|
350 |
|
|
MEM_BE_N <= not imem_be;
|
351 |
|
|
MEM_OE_N <= not imem_oe;
|
352 |
|
|
ADDR_CE <= iaddr_ce;
|
353 |
|
|
DATA_CEI <= idata_cei;
|
354 |
|
|
DATA_CEO <= idata_ceo;
|
355 |
|
|
DATA_OE <= idata_oe;
|
356 |
|
|
|
357 |
|
|
BUSY <= ibusy;
|
358 |
|
|
ACK_R <= r.ackr;
|
359 |
|
|
ACK_W <= iackw;
|
360 |
|
|
ACT_R <= iactr;
|
361 |
|
|
ACT_W <= iactw;
|
362 |
|
|
|
363 |
|
|
end process proc_next;
|
364 |
|
|
|
365 |
|
|
end syn;
|