| 1 |
2 |
wfjm |
-- $Id: ibdr_maxisys.vhd 314 2010-07-09 17:38:41Z mueller $
|
| 2 |
|
|
--
|
| 3 |
|
|
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
| 4 |
|
|
--
|
| 5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
| 6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
| 7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
| 8 |
|
|
--
|
| 9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
| 10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
| 11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 12 |
|
|
-- for complete details.
|
| 13 |
|
|
--
|
| 14 |
|
|
------------------------------------------------------------------------------
|
| 15 |
|
|
-- Module Name: ibdr_maxisys - syn
|
| 16 |
|
|
-- Description: ibus(rem) devices for full system
|
| 17 |
|
|
--
|
| 18 |
|
|
-- Dependencies: ibd_iist
|
| 19 |
|
|
-- ibd_kw11l
|
| 20 |
|
|
-- ibdr_rk11
|
| 21 |
|
|
-- ibdr_dl11
|
| 22 |
|
|
-- ibdr_pc11
|
| 23 |
|
|
-- ibdr_lp11
|
| 24 |
|
|
-- ibdr_sdreg
|
| 25 |
|
|
-- ib_sres_or_4
|
| 26 |
|
|
-- ib_sres_or_3
|
| 27 |
|
|
-- ib_intmap
|
| 28 |
|
|
-- Test bench: -
|
| 29 |
|
|
-- Target Devices: generic
|
| 30 |
|
|
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
| 31 |
|
|
-- Revision History:
|
| 32 |
|
|
-- Date Rev Version Comment
|
| 33 |
|
|
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
|
| 34 |
|
|
-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11
|
| 35 |
|
|
-- 2009-06-20 227 1.0.3 rename generate labels.
|
| 36 |
|
|
-- 2009-06-07 224 1.0.2 add iist_mreq and iist_sres interfaces
|
| 37 |
|
|
-- 2009-06-01 221 1.0.1 add CE_USEC; add RESET to kw11l; add _pc11, _iist
|
| 38 |
|
|
-- 2009-05-24 219 1.0 Initial version
|
| 39 |
|
|
------------------------------------------------------------------------------
|
| 40 |
|
|
--
|
| 41 |
|
|
--
|
| 42 |
|
|
-- full system setup
|
| 43 |
|
|
--
|
| 44 |
|
|
-- ibbase vec pri slot attn sror device name
|
| 45 |
|
|
--
|
| 46 |
|
|
-- 172540 104 ?7 14 17 - 1/1 KW11-P
|
| 47 |
|
|
-- 177500 260 6 13 16 - 1/2 IIST
|
| 48 |
|
|
-- 177546 100 6 12 15 - 1/3 KW11-L
|
| 49 |
|
|
-- 174510 120 5 14 9 1/4 DEUNA
|
| 50 |
|
|
-- 176700 254 5 13 6 2/1 RH70/RP06
|
| 51 |
|
|
-- 174400 160 5 11 12 5 2/2 RL11
|
| 52 |
|
|
-- 177400 220 5 10 11 4 2/3 RK11
|
| 53 |
|
|
-- 172520 224 5 10 7 2/4 TM11
|
| 54 |
|
|
-- 160100 310? 5 9 9 3 3/1 DZ11-RX
|
| 55 |
|
|
-- 314? 5 8 8 ^ DZ11-TX
|
| 56 |
|
|
-- 177560 060 4 7 7 1 3/2 DL11-RX 1st
|
| 57 |
|
|
-- 064 4 6 6 ^ DL11-TX 1st
|
| 58 |
|
|
-- 176500 300 4 5 5 2 3/3 DL11-RX 2nd
|
| 59 |
|
|
-- 304 4 4 4 ^ DL11-TX 2nd
|
| 60 |
|
|
-- 177550 070 4 3 3 10 4/1 PC11/PTR
|
| 61 |
|
|
-- 074 4 2 2 ^ PC11/PTP
|
| 62 |
|
|
-- 177514 200 4 1 1 8 4/2 LP11
|
| 63 |
|
|
-- 177570 - - - - 4/3 sdreg
|
| 64 |
|
|
--
|
| 65 |
|
|
|
| 66 |
|
|
library ieee;
|
| 67 |
|
|
use ieee.std_logic_1164.all;
|
| 68 |
|
|
use ieee.std_logic_arith.all;
|
| 69 |
|
|
|
| 70 |
|
|
use work.slvtypes.all;
|
| 71 |
|
|
use work.iblib.all;
|
| 72 |
|
|
use work.ibdlib.all;
|
| 73 |
|
|
|
| 74 |
|
|
-- ----------------------------------------------------------------------------
|
| 75 |
|
|
entity ibdr_maxisys is -- ibus(rem) full system
|
| 76 |
|
|
port (
|
| 77 |
|
|
CLK : in slbit; -- clock
|
| 78 |
|
|
CE_USEC : in slbit; -- usec pulse
|
| 79 |
|
|
CE_MSEC : in slbit; -- msec pulse
|
| 80 |
|
|
RESET : in slbit; -- reset
|
| 81 |
|
|
BRESET : in slbit; -- ibus reset
|
| 82 |
|
|
RRI_LAM : out slv16_1; -- remote attention vector
|
| 83 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 84 |
|
|
IB_SRES : out ib_sres_type; -- ibus response
|
| 85 |
|
|
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
|
| 86 |
|
|
EI_PRI : out slv3; -- interrupt priority (to cpu)
|
| 87 |
|
|
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
|
| 88 |
|
|
DISPREG : out slv16 -- display register
|
| 89 |
|
|
);
|
| 90 |
|
|
end ibdr_maxisys;
|
| 91 |
|
|
|
| 92 |
|
|
architecture syn of ibdr_maxisys is
|
| 93 |
|
|
|
| 94 |
|
|
constant conf_intmap : intmap_array_type :=
|
| 95 |
|
|
(intmap_init, -- line 15
|
| 96 |
|
|
(8#104#,6), -- line 14 KW11-P
|
| 97 |
|
|
(8#260#,6), -- line 13 IIST
|
| 98 |
|
|
(8#100#,6), -- line 12 KW11-L
|
| 99 |
|
|
(8#160#,5), -- line 11 RL11
|
| 100 |
|
|
(8#220#,5), -- line 10 RK11
|
| 101 |
|
|
(8#310#,5), -- line 9 DZ11-RX
|
| 102 |
|
|
(8#314#,5), -- line 8 DZ11-TX
|
| 103 |
|
|
(8#060#,4), -- line 7 DL11-RX 1st
|
| 104 |
|
|
(8#064#,4), -- line 6 DL11-TX 1st
|
| 105 |
|
|
(8#300#,4), -- line 5 DL11-RX 2nd
|
| 106 |
|
|
(8#304#,4), -- line 4 DL11-TX 2nd
|
| 107 |
|
|
(8#070#,4), -- line 3 PC11-PTR
|
| 108 |
|
|
(8#074#,4), -- line 2 PC11-PTP
|
| 109 |
|
|
(8#200#,4), -- line 1 LP11
|
| 110 |
|
|
intmap_init -- line 0
|
| 111 |
|
|
);
|
| 112 |
|
|
|
| 113 |
|
|
signal RRI_LAM_DENUA : slbit := '0';
|
| 114 |
|
|
signal RRI_LAM_RP06 : slbit := '0';
|
| 115 |
|
|
signal RRI_LAM_RL11 : slbit := '0';
|
| 116 |
|
|
signal RRI_LAM_RK11 : slbit := '0';
|
| 117 |
|
|
signal RRI_LAM_TM11 : slbit := '0';
|
| 118 |
|
|
signal RRI_LAM_DZ11 : slbit := '0';
|
| 119 |
|
|
signal RRI_LAM_DL11_0 : slbit := '0';
|
| 120 |
|
|
signal RRI_LAM_DL11_1 : slbit := '0';
|
| 121 |
|
|
signal RRI_LAM_PC11 : slbit := '0';
|
| 122 |
|
|
signal RRI_LAM_LP11 : slbit := '0';
|
| 123 |
|
|
|
| 124 |
|
|
signal IB_SRES_IIST : ib_sres_type := ib_sres_init;
|
| 125 |
|
|
signal IB_SRES_KW11P : ib_sres_type := ib_sres_init;
|
| 126 |
|
|
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
|
| 127 |
|
|
signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init;
|
| 128 |
|
|
signal IB_SRES_RP06 : ib_sres_type := ib_sres_init;
|
| 129 |
|
|
signal IB_SRES_RL11 : ib_sres_type := ib_sres_init;
|
| 130 |
|
|
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
|
| 131 |
|
|
signal IB_SRES_TM11 : ib_sres_type := ib_sres_init;
|
| 132 |
|
|
signal IB_SRES_DZ11 : ib_sres_type := ib_sres_init;
|
| 133 |
|
|
signal IB_SRES_DL11_0 : ib_sres_type := ib_sres_init;
|
| 134 |
|
|
signal IB_SRES_DL11_1 : ib_sres_type := ib_sres_init;
|
| 135 |
|
|
signal IB_SRES_PC11 : ib_sres_type := ib_sres_init;
|
| 136 |
|
|
signal IB_SRES_LP11 : ib_sres_type := ib_sres_init;
|
| 137 |
|
|
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
|
| 138 |
|
|
|
| 139 |
|
|
signal IB_SRES_1 : ib_sres_type := ib_sres_init;
|
| 140 |
|
|
signal IB_SRES_2 : ib_sres_type := ib_sres_init;
|
| 141 |
|
|
signal IB_SRES_3 : ib_sres_type := ib_sres_init;
|
| 142 |
|
|
signal IB_SRES_4 : ib_sres_type := ib_sres_init;
|
| 143 |
|
|
|
| 144 |
|
|
signal EI_REQ : slv16_1 := (others=>'0');
|
| 145 |
|
|
signal EI_ACK : slv16_1 := (others=>'0');
|
| 146 |
|
|
|
| 147 |
|
|
signal EI_REQ_IIST : slbit := '0';
|
| 148 |
|
|
signal EI_REQ_KW11P : slbit := '0';
|
| 149 |
|
|
signal EI_REQ_KW11L : slbit := '0';
|
| 150 |
|
|
signal EI_REQ_DEUNA : slbit := '0';
|
| 151 |
|
|
signal EI_REQ_RP06 : slbit := '0';
|
| 152 |
|
|
signal EI_REQ_RL11 : slbit := '0';
|
| 153 |
|
|
signal EI_REQ_RK11 : slbit := '0';
|
| 154 |
|
|
signal EI_REQ_TM11 : slbit := '0';
|
| 155 |
|
|
signal EI_REQ_DZ11RX : slbit := '0';
|
| 156 |
|
|
signal EI_REQ_DZ11TX : slbit := '0';
|
| 157 |
|
|
signal EI_REQ_DL11RX_0 : slbit := '0';
|
| 158 |
|
|
signal EI_REQ_DL11TX_0 : slbit := '0';
|
| 159 |
|
|
signal EI_REQ_DL11RX_1 : slbit := '0';
|
| 160 |
|
|
signal EI_REQ_DL11TX_1 : slbit := '0';
|
| 161 |
|
|
signal EI_REQ_PC11PTR : slbit := '0';
|
| 162 |
|
|
signal EI_REQ_PC11PTP : slbit := '0';
|
| 163 |
|
|
signal EI_REQ_LP11 : slbit := '0';
|
| 164 |
|
|
|
| 165 |
|
|
signal EI_ACK_IIST : slbit := '0';
|
| 166 |
|
|
signal EI_ACK_KW11P : slbit := '0';
|
| 167 |
|
|
signal EI_ACK_KW11L : slbit := '0';
|
| 168 |
|
|
signal EI_ACK_DEUNA : slbit := '0';
|
| 169 |
|
|
signal EI_ACK_RP06 : slbit := '0';
|
| 170 |
|
|
signal EI_ACK_RL11 : slbit := '0';
|
| 171 |
|
|
signal EI_ACK_RK11 : slbit := '0';
|
| 172 |
|
|
signal EI_ACK_TM11 : slbit := '0';
|
| 173 |
|
|
signal EI_ACK_DZ11RX : slbit := '0';
|
| 174 |
|
|
signal EI_ACK_DZ11TX : slbit := '0';
|
| 175 |
|
|
signal EI_ACK_DL11RX_0 : slbit := '0';
|
| 176 |
|
|
signal EI_ACK_DL11TX_0 : slbit := '0';
|
| 177 |
|
|
signal EI_ACK_DL11RX_1 : slbit := '0';
|
| 178 |
|
|
signal EI_ACK_DL11TX_1 : slbit := '0';
|
| 179 |
|
|
signal EI_ACK_PC11PTR : slbit := '0';
|
| 180 |
|
|
signal EI_ACK_PC11PTP : slbit := '0';
|
| 181 |
|
|
signal EI_ACK_LP11 : slbit := '0';
|
| 182 |
|
|
|
| 183 |
|
|
signal IIST_BUS : iist_bus_type := iist_bus_init;
|
| 184 |
|
|
signal IIST_OUT_0 : iist_line_type := iist_line_init;
|
| 185 |
|
|
signal IIST_MREQ : iist_mreq_type := iist_mreq_init;
|
| 186 |
|
|
signal IIST_SRES : iist_sres_type := iist_sres_init;
|
| 187 |
|
|
|
| 188 |
|
|
begin
|
| 189 |
|
|
|
| 190 |
|
|
IIST: if true generate
|
| 191 |
|
|
begin
|
| 192 |
|
|
I0 : ibd_iist
|
| 193 |
|
|
port map (
|
| 194 |
|
|
CLK => CLK,
|
| 195 |
|
|
CE_USEC => CE_USEC,
|
| 196 |
|
|
RESET => RESET,
|
| 197 |
|
|
BRESET => BRESET,
|
| 198 |
|
|
IB_MREQ => IB_MREQ,
|
| 199 |
|
|
IB_SRES => IB_SRES_IIST,
|
| 200 |
|
|
EI_REQ => EI_REQ_IIST,
|
| 201 |
|
|
EI_ACK => EI_ACK_IIST,
|
| 202 |
|
|
IIST_BUS => IIST_BUS,
|
| 203 |
|
|
IIST_OUT => IIST_OUT_0,
|
| 204 |
|
|
IIST_MREQ => IIST_MREQ,
|
| 205 |
|
|
IIST_SRES => IIST_SRES
|
| 206 |
|
|
);
|
| 207 |
|
|
|
| 208 |
|
|
IIST_BUS(0) <= IIST_OUT_0;
|
| 209 |
|
|
IIST_BUS(1) <= iist_line_init;
|
| 210 |
|
|
IIST_BUS(2) <= iist_line_init;
|
| 211 |
|
|
IIST_BUS(3) <= iist_line_init;
|
| 212 |
|
|
|
| 213 |
|
|
end generate IIST;
|
| 214 |
|
|
|
| 215 |
|
|
KW11L : ibd_kw11l
|
| 216 |
|
|
port map (
|
| 217 |
|
|
CLK => CLK,
|
| 218 |
|
|
CE_MSEC => CE_MSEC,
|
| 219 |
|
|
RESET => RESET,
|
| 220 |
|
|
BRESET => BRESET,
|
| 221 |
|
|
IB_MREQ => IB_MREQ,
|
| 222 |
|
|
IB_SRES => IB_SRES_KW11L,
|
| 223 |
|
|
EI_REQ => EI_REQ_KW11L,
|
| 224 |
|
|
EI_ACK => EI_ACK_KW11L
|
| 225 |
|
|
);
|
| 226 |
|
|
|
| 227 |
|
|
RK11: if true generate
|
| 228 |
|
|
begin
|
| 229 |
|
|
I0 : ibdr_rk11
|
| 230 |
|
|
port map (
|
| 231 |
|
|
CLK => CLK,
|
| 232 |
|
|
CE_MSEC => CE_MSEC,
|
| 233 |
|
|
BRESET => BRESET,
|
| 234 |
|
|
RRI_LAM => RRI_LAM_RK11,
|
| 235 |
|
|
IB_MREQ => IB_MREQ,
|
| 236 |
|
|
IB_SRES => IB_SRES_RK11,
|
| 237 |
|
|
EI_REQ => EI_REQ_RK11,
|
| 238 |
|
|
EI_ACK => EI_ACK_RK11
|
| 239 |
|
|
);
|
| 240 |
|
|
end generate RK11;
|
| 241 |
|
|
|
| 242 |
|
|
DL11_0 : ibdr_dl11
|
| 243 |
|
|
port map (
|
| 244 |
|
|
CLK => CLK,
|
| 245 |
|
|
CE_USEC => CE_USEC,
|
| 246 |
|
|
RESET => RESET,
|
| 247 |
|
|
BRESET => BRESET,
|
| 248 |
|
|
RRI_LAM => RRI_LAM_DL11_0,
|
| 249 |
|
|
IB_MREQ => IB_MREQ,
|
| 250 |
|
|
IB_SRES => IB_SRES_DL11_0,
|
| 251 |
|
|
EI_REQ_RX => EI_REQ_DL11RX_0,
|
| 252 |
|
|
EI_REQ_TX => EI_REQ_DL11TX_0,
|
| 253 |
|
|
EI_ACK_RX => EI_ACK_DL11RX_0,
|
| 254 |
|
|
EI_ACK_TX => EI_ACK_DL11TX_0
|
| 255 |
|
|
);
|
| 256 |
|
|
|
| 257 |
|
|
DL11_1: if true generate
|
| 258 |
|
|
begin
|
| 259 |
|
|
I0 : ibdr_dl11
|
| 260 |
|
|
generic map (
|
| 261 |
|
|
IB_ADDR => conv_std_logic_vector(8#176500#,16))
|
| 262 |
|
|
port map (
|
| 263 |
|
|
CLK => CLK,
|
| 264 |
|
|
CE_USEC => CE_USEC,
|
| 265 |
|
|
RESET => RESET,
|
| 266 |
|
|
BRESET => BRESET,
|
| 267 |
|
|
RRI_LAM => RRI_LAM_DL11_1,
|
| 268 |
|
|
IB_MREQ => IB_MREQ,
|
| 269 |
|
|
IB_SRES => IB_SRES_DL11_1,
|
| 270 |
|
|
EI_REQ_RX => EI_REQ_DL11RX_1,
|
| 271 |
|
|
EI_REQ_TX => EI_REQ_DL11TX_1,
|
| 272 |
|
|
EI_ACK_RX => EI_ACK_DL11RX_1,
|
| 273 |
|
|
EI_ACK_TX => EI_ACK_DL11TX_1
|
| 274 |
|
|
);
|
| 275 |
|
|
end generate DL11_1;
|
| 276 |
|
|
|
| 277 |
|
|
PC11: if true generate
|
| 278 |
|
|
begin
|
| 279 |
|
|
I0 : ibdr_pc11
|
| 280 |
|
|
port map (
|
| 281 |
|
|
CLK => CLK,
|
| 282 |
|
|
RESET => RESET,
|
| 283 |
|
|
BRESET => BRESET,
|
| 284 |
|
|
RRI_LAM => RRI_LAM_PC11,
|
| 285 |
|
|
IB_MREQ => IB_MREQ,
|
| 286 |
|
|
IB_SRES => IB_SRES_PC11,
|
| 287 |
|
|
EI_REQ_PTR => EI_REQ_PC11PTR,
|
| 288 |
|
|
EI_REQ_PTP => EI_REQ_PC11PTP,
|
| 289 |
|
|
EI_ACK_PTR => EI_ACK_PC11PTR,
|
| 290 |
|
|
EI_ACK_PTP => EI_ACK_PC11PTP
|
| 291 |
|
|
);
|
| 292 |
|
|
end generate PC11;
|
| 293 |
|
|
|
| 294 |
|
|
LP11: if true generate
|
| 295 |
|
|
begin
|
| 296 |
|
|
I0 : ibdr_lp11
|
| 297 |
|
|
port map (
|
| 298 |
|
|
CLK => CLK,
|
| 299 |
|
|
RESET => RESET,
|
| 300 |
|
|
BRESET => BRESET,
|
| 301 |
|
|
RRI_LAM => RRI_LAM_LP11,
|
| 302 |
|
|
IB_MREQ => IB_MREQ,
|
| 303 |
|
|
IB_SRES => IB_SRES_LP11,
|
| 304 |
|
|
EI_REQ => EI_REQ_LP11,
|
| 305 |
|
|
EI_ACK => EI_ACK_LP11
|
| 306 |
|
|
);
|
| 307 |
|
|
end generate LP11;
|
| 308 |
|
|
|
| 309 |
|
|
SDREG : ibdr_sdreg
|
| 310 |
|
|
port map (
|
| 311 |
|
|
CLK => CLK,
|
| 312 |
|
|
RESET => RESET,
|
| 313 |
|
|
IB_MREQ => IB_MREQ,
|
| 314 |
|
|
IB_SRES => IB_SRES_SDREG,
|
| 315 |
|
|
DISPREG => DISPREG
|
| 316 |
|
|
);
|
| 317 |
|
|
|
| 318 |
|
|
SRES_OR_1 : ib_sres_or_4
|
| 319 |
|
|
port map (
|
| 320 |
|
|
IB_SRES_1 => IB_SRES_KW11P,
|
| 321 |
|
|
IB_SRES_2 => IB_SRES_IIST,
|
| 322 |
|
|
IB_SRES_3 => IB_SRES_KW11L,
|
| 323 |
|
|
IB_SRES_4 => IB_SRES_DEUNA,
|
| 324 |
|
|
IB_SRES_OR => IB_SRES_1
|
| 325 |
|
|
);
|
| 326 |
|
|
|
| 327 |
|
|
SRES_OR_2 : ib_sres_or_4
|
| 328 |
|
|
port map (
|
| 329 |
|
|
IB_SRES_1 => IB_SRES_RP06,
|
| 330 |
|
|
IB_SRES_2 => IB_SRES_RL11,
|
| 331 |
|
|
IB_SRES_3 => IB_SRES_RK11,
|
| 332 |
|
|
IB_SRES_4 => IB_SRES_TM11,
|
| 333 |
|
|
IB_SRES_OR => IB_SRES_2
|
| 334 |
|
|
);
|
| 335 |
|
|
|
| 336 |
|
|
SRES_OR_3 : ib_sres_or_3
|
| 337 |
|
|
port map (
|
| 338 |
|
|
IB_SRES_1 => IB_SRES_DZ11,
|
| 339 |
|
|
IB_SRES_2 => IB_SRES_DL11_0,
|
| 340 |
|
|
IB_SRES_3 => IB_SRES_DL11_1,
|
| 341 |
|
|
IB_SRES_OR => IB_SRES_3
|
| 342 |
|
|
);
|
| 343 |
|
|
|
| 344 |
|
|
SRES_OR_4 : ib_sres_or_3
|
| 345 |
|
|
port map (
|
| 346 |
|
|
IB_SRES_1 => IB_SRES_PC11,
|
| 347 |
|
|
IB_SRES_2 => IB_SRES_LP11,
|
| 348 |
|
|
IB_SRES_3 => IB_SRES_SDREG,
|
| 349 |
|
|
IB_SRES_OR => IB_SRES_4
|
| 350 |
|
|
);
|
| 351 |
|
|
|
| 352 |
|
|
SRES_OR : ib_sres_or_4
|
| 353 |
|
|
port map (
|
| 354 |
|
|
IB_SRES_1 => IB_SRES_1,
|
| 355 |
|
|
IB_SRES_2 => IB_SRES_2,
|
| 356 |
|
|
IB_SRES_3 => IB_SRES_3,
|
| 357 |
|
|
IB_SRES_4 => IB_SRES_4,
|
| 358 |
|
|
IB_SRES_OR => IB_SRES
|
| 359 |
|
|
);
|
| 360 |
|
|
|
| 361 |
|
|
INTMAP : ib_intmap
|
| 362 |
|
|
generic map (
|
| 363 |
|
|
INTMAP => conf_intmap)
|
| 364 |
|
|
port map (
|
| 365 |
|
|
EI_REQ => EI_REQ,
|
| 366 |
|
|
EI_ACKM => EI_ACKM,
|
| 367 |
|
|
EI_ACK => EI_ACK,
|
| 368 |
|
|
EI_PRI => EI_PRI,
|
| 369 |
|
|
EI_VECT => EI_VECT
|
| 370 |
|
|
);
|
| 371 |
|
|
|
| 372 |
|
|
EI_REQ(14) <= EI_REQ_KW11P;
|
| 373 |
|
|
EI_REQ(13) <= EI_REQ_IIST;
|
| 374 |
|
|
EI_REQ(12) <= EI_REQ_KW11L;
|
| 375 |
|
|
EI_REQ(11) <= EI_REQ_RL11;
|
| 376 |
|
|
EI_REQ(10) <= EI_REQ_RK11;
|
| 377 |
|
|
EI_REQ( 9) <= EI_REQ_DZ11RX;
|
| 378 |
|
|
EI_REQ( 8) <= EI_REQ_DZ11TX;
|
| 379 |
|
|
EI_REQ( 7) <= EI_REQ_DL11RX_0;
|
| 380 |
|
|
EI_REQ( 6) <= EI_REQ_DL11TX_0;
|
| 381 |
|
|
EI_REQ( 5) <= EI_REQ_DL11RX_1;
|
| 382 |
|
|
EI_REQ( 4) <= EI_REQ_DL11TX_1;
|
| 383 |
|
|
EI_REQ( 3) <= EI_REQ_PC11PTR;
|
| 384 |
|
|
EI_REQ( 2) <= EI_REQ_PC11PTP;
|
| 385 |
|
|
EI_REQ( 1) <= EI_REQ_LP11;
|
| 386 |
|
|
|
| 387 |
|
|
EI_ACK_KW11P <= EI_ACK(14);
|
| 388 |
|
|
EI_ACK_IIST <= EI_ACK(13);
|
| 389 |
|
|
EI_ACK_KW11L <= EI_ACK(12);
|
| 390 |
|
|
EI_ACK_RL11 <= EI_ACK(11);
|
| 391 |
|
|
EI_ACK_RK11 <= EI_ACK(10);
|
| 392 |
|
|
EI_ACK_DZ11RX <= EI_ACK( 9);
|
| 393 |
|
|
EI_ACK_DZ11TX <= EI_ACK( 8);
|
| 394 |
|
|
EI_ACK_DL11RX_0 <= EI_ACK( 7);
|
| 395 |
|
|
EI_ACK_DL11TX_0 <= EI_ACK( 6);
|
| 396 |
|
|
EI_ACK_DL11RX_1 <= EI_ACK( 5);
|
| 397 |
|
|
EI_ACK_DL11TX_1 <= EI_ACK( 4);
|
| 398 |
|
|
EI_ACK_PC11PTR <= EI_ACK( 3);
|
| 399 |
|
|
EI_ACK_PC11PTP <= EI_ACK( 2);
|
| 400 |
|
|
EI_ACK_LP11 <= EI_ACK( 1);
|
| 401 |
|
|
|
| 402 |
|
|
RRI_LAM(15 downto 11) <= (others=>'0');
|
| 403 |
|
|
RRI_LAM(10) <= RRI_LAM_PC11;
|
| 404 |
|
|
RRI_LAM( 9) <= RRI_LAM_DENUA;
|
| 405 |
|
|
RRI_LAM( 8) <= RRI_LAM_LP11;
|
| 406 |
|
|
RRI_LAM( 7) <= RRI_LAM_TM11;
|
| 407 |
|
|
RRI_LAM( 6) <= RRI_LAM_RP06;
|
| 408 |
|
|
RRI_LAM( 5) <= RRI_LAM_RL11;
|
| 409 |
|
|
RRI_LAM( 4) <= RRI_LAM_RK11;
|
| 410 |
|
|
RRI_LAM( 3) <= RRI_LAM_DZ11;
|
| 411 |
|
|
RRI_LAM( 2) <= RRI_LAM_DL11_1;
|
| 412 |
|
|
RRI_LAM( 1) <= RRI_LAM_DL11_0;
|
| 413 |
|
|
|
| 414 |
|
|
end syn;
|
