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-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name:    ram_2swsr_xfirst_gen_unisim - syn
-- Description:    Dual-Port RAM with with two synchronous read/write ports
--                 Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies:   -
-- Test bench:     -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History: 
-- Date         Rev Version  Comment
-- 2008-04-13   135   1.0.1  fix range error for AW_14_S1
-- 2008-03-08   123   1.0    Initial version (merged from _rfirst/_wfirst) 
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_2swsr_xfirst_gen_unisim is   -- RAM, 2 sync r/w ports
  generic (
    AWIDTH : positive := 11;            -- address port width
    DWIDTH : positive :=  9;            -- data port width
    WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
  port(
    CLKA  : in slbit;                   -- clock port A
    CLKB  : in slbit;                   -- clock port B
    ENA   : in slbit;                   -- enable port A
    ENB   : in slbit;                   -- enable port B
    WEA   : in slbit;                   -- write enable port A
    WEB   : in slbit;                   -- write enable port B
    ADDRA : in slv(AWIDTH-1 downto 0);  -- address port A
    ADDRB : in slv(AWIDTH-1 downto 0);  -- address port B
    DIA   : in slv(DWIDTH-1 downto 0);  -- data in port A
    DIB   : in slv(DWIDTH-1 downto 0);  -- data in port B
    DOA   : out slv(DWIDTH-1 downto 0); -- data out port A
    DOB   : out slv(DWIDTH-1 downto 0)  -- data out port B
  );
end ram_2swsr_xfirst_gen_unisim;
 
 
architecture syn of ram_2swsr_xfirst_gen_unisim is
 
  constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+35)/36)=((DWIDTH+31)/32);
  constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
                                 ((DWIDTH+17)/18)=((DWIDTH+16)/16);
  constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+8)/9)=((DWIDTH+7)/8);
 
begin
 
  assert AWIDTH>=9 and AWIDTH<=14
    report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
    severity failure;
 
  AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
    constant dw_mem : positive := ((DWIDTH+35)/36)*36;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
   GL: for i in dw_mem/36-1 downto 0 generate
      MEM : RAMB16_S36_S36
        generic map (
          INIT_A       => O"000000000000",
          INIT_B       => O"000000000000",
          SRVAL_A      => O"000000000000",
          SRVAL_B      => O"000000000000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(36*i+31 downto 36*i),
          DOB   => L_DOB(36*i+31 downto 36*i),
          DOPA  => L_DOA(36*i+35 downto 36*i+32),
          DOPB  => L_DOB(36*i+35 downto 36*i+32),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(36*i+31 downto 36*i),
          DIB   => L_DIB(36*i+31 downto 36*i),
          DIPA  => L_DIA(36*i+35 downto 36*i+32),
          DIPB  => L_DIB(36*i+35 downto 36*i+32),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_09_S36;
 
  AW_09_S32: if AWIDTH=9 and ok_mod32 generate
    GL: for i in DWIDTH/32-1 downto 0 generate
      MEM : RAMB16_S36_S36
        generic map (
          INIT_A       => X"00000000",
          INIT_B       => X"00000000",
          SRVAL_A      => X"00000000",
          SRVAL_B      => X"00000000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(32*i+31 downto 32*i),
          DOB   => DOB(32*i+31 downto 32*i),
          DOPA  => open,
          DOPB  => open,
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(32*i+31 downto 32*i),
          DIB   => DIB(32*i+31 downto 32*i),
          DIPA  => "0000",
          DIPB  => "0000",
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_09_S32;
 
  AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
    constant dw_mem : positive := ((DWIDTH+17)/18)*18;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/18-1 downto 0 generate
      MEM : RAMB16_S18_S18
        generic map (
          INIT_A       => O"000000",
          INIT_B       => O"000000",
          SRVAL_A      => O"000000",
          SRVAL_B      => O"000000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(18*i+15 downto 18*i),
          DOB   => L_DOB(18*i+15 downto 18*i),
          DOPA  => L_DOA(18*i+17 downto 18*i+16),
          DOPB  => L_DOB(18*i+17 downto 18*i+16),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(18*i+15 downto 18*i),
          DIB   => L_DIB(18*i+15 downto 18*i),
          DIPA  => L_DIA(18*i+17 downto 18*i+16),
          DIPB  => L_DIB(18*i+17 downto 18*i+16),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_10_S18;
 
  AW_10_S16: if AWIDTH=10 and ok_mod16 generate
    GL: for i in DWIDTH/16-1 downto 0 generate
      MEM : RAMB16_S18_S18
        generic map (
          INIT_A       => X"0000",
          INIT_B       => X"0000",
          SRVAL_A      => X"0000",
          SRVAL_B      => X"0000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(16*i+15 downto 16*i),
          DOB   => DOB(16*i+15 downto 16*i),
          DOPA  => open,
          DOPB  => open,
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(16*i+15 downto 16*i),
          DIB   => DIB(16*i+15 downto 16*i),
          DIPA  => "00",
          DIPB  => "00",
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_10_S16;
 
  AW_11_S9: if AWIDTH=11  and not ok_mod08 generate
    constant dw_mem : positive := ((DWIDTH+8)/9)*9;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/9-1 downto 0 generate
      MEM : RAMB16_S9_S9
        generic map (
          INIT_A       => O"000",
          INIT_B       => O"000",
          SRVAL_A      => O"000",
          SRVAL_B      => O"000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(9*i+7 downto 9*i),
          DOB   => L_DOB(9*i+7 downto 9*i),
          DOPA  => L_DOA(9*i+8 downto 9*i+8),
          DOPB  => L_DOB(9*i+8 downto 9*i+8),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(9*i+7 downto 9*i),
          DIB   => L_DIB(9*i+7 downto 9*i),
          DIPA  => L_DIA(9*i+8 downto 9*i+8),
          DIPB  => L_DIB(9*i+8 downto 9*i+8),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_11_S9;
 
  AW_11_S8: if AWIDTH=11 and ok_mod08 generate
    GL: for i in DWIDTH/8-1 downto 0 generate
      MEM : RAMB16_S9_S9
        generic map (
          INIT_A       => X"00",
          INIT_B       => X"00",
          SRVAL_A      => X"00",
          SRVAL_B      => X"00",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(8*i+7 downto 8*i),
          DOB   => DOB(8*i+7 downto 8*i),
          DOPA  => open,
          DOPB  => open,
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(8*i+7 downto 8*i),
          DIB   => DIB(8*i+7 downto 8*i),
          DIPA  => "0",
          DIPB  => "0",
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_11_S8;
 
  AW_12_S4: if AWIDTH = 12 generate
    constant dw_mem : positive := ((DWIDTH+3)/4)*4;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/4-1 downto 0 generate
      MEM : RAMB16_S4_S4
        generic map (
          INIT_A       => X"0",
          INIT_B       => X"0",
          SRVAL_A      => X"0",
          SRVAL_B      => X"0",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(4*i+3 downto 4*i),
          DOB   => L_DOB(4*i+3 downto 4*i),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(4*i+3 downto 4*i),
          DIB   => L_DIB(4*i+3 downto 4*i),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_12_S4;
 
  AW_13_S2: if AWIDTH = 13 generate
    constant dw_mem : positive := ((DWIDTH+1)/2)*2;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/2-1 downto 0 generate
      MEM : RAMB16_S2_S2
        generic map (
          INIT_A       => "00",
          INIT_B       => "00",
          SRVAL_A      => "00",
          SRVAL_B      => "00",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(2*i+1 downto 2*i),
          DOB   => L_DOB(2*i+1 downto 2*i),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(2*i+1 downto 2*i),
          DIB   => L_DIB(2*i+1 downto 2*i),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_13_S2;
 
  AW_14_S1: if AWIDTH = 14 generate
    GL: for i in DWIDTH-1 downto 0 generate
      MEM : RAMB16_S1_S1
        generic map (
          INIT_A       => "0",
          INIT_B       => "0",
          SRVAL_A      => "0",
          SRVAL_B      => "0",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(i downto i),
          DOB   => DOB(i downto i),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(i downto i),
          DIB   => DIB(i downto i),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_14_S1;
 
 
end syn;
 
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
--       nonsense:  INIT_A : bit_vector := X"000";
--       This is a 12 bit value, while a 9 bit one is needed. Thus the
--       explicit definition above.

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[/] [w11/] [tags/] [w11a_V0.5/] [rtl/] [vlib/] [memlib/] [ram_2swsr_xfirst_gen_unisim.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	2	wfjm	`-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $`
2			`--`
3			`-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Module Name: ram_2swsr_xfirst_gen_unisim - syn`
16			`-- Description: Dual-Port RAM with with two synchronous read/write ports`
17			`-- Direct instantiation of Xilinx UNISIM primitives`
18			`--`
19			`-- Dependencies: -`
20			`-- Test bench: -`
21			`-- Target Devices: Spartan-3, Virtex-2,-4`
22			`-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25`
23			`-- Revision History:`
24			`-- Date Rev Version Comment`
25			`-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1`
26			`-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)`
27			`------------------------------------------------------------------------------`
28
29			`library ieee;`
30			`use ieee.std_logic_1164.all;`
31
32			`library unisim;`
33			`use unisim.vcomponents.ALL;`
34
35			`use work.slvtypes.all;`
36
37			`entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports`
38			`generic (`
39			`AWIDTH : positive := 11; -- address port width`
40			`DWIDTH : positive := 9; -- data port width`
41			`WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ\|WRITE)_FIRST`
42			`port(`
43			`CLKA : in slbit; -- clock port A`
44			`CLKB : in slbit; -- clock port B`
45			`ENA : in slbit; -- enable port A`
46			`ENB : in slbit; -- enable port B`
47			`WEA : in slbit; -- write enable port A`
48			`WEB : in slbit; -- write enable port B`
49			`ADDRA : in slv(AWIDTH-1 downto 0); -- address port A`
50			`ADDRB : in slv(AWIDTH-1 downto 0); -- address port B`
51			`DIA : in slv(DWIDTH-1 downto 0); -- data in port A`
52			`DIB : in slv(DWIDTH-1 downto 0); -- data in port B`
53			`DOA : out slv(DWIDTH-1 downto 0); -- data out port A`
54			`DOB : out slv(DWIDTH-1 downto 0) -- data out port B`
55			`);`
56			`end ram_2swsr_xfirst_gen_unisim;`
57
58
59			`architecture syn of ram_2swsr_xfirst_gen_unisim is`
60
61			`constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and`
62			`((DWIDTH+35)/36)=((DWIDTH+31)/32);`
63			`constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and`
64			`((DWIDTH+17)/18)=((DWIDTH+16)/16);`
65			`constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and`
66			`((DWIDTH+8)/9)=((DWIDTH+7)/8);`
67
68			`begin`
69
70			`assert AWIDTH>=9 and AWIDTH<=14`
71			`report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"`
72			`severity failure;`
73
74			`AW_09_S36: if AWIDTH=9 and not ok_mod32 generate`
75			`constant dw_mem : positive := ((DWIDTH+35)/36)*36;`
76			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
77			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
78			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
79			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
80			`begin`
81
82			`L_DIA(DIA'range) <= DIA;`
83			`L_DIB(DIB'range) <= DIB;`
84
85			`GL: for i in dw_mem/36-1 downto 0 generate`
86			`MEM : RAMB16_S36_S36`
87			`generic map (`
88			`INIT_A => O"000000000000",`
89			`INIT_B => O"000000000000",`
90			`SRVAL_A => O"000000000000",`
91			`SRVAL_B => O"000000000000",`
92			`WRITE_MODE_A => WRITE_MODE,`
93			`WRITE_MODE_B => WRITE_MODE)`
94			`port map (`
95			`DOA => L_DOA(36i+31 downto 36i),`
96			`DOB => L_DOB(36i+31 downto 36i),`
97			`DOPA => L_DOA(36i+35 downto 36i+32),`
98			`DOPB => L_DOB(36i+35 downto 36i+32),`
99			`ADDRA => ADDRA,`
100			`ADDRB => ADDRB,`
101			`CLKA => CLKA,`
102			`CLKB => CLKB,`
103			`DIA => L_DIA(36i+31 downto 36i),`
104			`DIB => L_DIB(36i+31 downto 36i),`
105			`DIPA => L_DIA(36i+35 downto 36i+32),`
106			`DIPB => L_DIB(36i+35 downto 36i+32),`
107			`ENA => ENA,`
108			`ENB => ENB,`
109			`SSRA => '0',`
110			`SSRB => '0',`
111			`WEA => WEA,`
112			`WEB => WEB`
113			`);`
114			`end generate GL;`
115
116			`DOA <= L_DOA(DOA'range);`
117			`DOB <= L_DOB(DOB'range);`
118
119			`end generate AW_09_S36;`
120
121			`AW_09_S32: if AWIDTH=9 and ok_mod32 generate`
122			`GL: for i in DWIDTH/32-1 downto 0 generate`
123			`MEM : RAMB16_S36_S36`
124			`generic map (`
125			`INIT_A => X"00000000",`
126			`INIT_B => X"00000000",`
127			`SRVAL_A => X"00000000",`
128			`SRVAL_B => X"00000000",`
129			`WRITE_MODE_A => WRITE_MODE,`
130			`WRITE_MODE_B => WRITE_MODE)`
131			`port map (`
132			`DOA => DOA(32i+31 downto 32i),`
133			`DOB => DOB(32i+31 downto 32i),`
134			`DOPA => open,`
135			`DOPB => open,`
136			`ADDRA => ADDRA,`
137			`ADDRB => ADDRB,`
138			`CLKA => CLKA,`
139			`CLKB => CLKB,`
140			`DIA => DIA(32i+31 downto 32i),`
141			`DIB => DIB(32i+31 downto 32i),`
142			`DIPA => "0000",`
143			`DIPB => "0000",`
144			`ENA => ENA,`
145			`ENB => ENB,`
146			`SSRA => '0',`
147			`SSRB => '0',`
148			`WEA => WEA,`
149			`WEB => WEB`
150			`);`
151			`end generate GL;`
152			`end generate AW_09_S32;`
153
154			`AW_10_S18: if AWIDTH=10 and not ok_mod16 generate`
155			`constant dw_mem : positive := ((DWIDTH+17)/18)*18;`
156			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
157			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
158			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
159			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
160			`begin`
161
162			`L_DIA(DIA'range) <= DIA;`
163			`L_DIB(DIB'range) <= DIB;`
164
165			`GL: for i in dw_mem/18-1 downto 0 generate`
166			`MEM : RAMB16_S18_S18`
167			`generic map (`
168			`INIT_A => O"000000",`
169			`INIT_B => O"000000",`
170			`SRVAL_A => O"000000",`
171			`SRVAL_B => O"000000",`
172			`WRITE_MODE_A => WRITE_MODE,`
173			`WRITE_MODE_B => WRITE_MODE)`
174			`port map (`
175			`DOA => L_DOA(18i+15 downto 18i),`
176			`DOB => L_DOB(18i+15 downto 18i),`
177			`DOPA => L_DOA(18i+17 downto 18i+16),`
178			`DOPB => L_DOB(18i+17 downto 18i+16),`
179			`ADDRA => ADDRA,`
180			`ADDRB => ADDRB,`
181			`CLKA => CLKA,`
182			`CLKB => CLKB,`
183			`DIA => L_DIA(18i+15 downto 18i),`
184			`DIB => L_DIB(18i+15 downto 18i),`
185			`DIPA => L_DIA(18i+17 downto 18i+16),`
186			`DIPB => L_DIB(18i+17 downto 18i+16),`
187			`ENA => ENA,`
188			`ENB => ENB,`
189			`SSRA => '0',`
190			`SSRB => '0',`
191			`WEA => WEA,`
192			`WEB => WEB`
193			`);`
194			`end generate GL;`
195
196			`DOA <= L_DOA(DOA'range);`
197			`DOB <= L_DOB(DOB'range);`
198
199			`end generate AW_10_S18;`
200
201			`AW_10_S16: if AWIDTH=10 and ok_mod16 generate`
202			`GL: for i in DWIDTH/16-1 downto 0 generate`
203			`MEM : RAMB16_S18_S18`
204			`generic map (`
205			`INIT_A => X"0000",`
206			`INIT_B => X"0000",`
207			`SRVAL_A => X"0000",`
208			`SRVAL_B => X"0000",`
209			`WRITE_MODE_A => WRITE_MODE,`
210			`WRITE_MODE_B => WRITE_MODE)`
211			`port map (`
212			`DOA => DOA(16i+15 downto 16i),`
213			`DOB => DOB(16i+15 downto 16i),`
214			`DOPA => open,`
215			`DOPB => open,`
216			`ADDRA => ADDRA,`
217			`ADDRB => ADDRB,`
218			`CLKA => CLKA,`
219			`CLKB => CLKB,`
220			`DIA => DIA(16i+15 downto 16i),`
221			`DIB => DIB(16i+15 downto 16i),`
222			`DIPA => "00",`
223			`DIPB => "00",`
224			`ENA => ENA,`
225			`ENB => ENB,`
226			`SSRA => '0',`
227			`SSRB => '0',`
228			`WEA => WEA,`
229			`WEB => WEB`
230			`);`
231			`end generate GL;`
232			`end generate AW_10_S16;`
233
234			`AW_11_S9: if AWIDTH=11 and not ok_mod08 generate`
235			`constant dw_mem : positive := ((DWIDTH+8)/9)*9;`
236			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
237			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
238			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
239			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
240			`begin`
241
242			`L_DIA(DIA'range) <= DIA;`
243			`L_DIB(DIB'range) <= DIB;`
244
245			`GL: for i in dw_mem/9-1 downto 0 generate`
246			`MEM : RAMB16_S9_S9`
247			`generic map (`
248			`INIT_A => O"000",`
249			`INIT_B => O"000",`
250			`SRVAL_A => O"000",`
251			`SRVAL_B => O"000",`
252			`WRITE_MODE_A => WRITE_MODE,`
253			`WRITE_MODE_B => WRITE_MODE)`
254			`port map (`
255			`DOA => L_DOA(9i+7 downto 9i),`
256			`DOB => L_DOB(9i+7 downto 9i),`
257			`DOPA => L_DOA(9i+8 downto 9i+8),`
258			`DOPB => L_DOB(9i+8 downto 9i+8),`
259			`ADDRA => ADDRA,`
260			`ADDRB => ADDRB,`
261			`CLKA => CLKA,`
262			`CLKB => CLKB,`
263			`DIA => L_DIA(9i+7 downto 9i),`
264			`DIB => L_DIB(9i+7 downto 9i),`
265			`DIPA => L_DIA(9i+8 downto 9i+8),`
266			`DIPB => L_DIB(9i+8 downto 9i+8),`
267			`ENA => ENA,`
268			`ENB => ENB,`
269			`SSRA => '0',`
270			`SSRB => '0',`
271			`WEA => WEA,`
272			`WEB => WEB`
273			`);`
274			`end generate GL;`
275
276			`DOA <= L_DOA(DOA'range);`
277			`DOB <= L_DOB(DOB'range);`
278
279			`end generate AW_11_S9;`
280
281			`AW_11_S8: if AWIDTH=11 and ok_mod08 generate`
282			`GL: for i in DWIDTH/8-1 downto 0 generate`
283			`MEM : RAMB16_S9_S9`
284			`generic map (`
285			`INIT_A => X"00",`
286			`INIT_B => X"00",`
287			`SRVAL_A => X"00",`
288			`SRVAL_B => X"00",`
289			`WRITE_MODE_A => WRITE_MODE,`
290			`WRITE_MODE_B => WRITE_MODE)`
291			`port map (`
292			`DOA => DOA(8i+7 downto 8i),`
293			`DOB => DOB(8i+7 downto 8i),`
294			`DOPA => open,`
295			`DOPB => open,`
296			`ADDRA => ADDRA,`
297			`ADDRB => ADDRB,`
298			`CLKA => CLKA,`
299			`CLKB => CLKB,`
300			`DIA => DIA(8i+7 downto 8i),`
301			`DIB => DIB(8i+7 downto 8i),`
302			`DIPA => "0",`
303			`DIPB => "0",`
304			`ENA => ENA,`
305			`ENB => ENB,`
306			`SSRA => '0',`
307			`SSRB => '0',`
308			`WEA => WEA,`
309			`WEB => WEB`
310			`);`
311			`end generate GL;`
312			`end generate AW_11_S8;`
313
314			`AW_12_S4: if AWIDTH = 12 generate`
315			`constant dw_mem : positive := ((DWIDTH+3)/4)*4;`
316			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
317			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
318			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
319			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
320			`begin`
321
322			`L_DIA(DIA'range) <= DIA;`
323			`L_DIB(DIB'range) <= DIB;`
324
325			`GL: for i in dw_mem/4-1 downto 0 generate`
326			`MEM : RAMB16_S4_S4`
327			`generic map (`
328			`INIT_A => X"0",`
329			`INIT_B => X"0",`
330			`SRVAL_A => X"0",`
331			`SRVAL_B => X"0",`
332			`WRITE_MODE_A => WRITE_MODE,`
333			`WRITE_MODE_B => WRITE_MODE)`
334			`port map (`
335			`DOA => L_DOA(4i+3 downto 4i),`
336			`DOB => L_DOB(4i+3 downto 4i),`
337			`ADDRA => ADDRA,`
338			`ADDRB => ADDRB,`
339			`CLKA => CLKA,`
340			`CLKB => CLKB,`
341			`DIA => L_DIA(4i+3 downto 4i),`
342			`DIB => L_DIB(4i+3 downto 4i),`
343			`ENA => ENA,`
344			`ENB => ENB,`
345			`SSRA => '0',`
346			`SSRB => '0',`
347			`WEA => WEA,`
348			`WEB => WEB`
349			`);`
350			`end generate GL;`
351
352			`DOA <= L_DOA(DOA'range);`
353			`DOB <= L_DOB(DOB'range);`
354
355			`end generate AW_12_S4;`
356
357			`AW_13_S2: if AWIDTH = 13 generate`
358			`constant dw_mem : positive := ((DWIDTH+1)/2)*2;`
359			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
360			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
361			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
362			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
363			`begin`
364
365			`L_DIA(DIA'range) <= DIA;`
366			`L_DIB(DIB'range) <= DIB;`
367
368			`GL: for i in dw_mem/2-1 downto 0 generate`
369			`MEM : RAMB16_S2_S2`
370			`generic map (`
371			`INIT_A => "00",`
372			`INIT_B => "00",`
373			`SRVAL_A => "00",`
374			`SRVAL_B => "00",`
375			`WRITE_MODE_A => WRITE_MODE,`
376			`WRITE_MODE_B => WRITE_MODE)`
377			`port map (`
378			`DOA => L_DOA(2i+1 downto 2i),`
379			`DOB => L_DOB(2i+1 downto 2i),`
380			`ADDRA => ADDRA,`
381			`ADDRB => ADDRB,`
382			`CLKA => CLKA,`
383			`CLKB => CLKB,`
384			`DIA => L_DIA(2i+1 downto 2i),`
385			`DIB => L_DIB(2i+1 downto 2i),`
386			`ENA => ENA,`
387			`ENB => ENB,`
388			`SSRA => '0',`
389			`SSRB => '0',`
390			`WEA => WEA,`
391			`WEB => WEB`
392			`);`
393			`end generate GL;`
394
395			`DOA <= L_DOA(DOA'range);`
396			`DOB <= L_DOB(DOB'range);`
397
398			`end generate AW_13_S2;`
399
400			`AW_14_S1: if AWIDTH = 14 generate`
401			`GL: for i in DWIDTH-1 downto 0 generate`
402			`MEM : RAMB16_S1_S1`
403			`generic map (`
404			`INIT_A => "0",`
405			`INIT_B => "0",`
406			`SRVAL_A => "0",`
407			`SRVAL_B => "0",`
408			`WRITE_MODE_A => WRITE_MODE,`
409			`WRITE_MODE_B => WRITE_MODE)`
410			`port map (`
411			`DOA => DOA(i downto i),`
412			`DOB => DOB(i downto i),`
413			`ADDRA => ADDRA,`
414			`ADDRB => ADDRB,`
415			`CLKA => CLKA,`
416			`CLKB => CLKB,`
417			`DIA => DIA(i downto i),`
418			`DIB => DIB(i downto i),`
419			`ENA => ENA,`
420			`ENB => ENB,`
421			`SSRA => '0',`
422			`SSRB => '0',`
423			`WEA => WEA,`
424			`WEB => WEB`
425			`);`
426			`end generate GL;`
427			`end generate AW_14_S1;`
428
429
430			`end syn;`
431
432			`-- Note: in XST 8.2 the defaults for INIT_(A\|B) and SRVAL_(A\|B) are`
433			`-- nonsense: INIT_A : bit_vector := X"000";`
434			`-- This is a 12 bit value, while a 9 bit one is needed. Thus the`
435			`-- explicit definition above.`