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-- $Id: rb_sres_or_2.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: rb_sres_or_2 - syn
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-- Description: rribus result or, 2 input
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--
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-- Dependencies: rritb_sres_or_mon [sim only]
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-06-26 309 1.1 add rritb_sres_or_mon
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-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
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-- 2008-01-20 113 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.rrilib.all;
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-- synthesis translate_off
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use work.rritblib.all;
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-- synthesis translate_on
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-- ----------------------------------------------------------------------------
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entity rb_sres_or_2 is -- rribus result or, 2 input
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port (
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RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
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RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
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RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
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);
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end rb_sres_or_2;
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architecture syn of rb_sres_or_2 is
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begin
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proc_comb : process (RB_SRES_1, RB_SRES_2)
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begin
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RB_SRES_OR.ack <= RB_SRES_1.ack or
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RB_SRES_2.ack;
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RB_SRES_OR.busy <= RB_SRES_1.busy or
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RB_SRES_2.busy;
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RB_SRES_OR.err <= RB_SRES_1.err or
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RB_SRES_2.err;
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RB_SRES_OR.dout <= RB_SRES_1.dout or
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RB_SRES_2.dout;
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end process proc_comb;
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-- synthesis translate_off
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ORMON : rritb_sres_or_mon
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port map (
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RB_SRES_1 => RB_SRES_1,
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RB_SRES_2 => RB_SRES_2,
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RB_SRES_3 => rb_sres_init,
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RB_SRES_4 => rb_sres_init
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);
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-- synthesis translate_on
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end syn;
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