| 1 |
2 |
wfjm |
-- $Id: rb_sres_or_3.vhd 314 2010-07-09 17:38:41Z mueller $
|
| 2 |
|
|
--
|
| 3 |
|
|
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
| 4 |
|
|
--
|
| 5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
| 6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
| 7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
| 8 |
|
|
--
|
| 9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
| 10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
| 11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 12 |
|
|
-- for complete details.
|
| 13 |
|
|
--
|
| 14 |
|
|
------------------------------------------------------------------------------
|
| 15 |
|
|
-- Module Name: rb_sres_or_3 - syn
|
| 16 |
|
|
-- Description: rribus result or, 3 input
|
| 17 |
|
|
--
|
| 18 |
|
|
-- Dependencies: rritb_sres_or_mon [sim only]
|
| 19 |
|
|
-- Test bench: -
|
| 20 |
|
|
-- Target Devices: generic
|
| 21 |
|
|
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
|
| 22 |
|
|
-- Revision History:
|
| 23 |
|
|
-- Date Rev Version Comment
|
| 24 |
|
|
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
|
| 25 |
|
|
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
|
| 26 |
|
|
-- 2008-01-20 113 1.0 Initial version
|
| 27 |
|
|
------------------------------------------------------------------------------
|
| 28 |
|
|
|
| 29 |
|
|
library ieee;
|
| 30 |
|
|
use ieee.std_logic_1164.all;
|
| 31 |
|
|
|
| 32 |
|
|
use work.slvtypes.all;
|
| 33 |
|
|
use work.rrilib.all;
|
| 34 |
|
|
-- synthesis translate_off
|
| 35 |
|
|
use work.rritblib.all;
|
| 36 |
|
|
-- synthesis translate_on
|
| 37 |
|
|
|
| 38 |
|
|
-- ----------------------------------------------------------------------------
|
| 39 |
|
|
|
| 40 |
|
|
entity rb_sres_or_3 is -- rribus result or, 3 input
|
| 41 |
|
|
port (
|
| 42 |
|
|
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
|
| 43 |
|
|
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
|
| 44 |
|
|
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
|
| 45 |
|
|
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
|
| 46 |
|
|
);
|
| 47 |
|
|
end rb_sres_or_3;
|
| 48 |
|
|
|
| 49 |
|
|
architecture syn of rb_sres_or_3 is
|
| 50 |
|
|
|
| 51 |
|
|
begin
|
| 52 |
|
|
|
| 53 |
|
|
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3)
|
| 54 |
|
|
begin
|
| 55 |
|
|
|
| 56 |
|
|
RB_SRES_OR.ack <= RB_SRES_1.ack or
|
| 57 |
|
|
RB_SRES_2.ack or
|
| 58 |
|
|
RB_SRES_3.ack;
|
| 59 |
|
|
RB_SRES_OR.busy <= RB_SRES_1.busy or
|
| 60 |
|
|
RB_SRES_2.busy or
|
| 61 |
|
|
RB_SRES_3.busy;
|
| 62 |
|
|
RB_SRES_OR.err <= RB_SRES_1.err or
|
| 63 |
|
|
RB_SRES_2.err or
|
| 64 |
|
|
RB_SRES_3.err;
|
| 65 |
|
|
RB_SRES_OR.dout <= RB_SRES_1.dout or
|
| 66 |
|
|
RB_SRES_2.dout or
|
| 67 |
|
|
RB_SRES_3.dout;
|
| 68 |
|
|
|
| 69 |
|
|
end process proc_comb;
|
| 70 |
|
|
|
| 71 |
|
|
-- synthesis translate_off
|
| 72 |
|
|
ORMON : rritb_sres_or_mon
|
| 73 |
|
|
port map (
|
| 74 |
|
|
RB_SRES_1 => RB_SRES_1,
|
| 75 |
|
|
RB_SRES_2 => RB_SRES_2,
|
| 76 |
|
|
RB_SRES_3 => RB_SRES_3,
|
| 77 |
|
|
RB_SRES_4 => rb_sres_init
|
| 78 |
|
|
);
|
| 79 |
|
|
-- synthesis translate_on
|
| 80 |
|
|
|
| 81 |
|
|
end syn;
|
