URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.5/] [rtl/] [vlib/] [rri/] [tb/] [tb_rri.vbom] - Blame information for rev 7

Details | Compare with Previous | View Log


# Not meant for direct top level usage. Used with
# tb_rri_(core|serport|...)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../slvtypes.vhd
../../genlib/genlib.vhd
../../comlib/comlib.vhd
../rrilib.vhd
../../simlib/simlib.vhd
# components
../../simlib/simclk.vbom
../../genlib/clkdivce.vbom
tbd_rri_gen : tbd_rri_core.vbom
# design
tb_rri.vhd
@top:tb_rri

Line No.	Rev	Author	Line
1	2	wfjm	`# Not meant for direct top level usage. Used with`
2			`# tb_rri_(core\|serport\|...)[_ssim].vbom and config`
3			`# lines to generate the different cases.`
4			`#`
5			`# libs`
6			`../../slvtypes.vhd`
7			`../../genlib/genlib.vhd`
8			`../../comlib/comlib.vhd`
9			`../rrilib.vhd`
10			`../../simlib/simlib.vhd`
11			`# components`
12			`../../simlib/simclk.vbom`
13			`../../genlib/clkdivce.vbom`
14			`tbd_rri_gen : tbd_rri_core.vbom`
15			`# design`
16			`tb_rri.vhd`
17			`@top:tb_rri`

Browse

Tools

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.5/] [rtl/] [vlib/] [rri/] [tb/] [tb_rri.vbom] - Blame information for rev 7