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-- $Id: serport.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: serport
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-- Description: serial port interface components
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--
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-- Dependencies: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-04-10 276 1.2 add clock divider constant defs
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-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
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-- 2007-06-03 45 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package serport is
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-- clock divider constants assume 50 MHz clock
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constant serport_clkdiv_009600 : integer := 5208-1; -- 50000000/ 9600=5208.33
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constant serport_clkdiv_019200 : integer := 2604-1; -- 50000000/ 19200=2604.16
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constant serport_clkdiv_038400 : integer := 1302-1; -- 50000000/ 38400=1302.08
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constant serport_clkdiv_057600 : integer := 868-1; -- 50000000/ 57600= 868.05
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constant serport_clkdiv_115200 : integer := 434-1; -- 50000000/115200= 434.02
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constant serport_clkdiv_230400 : integer := 217-1; -- 50000000/230400= 217.01
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constant serport_clkdiv_460800 : integer := 109-1; -- 50000000/460800= 108.51
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constant serport_clkdiv_500000 : integer := 100-1; -- 50000000/500000= 100
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constant serport_clkdiv_576000 : integer := 87-1; -- 50000000/576000= 86.80
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constant serport_clkdiv_921600 : integer := 54-1; -- 50000000/921600= 54.25
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constant serport_clkdiv_1M : integer := 50-1; -- 50000000/1M = 50
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constant serport_clkdiv_2M : integer := 24-1; -- 50000000/2M = 25
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component serport_uart_rxtx is -- serial port uart: rx+tx combo
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit; -- receiver active
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit -- transmit busy
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);
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end component;
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component serport_uart_rx is -- serial port uart: receive part
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit -- receiver active
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);
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end component;
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component serport_uart_tx is -- serial port uart: transmit part
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit -- transmit busy
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);
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end component;
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component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT: natural := 15); -- clk divider initial/reset setting
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- 1 msec clock enable
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RESET : in slbit; -- reset
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit; -- receiver active
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit busy
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ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
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ABDONE : out slbit -- autobaud resync done
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);
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end component;
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component serport_uart_autobaud is -- serial port uart: autobauder
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT: natural := 15); -- clk divider initial/reset setting
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- 1 msec clock enable
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RESET : in slbit; -- reset
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RXSD : in slbit; -- receive serial data (uart view)
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CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
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ACT : out slbit; -- active; if 1 clkdiv is invalid
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DONE : out slbit -- resync done
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);
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end component;
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end serport;
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