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-- $Id: pdp11.vhd 314 2010-07-09 17:38:41Z mueller $

--

-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

--

-- This program is free software; you may redistribute and/or modify it under

-- the terms of the GNU General Public License as published by the Free

-- Software Foundation, either version 2, or at your option any later version.

--

-- This program is distributed in the hope that it will be useful, but

-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY

-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

-- for complete details.

--

------------------------------------------------------------------------------

-- Package Name:   pdp11

-- Description:    Definitions for pdp11 components

--

-- Dependencies:   -

-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26

-- Revision History: 

-- Date         Rev Version  Comment

-- 2010-06-20   308   1.4.3  add c_ibrb_ibf_ def's

-- 2010-06-20   307   1.4.2  rename cpacc to cacc in vm_cntl_type, mmu_cntl_type

-- 2010-06-18   306   1.4.1  add racc, be to cp_addr_type; rm pdp11_ibdr_rri

-- 2010-06-13   305   1.4    add rnum to cp_cntl_type, cprnum to cpustat_type;

--                           reassign cp command codes and rename: c_cp_func_...

--                           -> c_cpfunc_...; remove  cpaddr_(lal|lah|inc) from

--                           dpath_cntl_type; add cpdout_we to dpath_cntl_type;

--                           reassign rbus adresses and rename: c_rb_addr_...

--                           -> c_rbaddr_...; rename rbus fields: c_rb_statf_...

--                           -> c_stat_rbf_...

-- 2010-06-12   304   1.3.3  add cpuwait to cp_stat_type and cpustat_type

-- 2010-06-11   303   1.3.2  use IB_MREQ.racc instead of RRI_REQ

-- 2010-05-02   287   1.3.1  rename RP_STAT->RB_STAT

-- 2010-05-01   285   1.3    port to rri V2 interface; drop pdp11_rri_2rp;

--                           rename c_rp_addr_* -> c_rb_addr_*

-- 2010-03-21   270   1.2.6  add pdp11_du_drv

-- 2009-05-30   220   1.2.5  final removal of snoopers (were already commented)

-- 2009-05-10   214   1.2.4  add ENA (trace enable) for _tmu; add _pdp11_tmu_sb

-- 2009-05-09   213   1.2.3  BUGFIX: default for inst_compl now '0'

-- 2008-12-14   177   1.2.2  add gpr_* fields to DM_STAT_DP

-- 2008-11-30   174   1.2.1  BUGFIX: add updt_dstadsrc;

-- 2008-08-22   161   1.2    move slvnn_m subtypes to slvtypes;

--                           move (and rename) intbus defs to iblib package;

--                           move intbus devices to ibdlib package;

--                           rename ubf_ --> ibf_;

-- 2008-05-09   144   1.1.17 use EI_ACK with _kw11l, _dl11

-- 2008-05-03   143   1.1.16 rename _cpursta->_cpurust

-- 2008-04-27   140   1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat

-- 2008-04-25   138   1.1.14 add BRESET port to _mmu, _vmbox, use in _irq

-- 2008-04-19   137   1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports

-- 2008-04-18   136   1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET

-- 2008-03-02   121   1.1.11 remove snoopers; add waitsusp in cpustat_type

-- 2008-02-24   119   1.1.10 add lah,rps,wps commands, cp_addr_type.

--                           _vmbox,_mmu interface changed

-- 2008-02-17   117   1.1.9  add em_(mreq|sres)_type, pdp11_cache, pdp11_bram

-- 2008-01-27   115   1.1.8  add pdp11_ubmap, pdp11_mem70

-- 2008-01-26   114   1.1.7  add c_rp_addr_ibr(b) defs (for ibr addresses)

-- 2008-01-20   113   1.1.6  _core_rri: use RRI_LAM; _minisys: RRI_LAM vector

-- 2008-01-20   112   1.1.5  added ibdr_minisys; _ibdr_rri

-- 2008-01-06   111   1.1.4  rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)

--                           mod pdp11_intmap;

-- 2008-01-05   110   1.1.3  delete _mmu_regfile; rename _mmu_regs->_mmu_sadr

--                           rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)

--                           add ibdr_kw11l.

-- 2008-01-01   109   1.1.2  _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type

-- 2007-12-30   108   1.1.1  add ibdr_sdreg, ubf_byte[01]

-- 2007-12-30   107   1.1    use IB_MREQ/IB_SRES interface now; remove DMA port

-- 2007-08-16    74   1.0.6  add AP_LAM interface to pdp11_core_rri

-- 2007-08-12    73   1.0.5  add c_rp_addr_xxx and c_rp_statf_xxx def's

-- 2007-08-10    72   1.0.4  added c_cp_func_xxx constant def's for commands

-- 2007-07-15    66   1.0.3  rename pdp11_top -> pdp11_core

-- 2007-07-02    63   1.0.2  reordered ports on pdp11_top (by function, not i/o)

-- 2007-06-14    56   1.0.1  Use slvtypes.all

-- 2007-05-12    26   1.0    Initial version 

------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use work.slvtypes.all;

use work.iblib.all;

use work.rrilib.all;

package pdp11 is

  type psw_type is record               -- processor status

    cmode : slv2;                       -- current mode

    pmode : slv2;                       -- previous mode

    rset : slbit;                       -- register set

    pri : slv3;                         -- processor priority

    tflag : slbit;                      -- trace flag

    cc : slv4;                          -- condition codes (NZVC).

  end record psw_type;

  constant psw_init : psw_type := (

    "00","00",                          -- cmode, pmode  (=kernel)

    '0',"111",'0',                      -- rset, pri (=7), tflag

    "0000"                              -- cc     NZVC=0

  );

  constant c_psw_kmode : slv2 := "00";  -- processor mode: kernel

  constant c_psw_smode : slv2 := "01";  -- processor mode: supervisor

  constant c_psw_umode : slv2 := "11";  -- processor mode: user

  subtype  psw_ibf_cmode  is integer range 15 downto 14;

  subtype  psw_ibf_pmode  is integer range 13 downto 12;

  constant psw_ibf_rset:  integer := 11;

  subtype  psw_ibf_pri    is integer range  7 downto  5;

  constant psw_ibf_tflag: integer :=  4;

  subtype  psw_ibf_cc     is integer range  3 downto  0;

  type sarsdr_type is record            -- combined SAR/SDR MMU status

    saf : slv16;                        -- segment address field

    slf : slv7;                         -- segment length field

    ed : slbit;                         -- expansion direction

    acf : slv3;                         -- access control field

  end record sarsdr_type;

  constant sarsdr_init : sarsdr_type := (

    (others=>'0'),                      -- saf

    "0000000",'0',"000"                 -- slf, ed, acf

  );

  type dpath_cntl_type is record        -- data path control

    gpr_asrc : slv3;                    -- src register address

    gpr_adst : slv3;                    -- dst register address

    gpr_mode : slv2;                    -- psw mode for gpr access

    gpr_rset : slbit;                   -- register set

    gpr_we : slbit;                     -- gpr write enable

    gpr_bytop : slbit;                  -- gpr high byte enable

    gpr_pcinc : slbit;                  -- pc increment enable

    psr_ccwe : slbit;                   -- enable update cc

    psr_we: slbit;                      -- write enable psw (from DIN)

    psr_func : slv3;                    -- write function psw (from DIN)

    dsrc_sel : slbit;                   -- src data register source select

    dsrc_we : slbit;                    -- src data register write enable

    ddst_sel : slbit;                   -- dst data register source select

    ddst_we : slbit;                    -- dst data register write enable

    dtmp_sel : slv2;                    -- tmp data register source select

    dtmp_we : slbit;                    -- tmp data register write enable

    abox_asel : slv2;                   -- abox a port selector

    abox_azero : slbit;                 -- abox a port force zero

    abox_const : slv9;                  -- abox b port const

    abox_bsel : slv2;                   -- abox b port selector

    abox_opsub : slbit;                 -- abox operation

    dbox_srcmod : slv2;                 -- dbox src port modifier

    dbox_dstmod : slv2;                 -- dbox dst port modifier

    dbox_cimod : slv2;                  -- dbox ci port modifier

    dbox_cc1op : slbit;                 -- dbox use cc modes (1 op instruction)

    dbox_ccmode : slv3;                 -- dbox cc port mode

    dbox_bytop : slbit;                 -- dbox byte operation

    lbox_func : slv4;                   -- lbox function

    lbox_bytop : slbit;                 -- lbox byte operation

    mbox_func : slv2;                   -- mbox function

    mbox_s_div : slbit;                 -- mbox s_opg_div state

    mbox_s_div_cn : slbit;              -- mbox s_opg_div_cn state

    mbox_s_div_cr : slbit;              -- mbox s_opg_div_cr state

    mbox_s_ash : slbit;                 -- mbox s_opg_ash state

    mbox_s_ash_cn : slbit;              -- mbox s_opg_ash_cn state

    mbox_s_ashc : slbit;                -- mbox s_opg_ashc state

    mbox_s_ashc_cn : slbit;             -- mbox s_opg_ashc_cn state

    ireg_we : slbit;                    -- ireg register write enable

    cres_sel : slv3;                    -- result bus (cres) select

    dres_sel : slv3;                    -- result bus (dres) select

    vmaddr_sel : slv2;                  -- virtual address select

    cpdout_we : slbit;                  -- capture dres for cpdout

  end record dpath_cntl_type;

  constant dpath_cntl_init : dpath_cntl_type := (

    "000","000","00",'0','0','0','0',   -- gpr

    '0','0',"000",                      -- psr

    '0','0','0','0',"00",'0',           -- dsrc,..,dtmp

    "00",'0',"000000000","00",'0',      -- abox

    "00","00","00",'0',"000",'0',       -- dbox

    "0000",'0',                         -- lbox

    "00",'0','0','0','0','0','0','0',   -- mbox

    '0',"000","000","00",'0'            -- rest

  );

  constant c_dpath_dsrc_src  : slbit := '0'; -- DSRC = R(SRC)

  constant c_dpath_dsrc_res  : slbit := '1'; -- DSRC = DRES

  constant c_dpath_ddst_dst  : slbit := '0'; -- DDST = R(DST)

  constant c_dpath_ddst_res  : slbit := '1'; -- DDST = DRES

  constant c_dpath_dtmp_dsrc  : slv2 := "00"; -- DTMP = DSRC

  constant c_dpath_dtmp_psw   : slv2 := "01"; -- DTMP = PSW

  constant c_dpath_dtmp_dres  : slv2 := "10"; -- DTMP = DRES

  constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE

  constant c_dpath_res_abox   : slv3 := "000"; -- D/CRES = ABOX

  constant c_dpath_res_dbox   : slv3 := "001"; -- D/CRES = DBOX

  constant c_dpath_res_lbox   : slv3 := "010"; -- D/CRES = LBOX

  constant c_dpath_res_mbox   : slv3 := "011"; -- D/CRES = MBOX

  constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT

  constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT

  constant c_dpath_res_ireg   : slv3 := "110"; -- D/CRES = IREG

  constant c_dpath_res_cpdin  : slv3 := "111"; -- D/CRES = CPDIN

  constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC

  constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST

  constant c_dpath_vmaddr_pc   : slv2 := "10"; -- VMADDR = PC

  constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP

  type dpath_stat_type is record        -- data path status

    ccout_z : slbit;                    -- current effective Z cc flag

    shc_tc : slbit;                     -- last shc cycle (shc==0)

    div_cr : slbit;                     -- division: reminder correction needed

    div_cq : slbit;                     -- division: quotient correction needed

    div_zero : slbit;                   -- division: divident or divisor zero

    div_ovfl : slbit;                   -- division: overflow

  end record dpath_stat_type;

  constant dpath_stat_init : dpath_stat_type := (others=>'0');

  type decode_stat_type is record       -- decode status

    is_dstmode0 : slbit;                -- dest. is register mode

    is_srcpc : slbit;                   -- source is pc

    is_srcpcmode1 : slbit;              -- source is pc and mode=1

    is_dstpc : slbit;                   -- dest. is pc

    is_dstw_reg : slbit;                -- dest. register to be written

    is_dstw_pc  : slbit;                -- pc register to be written

    is_rmwop : slbit;                   -- read-modify-write operation

    is_bytop : slbit;                   -- byte operation

    is_res : slbit;                     -- reserved operation code

    op_rtt : slbit;                     -- RTT instruction

    op_mov : slbit;                     -- MOV instruction

    trap_vec : slv3;                    -- trap vector addr bits 4:2

    force_srcsp : slbit;                -- force src register to be sp

    updt_dstadsrc : slbit;              -- update dsrc in dsta flow

    dbox_srcmod : slv2;                 -- dbox src port modifier

    dbox_dstmod : slv2;                 -- dbox dst port modifier

    dbox_cimod : slv2;                  -- dbox ci port modifier

    dbox_cc1op : slbit;                 -- dbox use cc modes (1 op instruction)

    dbox_ccmode : slv3;                 -- dbox cc port mode

    lbox_func : slv4;                   -- lbox function

    mbox_func : slv2;                   -- mbox function

    res_sel : slv3;                     -- result bus (cres/dres) select

    fork_op : slv4;                     -- op fork after idecode state

    fork_srcr : slv2;                   -- src-read fork after idecode state

    fork_dstr : slv2;                   -- dst-read fork after src read state

    fork_dsta : slv2;                   -- dst-addr fork after idecode state

    fork_opg : slv4;                    -- opg fork

    fork_opa : slv3;                    -- opa fork

    do_fork_op : slbit;                 -- execute fork_op

    do_fork_srcr : slbit;               -- execute fork_srcr

    do_fork_dstr : slbit;               -- execute fork_dstr

    do_fork_dsta : slbit;               -- execute fork_dsta

    do_fork_opg : slbit;                -- execute fork_opg

    do_pref_dec : slbit;                -- can do prefetch at decode phase

  end record decode_stat_type;

  constant decode_stat_init : decode_stat_type := (

    '0','0','0','0','0','0','0','0','0', -- is_

    '0','0',"000",'0','0',               -- op_, trap_, force_, updt_

    "00","00","00",'0',"000",            -- dbox_

    "0000","00","000",                   -- lbox_, mbox_, res_

    "0000","00","00","00","0000","000",  -- fork_

    '0','0','0','0','0',                 -- do_fork_

    '0'                                  -- do_pref_

  );

  constant c_fork_op_halt : slv4 := "0000";

  constant c_fork_op_wait : slv4 := "0001";

  constant c_fork_op_rtti : slv4 := "0010";

  constant c_fork_op_trap : slv4 := "0011";

  constant c_fork_op_reset: slv4 := "0100";

  constant c_fork_op_rts :  slv4 := "0101";

  constant c_fork_op_spl :  slv4 := "0110";

  constant c_fork_op_mcc :  slv4 := "0111";

  constant c_fork_op_br :   slv4 := "1000";

  constant c_fork_op_mark : slv4 := "1001";

  constant c_fork_op_sob :  slv4 := "1010";

  constant c_fork_op_mtp :  slv4 := "1011";

  constant c_fork_srcr_def : slv2:= "00";

  constant c_fork_srcr_inc : slv2:= "01";

  constant c_fork_srcr_dec : slv2:= "10";

  constant c_fork_srcr_ind : slv2:= "11";

  constant c_fork_dstr_def : slv2:= "00";

  constant c_fork_dstr_inc : slv2:= "01";

  constant c_fork_dstr_dec : slv2:= "10";

  constant c_fork_dstr_ind : slv2:= "11";

  constant c_fork_dsta_def : slv2:= "00";

  constant c_fork_dsta_inc : slv2:= "01";

  constant c_fork_dsta_dec : slv2:= "10";

  constant c_fork_dsta_ind : slv2:= "11";

  constant c_fork_opg_gen  : slv4 := "0000";

  constant c_fork_opg_wdef : slv4 := "0001";

  constant c_fork_opg_winc : slv4 := "0010";

  constant c_fork_opg_wdec : slv4 := "0011";

  constant c_fork_opg_wind : slv4 := "0100";

  constant c_fork_opg_mul  : slv4 := "0101";

  constant c_fork_opg_div  : slv4 := "0110";

  constant c_fork_opg_ash  : slv4 := "0111";

  constant c_fork_opg_ashc : slv4 := "1000";

  constant c_fork_opa_jsr :     slv3 := "000";

  constant c_fork_opa_jmp :     slv3 := "001";

  constant c_fork_opa_mtp :     slv3 := "010";

  constant c_fork_opa_mfp_reg : slv3 := "011";

  constant c_fork_opa_mfp_mem : slv3 := "100";

  -- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors

  constant c_cpurust_init   : slv4 := "0000";  -- cpu in init state

  constant c_cpurust_halt   : slv4 := "0001";  -- cpu executed HALT

  constant c_cpurust_reset  : slv4 := "0010";  -- cpu was reset    

  constant c_cpurust_stop   : slv4 := "0011";  -- cpu was stopped

  constant c_cpurust_step   : slv4 := "0100";  -- cpu was stepped

  constant c_cpurust_susp   : slv4 := "0101";  -- cpu was suspended

  constant c_cpurust_runs   : slv4 := "0111";  -- cpu running

  constant c_cpurust_vecfet : slv4 := "1000";  -- vector fetch error halt

  constant c_cpurust_recrsv : slv4 := "1001";  -- recursive red-stack halt

  constant c_cpurust_sfail  : slv4 := "1100";  -- sequencer failure

  constant c_cpurust_vfail  : slv4 := "1101";  -- vmbox failure

  type cpustat_type is record           -- CPU status

    cmdbusy : slbit;                    -- command busy

    cmdack  : slbit;                    -- command acknowledge

    cmderr  : slbit;                    -- command error

    cmdmerr : slbit;                    -- command memory access error

    cpugo   : slbit;                    -- CPU go state

    cpustep : slbit;                    -- CPU step flag

    cpuhalt : slbit;                    -- CPU halt flag

    cpuwait : slbit;                    -- CPU wait flag

    cpurust : slv4;                     -- CPU run status

    cpfunc  : slv5;                     -- current control port function

    cprnum  : slv3;                     -- current control port register number

    waitsusp : slbit;                   -- WAIT instruction suspended

    intvect  : slv9_2;                  -- current interrupt vector

    trap_mmu : slbit;                   -- mmu trace trap pending

    trap_ysv : slbit;                   -- ysv trap pending

    prefdone : slbit;                   -- prefetch done

    do_gprwe : slbit;                   -- pending gpr_we

    do_intrsv : slbit;                  -- active rsv interrupt sequence

  end record cpustat_type;

  constant cpustat_init : cpustat_type := (

    '0','0','0','0',                    -- cmd..

    '0','0','0','0',                    -- cpu..

    c_cpurust_init,                     -- cpurust

    "00000","000",                      -- cpfunc, cprnum

    '0',                                -- waitsusp

    (others=>'0'),                      -- intvect 

    '0','0','0',                        -- trap_(mmu|ysv), prefdone

    '0','0'                             -- do_gprwe, do_intrsv

  );

  type cpuerr_type is record            -- CPU error register

    illhlt : slbit;                     -- illegal halt (in non-kernel mode)

    adderr : slbit;                     -- address error (odd, jmp/jsr reg)

    nxm : slbit;                        -- non-existent memory

    iobto : slbit;                      -- I/O bus timeout (non-exist UB)

    ysv : slbit;                        -- yellow stack violation

    rsv : slbit;                        -- red stack violation

  end record cpuerr_type;

  constant cpuerr_init : cpuerr_type := (others=>'0');

  type vm_cntl_type is record           -- virt memory control port

    req : slbit;                        -- request

    wacc : slbit;                       -- write access

    macc : slbit;                       -- modify access (r-m-w sequence)

    cacc : slbit;                       -- console access

    bytop : slbit;                      -- byte operation

    dspace : slbit;                     -- dspace operation

    kstack : slbit;                     -- access through kernel stack

    intrsv : slbit;                     -- active rsv interrupt sequence

    mode : slv2;                        -- mode

    trap_done : slbit;                  -- mmu trap taken (to set ssr0 bit)

  end record vm_cntl_type;

  constant vm_cntl_init : vm_cntl_type := (

    '0','0','0','0',                    -- req, wacc, macc,cacc

    '0','0','0',                        -- bytop, dspace, kstack

    '0',"00",'0'                        -- intrsv, mode, trap_done

  );

  type vm_stat_type is record           -- virt memory status port

    ack : slbit;                        -- acknowledge

    err : slbit;                        -- error (see err_xxx for reason)

    fail : slbit;                       -- failure (machine check)

    err_odd : slbit;                    -- abort: odd address error

    err_mmu : slbit;                    -- abort: mmu reject

    err_nxm : slbit;                    -- abort: non-existing memory

    err_iobto : slbit;                  -- abort: non-existing I/O resource

    err_rsv : slbit;                    -- abort: red stack violation

    trap_ysv : slbit;                   -- trap: yellow stack violation

    trap_mmu : slbit;                   -- trap: mmu trace trap

  end record vm_stat_type;

  constant vm_stat_init : vm_stat_type := (others=>'0');

  type em_mreq_type is record           -- external memory - master request

    req : slbit;                        -- request

    we : slbit;                         -- write enable

    be : slv2;                          -- byte enables

    cancel : slbit;                     -- cancel request

    addr : slv22_1;                     -- address

    din : slv16;                        -- data in (input to memory)

  end record em_mreq_type;

  constant em_mreq_init : em_mreq_type := (

    '0','0',"00",'0',                   -- req, we, be, cancel

    (others=>'0'),(others=>'0')         -- addr, din

  );

  type em_sres_type is record           -- external memory - slave response

    ack_r  : slbit;                     -- acknowledge read

    ack_w  : slbit;                     -- acknowledge write

    dout : slv16;                       -- data out (output from memory)

  end record em_sres_type;

  constant em_sres_init : em_sres_type := (

    '0','0',                            -- ack_r, ack_w

    (others=>'0')                       -- dout

  );

  type mmu_cntl_type is record          -- mmu control port

    req : slbit;                        -- translate request

    wacc : slbit;                       -- write access

    macc : slbit;                       -- modify access (r-m-w sequence)

    cacc : slbit;                       -- console access (bypass mmu)

    dspace : slbit;                     -- dspace access

    mode : slv2;                        -- processor mode

    trap_done : slbit;                  -- mmu trap taken (set ssr0 bit)

  end record mmu_cntl_type;

  constant mmu_cntl_init : mmu_cntl_type := (

    '0','0','0','0',                    -- req, wacc, macc, cacc

    '0',"00",'0'                        -- dspace, mode, trap_done

  );

  type mmu_stat_type is record          -- mmu status port

    vaok : slbit;                       -- virtual address valid

    trap : slbit;                       -- mmu trap request

    ena_mmu : slbit;                    -- mmu enable (ssr0 bit 0)

    ena_22bit : slbit;                  -- mmu in 22 bit mode (ssr3 bit 4)

    ena_ubmap : slbit;                  -- ubmap enable (ssr3 bit 5)

  end record mmu_stat_type;

  constant mmu_stat_init : mmu_stat_type := (others=>'0');

  type mmu_moni_type is record          -- mmu monitor port

    istart : slbit;                     -- instruction start

    idone : slbit;                      -- instruction done

    pc : slv16;                         -- PC of new instruction

    regmod : slbit;                     -- register modified

    regnum : slv3;                      -- register number

    delta : slv4;                       -- register offset

    isdec : slbit;                      -- offset to be subtracted

    trace_prev : slbit;                 -- use ssr12 trace state of prev. state

  end record mmu_moni_type;

  constant mmu_moni_init : mmu_moni_type := (

    '0','0',(others=>'0'),              -- istart, idone, pc

    '0',"000","0000",                   -- regmod, regnum, delta

    '0','0'                             -- isdec, trace_prev

  );

  type mmu_ssr0_type is record          -- MMU ssr0

    abo_nonres : slbit;                 -- abort non resident

    abo_length : slbit;                 -- abort segment length

    abo_rdonly : slbit;                 -- abort read-only

    trap_mmu : slbit;                   -- trap management

    ena_trap : slbit;                   -- enable traps

    inst_compl : slbit;                 -- instruction complete

    seg_mode : slv2;                    -- segement mode

    dspace : slbit;                     -- address space (D=1, I=0)

    seg_num : slv3;                     -- segment number

    ena_mmu : slbit;                    -- enable memory management

    trace_prev : slbit;                 -- ssr12 trace status in prev. state

  end record mmu_ssr0_type;

  constant mmu_ssr0_init : mmu_ssr0_type := (

    inst_compl=>'0', seg_mode=>"00", seg_num=>"000",

    others=>'0'

  );

  type mmu_ssr1_type is record          -- MMU ssr1

    rb_delta : slv5;                    -- RB: amount change

    rb_num : slv3;                      -- RB: register number

    ra_delta : slv5;                    -- RA: amount change

    ra_num : slv3;                      -- RA: register number

  end record mmu_ssr1_type;

  constant mmu_ssr1_init : mmu_ssr1_type := (

    "00000","000",                      -- rb_...

    "00000","000"                       -- ra_...

  );

  type mmu_ssr3_type is record          -- MMU ssr3

    ena_ubmap : slbit;                  -- enable unibus mapping

    ena_22bit : slbit;                  -- enable 22 bit mapping

    dspace_km : slbit;                  -- enable dspace kernel

    dspace_sm : slbit;                  -- enable dspace supervisor

    dspace_um : slbit;                  -- enable dspace user

  end record mmu_ssr3_type;

  constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');

-- control port definitions --------------------------------------------------

  type cp_cntl_type is record           -- control port control

    req : slbit;                        -- request

    func : slv5;                        -- function

    rnum : slv3;                        -- register number

  end record cp_cntl_type;

  constant c_cpfunc_noop : slv5 := "00000";  -- noop : no operation

  constant c_cpfunc_sta  : slv5 := "00001";  -- sta  : cpu start

  constant c_cpfunc_sto  : slv5 := "00010";  -- sto  : cpu stop 

  constant c_cpfunc_cont : slv5 := "00011";  -- cont : cpu continue

  constant c_cpfunc_step : slv5 := "00100";  -- step : cpu step 

  constant c_cpfunc_rst  : slv5 := "01111";  -- rst  : cpu reset (soft)

  constant c_cpfunc_rreg : slv5 := "10000";  -- rreg : read register

  constant c_cpfunc_wreg : slv5 := "10001";  -- wreg : write register

  constant c_cpfunc_rpsw : slv5 := "10010";  -- rpsw : read psw

  constant c_cpfunc_wpsw : slv5 := "10011";  -- wpsw : write psw

  constant c_cpfunc_rmem : slv5 := "10100";  -- rmem : read memory

  constant c_cpfunc_wmem : slv5 := "10101";  -- wmem : write memory

  constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");

  type cp_stat_type is record           -- control port status

    cmdbusy : slbit;                    -- command busy

    cmdack : slbit;                     -- command acknowledge

    cmderr : slbit;                     -- command error

    cmdmerr : slbit;                    -- command memory access error

    cpugo : slbit;                      -- CPU go state

    cpustep : slbit;                    -- CPU step flag

    cpuhalt : slbit;                    -- CPU halt flag

    cpuwait : slbit;                    -- CPU wait flag

    cpurust : slv4;                     -- CPU run status

  end record cp_stat_type;

  constant cp_stat_init : cp_stat_type := (

    '0','0','0','0',                    -- cmd...

    '0','0','0','0',                    -- cpu...

    (others=>'0')                       -- cpurust

  );

  type cp_addr_type is record           -- control port address

    addr : slv22_1;                     -- address

    racc : slbit;                       -- ibr access

    be : slv2;                          -- byte enables

    ena_22bit : slbit;                  -- enable 22 bit mode

    ena_ubmap : slbit;                  -- enable unibus mapper

  end record cp_addr_type;

  constant cp_addr_init : cp_addr_type := (

    (others=>'0'),                      -- addr

    '0',"00",                           -- racc, be

    '0','0'                             -- ena_...

  );

-- debug and monitoring port definitions -------------------------------------

  type dm_cntl_type is record           -- debug and monitor control

    dum1 : slbit;                       -- dummy 1

    dum2 : slbit;                       -- dummy 2

  end record dm_cntl_type;

  constant dm_cntl_init : dm_cntl_type := (others=>'0');

  type dm_stat_dp_type is record        -- debug and monitor status - dpath

    pc : slv16;                         -- pc

    psw : psw_type;                     -- psw

    ireg : slv16;                       -- ireg

    ireg_we : slbit;                    -- ireg we

    dsrc : slv16;                       -- dsrc register

    ddst : slv16;                       -- ddst register

    dtmp : slv16;                       -- dtmp register

    dres : slv16;                       -- dres bus

    gpr_adst : slv3;                    -- gpr dst regsiter

    gpr_mode : slv2;                    -- gpr mode

    gpr_bytop : slbit;                  -- gpr bytop

    gpr_we : slbit;                     -- gpr we

  end record dm_stat_dp_type;

  constant dm_stat_dp_init : dm_stat_dp_type := (

    (others=>'0'),                      -- pc

    psw_init,                           -- psw

    (others=>'0'),'0',                  -- ireg, ireg_we

    (others=>'0'),(others=>'0'),        -- dsrc, ddst

    (others=>'0'),(others=>'0'),        -- dtmp, dres

    (others=>'0'),(others=>'0'),        -- gpr_adst, gpr_mode

    '0','0'                             -- gpr_bytop, gpr_we

  );

  type dm_stat_vm_type is record        -- debug and monitor status - vmbox

    ibmreq : ib_mreq_type;              -- ibus master request

    ibsres : ib_sres_type;              -- ibus slave response

  end record dm_stat_vm_type;

  constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);

  type dm_stat_co_type is record        -- debug and monitor status - core

    cpugo : slbit;                      -- cpugo state flag

    cpuhalt : slbit;                    -- cpuhalt state flag

  end record dm_stat_co_type;

  constant dm_stat_co_init : dm_stat_co_type := ('0','0');

  type dm_stat_sy_type is record        -- debug and monitor status - system

    emmreq : em_mreq_type;              -- external memory: request

    emsres : em_sres_type;              -- external memory: response

    chit : slbit;                       -- cache hit

  end record dm_stat_sy_type;

  constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0');

-- rbus interface definitions ------------------------------------------------

  constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg

  constant c_rbaddr_cntl : slv5 := "00001"; -- -/F  control reg

  constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg

  constant c_rbaddr_psw  : slv5 := "00011"; -- R/W psw access

  constant c_rbaddr_al   : slv5 := "00100"; -- R/W address low reg

  constant c_rbaddr_ah   : slv5 := "00101"; -- R/W address high reg

  constant c_rbaddr_mem  : slv5 := "00110"; -- R/W memory access

  constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr

  constant c_rbaddr_r0   : slv5 := "01000"; -- R/W gpr 0

  constant c_rbaddr_r1   : slv5 := "01001"; -- R/W gpr 1

  constant c_rbaddr_r2   : slv5 := "01010"; -- R/W gpr 2

  constant c_rbaddr_r3   : slv5 := "01011"; -- R/W gpr 3

  constant c_rbaddr_r4   : slv5 := "01100"; -- R/W gpr 4

  constant c_rbaddr_r5   : slv5 := "01101"; -- R/W gpr 5

  constant c_rbaddr_sp   : slv5 := "01110"; -- R/W gpr 6 (sp)

  constant c_rbaddr_pc   : slv5 := "01111"; -- R/W gpr 7 (pc)

  constant c_rbaddr_ibrb : slv5 := "10000"; -- R/W ibr base address

  subtype  c_al_rbf_addr       is integer range 15 downto 1;  -- al: address

  constant c_ah_rbf_ena_ubmap: integer :=  7;                 -- ah: ubmap

  constant c_ah_rbf_ena_22bit: integer :=  6;                 -- ah: 22bit

  subtype  c_ah_rbf_addr       is integer range  5 downto 0;  -- ah: address

  constant c_stat_rbf_cmderr:   integer := 0;  -- stat field: cmderr