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-- $Id: pdp11_core.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_core - syn
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-- Description: pdp11: full processor core
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--
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-- Dependencies: pdp11_vmbox
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-- pdp11_dpath
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-- pdp11_decode
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-- pdp11_sequencer
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-- pdp11_irq
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-- pdp11_sys70
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-- ibus/ib_sres_or_4
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--
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-- Test bench: tb/tb_pdp11_core
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-- tb/tb_rritba_pdp11core
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-- tb/tb_rripdp_pdp11core
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-- tb/tb_rriext_pdp11core
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--
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox
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-- CP_ADDR now from in port; dpath CP_DIN now from in
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-- port; out port CP_DOUT now from _dpath
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-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
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-- 2008-08-22 161 1.2.4 rename pdp11_ibres_ -> ib_sres_
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-- 2008-04-25 138 1.2.3 BRESET: add for _vmbox, use for _irq
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-- 2008-04-19 137 1.2.2 add DM_STAT_(DP|VM|CO) port; added pdp11_sys70
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-- 2008-03-02 121 1.2.1 remove snoopers
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-- 2008-02-17 117 1.2 add em_(mreq|sres) interface for memory
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-- 2008-01-20 112 1.1.3 add BRESET port (intbus reset), rename P->BRESET
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-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
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-- 2008-01-01 109 1.1.1 _vmbox w/ IB_SRES_(CPU|EXT)
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-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
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-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
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-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_core is -- full processor core
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CP_CNTL : in cp_cntl_type; -- console control port
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CP_ADDR : in cp_addr_type; -- console address port
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CP_DIN : in slv16; -- console data in
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CP_STAT : out cp_stat_type; -- console status port
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CP_DOUT : out slv16; -- console data out
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EI_PRI : in slv3; -- external interrupt priority
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EI_VECT : in slv9_2; -- external interrupt vector
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EI_ACKM : out slbit; -- external interrupt acknowledge
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EM_MREQ : out em_mreq_type; -- external memory: request
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EM_SRES : in em_sres_type; -- external memory: response
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BRESET : out slbit; -- ibus reset
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IB_MREQ_M : out ib_mreq_type; -- inbus master request (master)
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IB_SRES_M : in ib_sres_type; -- inbus slave response (master)
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DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
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DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
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DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
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);
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end pdp11_core;
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architecture syn of pdp11_core is
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signal GRESET : slbit := '0';
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signal CRESET : slbit := '0';
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signal BRESET_L : slbit := '0';
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signal SEQ_CRESET : slbit := '0';
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signal SEQ_BRESET : slbit := '0';
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signal VM_CNTL : vm_cntl_type := vm_cntl_init;
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signal VM_STAT : vm_stat_type := vm_stat_init;
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signal MMU_MONI : mmu_moni_type := mmu_moni_init;
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signal DP_CNTL : dpath_cntl_type := dpath_cntl_init;
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signal DP_STAT : dpath_stat_type := dpath_stat_init;
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signal DP_PSW : psw_type := psw_init;
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signal DP_PC : slv16 := (others=>'0');
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signal DP_IREG : slv16 := (others=>'0');
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signal VM_DIN : slv16 := (others=>'0');
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signal VM_ADDR : slv16 := (others=>'0');
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signal VM_DOUT : slv16 := (others=>'0');
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signal ID_STAT : decode_stat_type := decode_stat_init;
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signal INT_PRI : slv3 := (others=>'0');
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signal INT_VECT : slv9_2 := (others=>'0');
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signal CP_STAT_L : cp_stat_type := cp_stat_init;
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signal INT_ACK : slbit := '0';
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signal IB_SRES_DP : ib_sres_type := ib_sres_init;
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signal IB_SRES_SEQ : ib_sres_type := ib_sres_init;
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signal IB_SRES_IRQ : ib_sres_type := ib_sres_init;
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signal IB_SRES_SYS : ib_sres_type := ib_sres_init;
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signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
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signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
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begin
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GRESET <= RESET;
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CRESET <= RESET or SEQ_CRESET;
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BRESET_L <= RESET or SEQ_CRESET or SEQ_BRESET;
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VMBOX : pdp11_vmbox
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port map (
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CLK => CLK,
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GRESET => GRESET,
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CRESET => CRESET,
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BRESET => BRESET_L,
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CP_ADDR => CP_ADDR,
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VM_CNTL => VM_CNTL,
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VM_ADDR => VM_ADDR,
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VM_DIN => VM_DIN,
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VM_STAT => VM_STAT,
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VM_DOUT => VM_DOUT,
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EM_MREQ => EM_MREQ,
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EM_SRES => EM_SRES,
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MMU_MONI => MMU_MONI,
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IB_MREQ_M => IB_MREQ,
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IB_SRES_CPU => IB_SRES,
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IB_SRES_EXT => IB_SRES_M,
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DM_STAT_VM => DM_STAT_VM
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);
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DPATH : pdp11_dpath
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port map (
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CLK => CLK,
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CRESET => CRESET,
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CNTL => DP_CNTL,
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STAT => DP_STAT,
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CP_DIN => CP_DIN,
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CP_DOUT => CP_DOUT,
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PSWOUT => DP_PSW,
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PCOUT => DP_PC,
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IREG => DP_IREG,
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VM_ADDR => VM_ADDR,
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VM_DOUT => VM_DOUT,
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VM_DIN => VM_DIN,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_DP,
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DM_STAT_DP => DM_STAT_DP
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);
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IDEC : pdp11_decode
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port map (
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IREG => DP_IREG,
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STAT => ID_STAT
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);
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SEQ : pdp11_sequencer
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port map (
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CLK => CLK,
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GRESET => GRESET,
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PSW => DP_PSW,
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PC => DP_PC,
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IREG => DP_IREG,
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ID_STAT => ID_STAT,
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DP_STAT => DP_STAT,
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CP_CNTL => CP_CNTL,
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VM_STAT => VM_STAT,
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INT_PRI => INT_PRI,
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INT_VECT => INT_VECT,
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CRESET => SEQ_CRESET,
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BRESET => SEQ_BRESET,
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MMU_MONI => MMU_MONI,
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DP_CNTL => DP_CNTL,
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VM_CNTL => VM_CNTL,
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CP_STAT => CP_STAT_L,
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INT_ACK => INT_ACK,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_SEQ
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);
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IRQ : pdp11_irq
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port map (
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CLK => CLK,
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BRESET => BRESET_L,
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INT_ACK => INT_ACK,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT,
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EI_ACKM => EI_ACKM,
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PRI => INT_PRI,
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VECT => INT_VECT,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_IRQ
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);
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SYS70 : pdp11_sys70
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port map (
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CLK => CLK,
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CRESET => CRESET,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_SYS
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);
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IB_SRES_OR : ib_sres_or_4
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port map (
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IB_SRES_1 => IB_SRES_DP,
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IB_SRES_2 => IB_SRES_SEQ,
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IB_SRES_3 => IB_SRES_IRQ,
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IB_SRES_4 => IB_SRES_SYS,
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IB_SRES_OR => IB_SRES
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);
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IB_MREQ_M <= IB_MREQ;
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CP_STAT <= CP_STAT_L;
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BRESET <= BRESET_L;
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DM_STAT_CO.cpugo <= CP_STAT_L.cpugo;
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DM_STAT_CO.cpuhalt <= CP_STAT_L.cpuhalt;
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end syn;
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