1 |
2 |
wfjm |
-- $Id: pdp11_dbox.vhd 314 2010-07-09 17:38:41Z mueller $
|
2 |
|
|
--
|
3 |
|
|
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Module Name: pdp11_dbox - syn
|
16 |
|
|
-- Description: pdp11: arithmetic unit for data (dbox)
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: -
|
19 |
|
|
-- Test bench: tb/tb_pdp11_core (implicit)
|
20 |
|
|
-- Target Devices: generic
|
21 |
|
|
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
22 |
|
|
-- Revision History:
|
23 |
|
|
-- Date Rev Version Comment
|
24 |
|
|
-- 2007-06-14 56 1.0.1 Use slvtypes.all
|
25 |
|
|
-- 2007-05-12 26 1.0 Initial version
|
26 |
|
|
------------------------------------------------------------------------------
|
27 |
|
|
|
28 |
|
|
library ieee;
|
29 |
|
|
use ieee.std_logic_1164.all;
|
30 |
|
|
use ieee.std_logic_arith.all;
|
31 |
|
|
use ieee.std_logic_unsigned.all;
|
32 |
|
|
|
33 |
|
|
use work.slvtypes.all;
|
34 |
|
|
use work.pdp11.all;
|
35 |
|
|
|
36 |
|
|
-- ----------------------------------------------------------------------------
|
37 |
|
|
|
38 |
|
|
-- arithmetic unit for data, usage:
|
39 |
|
|
-- ADD: SRC + DST + 0 (dst+src)
|
40 |
|
|
-- SUB: ~SRC + DST + 1 (dst-src)
|
41 |
|
|
-- ADC: 0 + DST + CI (dst+ci)
|
42 |
|
|
-- SBC: ~0 + DST + ~CI (dst-ci)
|
43 |
|
|
-- CMP: SRC + ~DST + 1 (src-dst)
|
44 |
|
|
-- COM: 0 + ~DST + 0 (~dst)
|
45 |
|
|
-- NEG: 0 + ~DST + 1 (-dst)
|
46 |
|
|
-- INC: 0 + DST + 1 (dst+1)
|
47 |
|
|
-- DEC: ~0 + DST + 0 (dst-1)
|
48 |
|
|
-- CLR: 0 + 0 + 0 (0)
|
49 |
|
|
-- SOB: SRC + ~0 + 0 (src-1)
|
50 |
|
|
|
51 |
|
|
entity pdp11_dbox is -- arithmetic unit for data (dbox)
|
52 |
|
|
port (
|
53 |
|
|
DSRC : in slv16; -- 'src' data in
|
54 |
|
|
DDST : in slv16; -- 'dst' data in
|
55 |
|
|
CI : in slbit; -- carry flag in
|
56 |
|
|
SRCMOD : in slv2; -- src modifier mode
|
57 |
|
|
DSTMOD : in slv2; -- dst modifier mode
|
58 |
|
|
CIMOD : in slv2; -- ci modifier mode
|
59 |
|
|
CC1OP : in slbit; -- use cc modes (1 op instruction)
|
60 |
|
|
CCMODE : in slv3; -- cc mode
|
61 |
|
|
BYTOP : in slbit; -- byte operation
|
62 |
|
|
DOUT : out slv16; -- data output
|
63 |
|
|
CCOUT : out slv4 -- condition codes out
|
64 |
|
|
);
|
65 |
|
|
end pdp11_dbox;
|
66 |
|
|
|
67 |
|
|
architecture syn of pdp11_dbox is
|
68 |
|
|
|
69 |
|
|
-- --------------------------------------
|
70 |
|
|
|
71 |
|
|
begin
|
72 |
|
|
|
73 |
|
|
process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
|
74 |
|
|
|
75 |
|
|
variable msrc : slv16 := (others=>'0'); -- effective src data
|
76 |
|
|
variable mdst : slv16 := (others=>'0'); -- effective dst data
|
77 |
|
|
variable mci : slbit := '0'; -- effective ci
|
78 |
|
|
variable sum : slv16 := (others=>'0'); -- sum
|
79 |
|
|
variable co8 : slbit := '0'; -- co 8 bit
|
80 |
|
|
variable co16 : slbit := '0'; -- co 16 bit
|
81 |
|
|
|
82 |
|
|
variable nno : slbit := '0'; -- local no
|
83 |
|
|
variable nzo : slbit := '0'; -- local zo
|
84 |
|
|
variable nvo : slbit := '0'; -- local vo
|
85 |
|
|
variable nco : slbit := '0'; -- local co
|
86 |
|
|
|
87 |
|
|
variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
|
88 |
|
|
variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
|
89 |
|
|
variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
|
90 |
|
|
|
91 |
|
|
alias NO : slbit is CCOUT(3);
|
92 |
|
|
alias ZO : slbit is CCOUT(2);
|
93 |
|
|
alias VO : slbit is CCOUT(1);
|
94 |
|
|
alias CO : slbit is CCOUT(0);
|
95 |
|
|
|
96 |
|
|
-- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
|
97 |
|
|
-- implemented following the recommended pattern for XST ISE V8.1
|
98 |
|
|
|
99 |
|
|
procedure do_add8_ci_co (
|
100 |
|
|
variable a : in slv8; -- input a
|
101 |
|
|
variable b : in slv8; -- input b
|
102 |
|
|
variable ci : in slbit; -- carry in
|
103 |
|
|
variable sum : out slv8; -- sum out
|
104 |
|
|
variable co : out slbit -- carry out
|
105 |
|
|
) is
|
106 |
|
|
|
107 |
|
|
variable tmp: slv9;
|
108 |
|
|
|
109 |
|
|
begin
|
110 |
|
|
|
111 |
|
|
tmp := conv_std_logic_vector((conv_integer(a) + conv_integer(b) +
|
112 |
|
|
conv_integer(ci)),9);
|
113 |
|
|
sum := tmp(7 downto 0);
|
114 |
|
|
co := tmp(8);
|
115 |
|
|
|
116 |
|
|
end procedure do_add8_ci_co;
|
117 |
|
|
|
118 |
|
|
begin
|
119 |
|
|
|
120 |
|
|
case SRCMOD is
|
121 |
|
|
when c_dbox_mod_pass => msrc := DSRC;
|
122 |
|
|
when c_dbox_mod_inv => msrc := not DSRC;
|
123 |
|
|
when c_dbox_mod_zero => msrc := (others=>'0');
|
124 |
|
|
when c_dbox_mod_one => msrc := (others=>'1');
|
125 |
|
|
when others => null;
|
126 |
|
|
end case;
|
127 |
|
|
|
128 |
|
|
case DSTMOD is
|
129 |
|
|
when c_dbox_mod_pass => mdst := DDST;
|
130 |
|
|
when c_dbox_mod_inv => mdst := not DDST;
|
131 |
|
|
when c_dbox_mod_zero => mdst := (others=>'0');
|
132 |
|
|
when c_dbox_mod_one => mdst := (others=>'1');
|
133 |
|
|
when others => null;
|
134 |
|
|
end case;
|
135 |
|
|
|
136 |
|
|
case CIMOD is
|
137 |
|
|
when c_dbox_mod_pass => mci := CI;
|
138 |
|
|
when c_dbox_mod_inv => mci := not CI;
|
139 |
|
|
when c_dbox_mod_zero => mci := '0';
|
140 |
|
|
when c_dbox_mod_one => mci := '1';
|
141 |
|
|
when others => null;
|
142 |
|
|
end case;
|
143 |
|
|
|
144 |
|
|
do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
|
145 |
|
|
sum(7 downto 0), co8);
|
146 |
|
|
do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
|
147 |
|
|
sum(15 downto 8), co16);
|
148 |
|
|
|
149 |
|
|
DOUT <= sum;
|
150 |
|
|
|
151 |
|
|
-- V ('overflow) bit set if
|
152 |
|
|
-- ADD : both operants of same sign but has result opposite sign
|
153 |
|
|
-- SUB : both operants of opposide sign and sign source equals sign result
|
154 |
|
|
-- CMP : both operants of opposide sign and sign dest. equals sign result
|
155 |
|
|
|
156 |
|
|
nno := '0';
|
157 |
|
|
nzo := '0';
|
158 |
|
|
nvo := '0';
|
159 |
|
|
nco := '0';
|
160 |
|
|
|
161 |
|
|
if BYTOP = '1' then
|
162 |
|
|
nno := sum(7);
|
163 |
|
|
if unsigned(sum(7 downto 0)) = 0 then
|
164 |
|
|
nzo := '1';
|
165 |
|
|
else
|
166 |
|
|
nzo := '0';
|
167 |
|
|
end if;
|
168 |
|
|
nco := co8;
|
169 |
|
|
|
170 |
|
|
src_msb := DSRC(7);
|
171 |
|
|
dst_msb := DDST(7);
|
172 |
|
|
sum_msb := sum(7);
|
173 |
|
|
|
174 |
|
|
else
|
175 |
|
|
nno := sum(15);
|
176 |
|
|
if unsigned(sum) = 0 then
|
177 |
|
|
nzo := '1';
|
178 |
|
|
else
|
179 |
|
|
nzo := '0';
|
180 |
|
|
end if;
|
181 |
|
|
nco := co16;
|
182 |
|
|
|
183 |
|
|
src_msb := DSRC(15);
|
184 |
|
|
dst_msb := DDST(15);
|
185 |
|
|
sum_msb := sum(15);
|
186 |
|
|
end if;
|
187 |
|
|
|
188 |
|
|
-- the logic for 2 operand V+C is ugly. It is reverse engineered from
|
189 |
|
|
-- the MOD's the operation type.
|
190 |
|
|
|
191 |
|
|
if CC1OP = '0' then -- 2 operand cases
|
192 |
|
|
if unsigned(CIMOD) = unsigned(c_dbox_mod_zero) then -- case ADD
|
193 |
|
|
nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
|
194 |
|
|
else
|
195 |
|
|
if unsigned(SRCMOD) = unsigned(c_dbox_mod_inv) then -- case SUB
|
196 |
|
|
nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
|
197 |
|
|
else -- case CMP
|
198 |
|
|
nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
|
199 |
|
|
end if;
|
200 |
|
|
nco := not nco; -- invert C for SUB and CMP
|
201 |
|
|
end if;
|
202 |
|
|
|
203 |
|
|
else -- 1 operand cases
|
204 |
|
|
case CCMODE is
|
205 |
|
|
when c_dbox_ccmode_clr|c_dbox_ccmode_tst =>
|
206 |
|
|
nvo := '0'; -- force v=0 for tst and clr
|
207 |
|
|
nco := '0'; -- force c=0 for tst and clr
|
208 |
|
|
|
209 |
|
|
when c_dbox_ccmode_com =>
|
210 |
|
|
nvo := '0'; -- force v=0 for com
|
211 |
|
|
nco := '1'; -- force c=1 for com
|
212 |
|
|
|
213 |
|
|
when c_dbox_ccmode_inc =>
|
214 |
|
|
nvo := sum_msb and not dst_msb;
|
215 |
|
|
nco := CI; -- C not affected for INC
|
216 |
|
|
|
217 |
|
|
when c_dbox_ccmode_dec =>
|
218 |
|
|
nvo := not sum_msb and dst_msb;
|
219 |
|
|
nco := CI; -- C not affected for DEC
|
220 |
|
|
|
221 |
|
|
when c_dbox_ccmode_neg =>
|
222 |
|
|
nvo := sum_msb and dst_msb;
|
223 |
|
|
nco := not nzo;
|
224 |
|
|
|
225 |
|
|
when c_dbox_ccmode_adc =>
|
226 |
|
|
nvo := sum_msb and not dst_msb;
|
227 |
|
|
|
228 |
|
|
when c_dbox_ccmode_sbc =>
|
229 |
|
|
nvo := not sum_msb and dst_msb;
|
230 |
|
|
nco := not nco;
|
231 |
|
|
|
232 |
|
|
when others => null;
|
233 |
|
|
end case;
|
234 |
|
|
end if;
|
235 |
|
|
|
236 |
|
|
NO <= nno;
|
237 |
|
|
ZO <= nzo;
|
238 |
|
|
VO <= nvo;
|
239 |
|
|
CO <= nco;
|
240 |
|
|
|
241 |
|
|
end process;
|
242 |
|
|
|
243 |
|
|
end syn;
|