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-- $Id: pdp11_irq.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_irq - syn
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-- Description: pdp11: interrupt requester
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2008-08-22 161 1.1.4 use iblib
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-- 2008-04-25 138 1.1.3 use BRESET to clear pirq
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-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
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-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
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-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_irq is -- interrupt requester
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port (
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CLK : in slbit; -- clock
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BRESET : in slbit; -- ibus reset
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INT_ACK : in slbit; -- interrupt acknowledge from CPU
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EI_PRI : in slv3; -- external interrupt priority
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EI_VECT : in slv9_2; -- external interrupt vector
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EI_ACKM : out slbit; -- external interrupt acknowledge
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PRI : out slv3; -- interrupt priority
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VECT : out slv9_2; -- interrupt vector
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type -- ibus response
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);
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end pdp11_irq;
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architecture syn of pdp11_irq is
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constant ibaddr_pirq : slv16 := conv_std_logic_vector(8#177772#,16);
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subtype pirq_ubf_pir is integer range 15 downto 9;
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subtype pirq_ubf_pia_h is integer range 7 downto 5;
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subtype pirq_ubf_pia_l is integer range 3 downto 1;
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signal IBSEL_PIRQ : slbit := '0';
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signal R_PIRQ : slv8_1 := (others => '0'); -- pirq register
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signal PI_PRI : slv3 := (others => '0'); -- prog.int. priority
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-- attribute PRIORITY_EXTRACT : string;
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-- attribute PRIORITY_EXTRACT of PI_PRI : signal is "force";
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begin
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proc_ibsel: process (IB_MREQ)
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variable ipirq : slbit := '0';
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begin
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ipirq := '0';
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if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_pirq(12 downto 1) then
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ipirq := '1';
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end if;
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IBSEL_PIRQ <= ipirq;
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IB_SRES.ack <= ipirq;
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IB_SRES.busy <= '0';
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end process proc_ibsel;
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proc_ibdout : process (IBSEL_PIRQ, R_PIRQ, PI_PRI)
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variable pirqout : slv16 := (others=>'0');
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begin
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pirqout := (others=>'0');
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if IBSEL_PIRQ = '1' then
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pirqout(pirq_ubf_pir) := R_PIRQ;
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pirqout(pirq_ubf_pia_h) := PI_PRI;
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pirqout(pirq_ubf_pia_l) := PI_PRI;
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end if;
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IB_SRES.dout <= pirqout;
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end process proc_ibdout;
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proc_pirq : process (CLK)
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begin
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if CLK'event and CLK='1' then
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if BRESET = '1' then
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R_PIRQ <= (others => '0');
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elsif IBSEL_PIRQ='1' and IB_MREQ.we='1'and IB_MREQ.be1='1' then
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R_PIRQ <= IB_MREQ.din(pirq_ubf_pir);
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end if;
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end if;
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end process proc_pirq;
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PI_PRI <= "111" when R_PIRQ(7)='1' else
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"110" when R_PIRQ(6)='1' else
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"101" when R_PIRQ(5)='1' else
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"100" when R_PIRQ(4)='1' else
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"011" when R_PIRQ(3)='1' else
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"010" when R_PIRQ(2)='1' else
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"001" when R_PIRQ(1)='1' else
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"000";
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proc_irq : process (PI_PRI, EI_PRI, EI_VECT, INT_ACK)
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begin
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EI_ACKM <= '0';
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if unsigned(EI_PRI) > unsigned(PI_PRI) then
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PRI <= EI_PRI;
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VECT <= EI_VECT;
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EI_ACKM <= INT_ACK;
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else
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PRI <= PI_PRI;
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VECT <= conv_std_logic_vector(8#240#,9)(8 downto 2);
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end if;
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end process proc_irq;
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end syn;
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