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-- $Id: tbd_pdp11_core.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tbd_pdp11_core - syn
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-- Description: Wrapper for pdp11_core to avoid records. It has a port
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-- interface which will not be modified by xst synthesis
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-- (no records, no generic port).
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--
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-- Dependencies: genlib/clkdivce
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-- pdp11_core
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-- pdp11_bram
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-- ibus/ibdr_minisys
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-- pdp11_tmu_sb [sim only]
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--
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-- To test: pdp11_core
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--
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-06-13 305 11.4 L68 xc3s1000-4 601 2504 206 1428 s 18.6
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-- 2008-03-01 120 8.2.03 I34 xc3s1000-4 679 2562 206 1465 s 18.5
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-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 605 2324 164 1297 s 18.7
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-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 536 2119 119 1184 s 19.3
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-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 INTERNAL_ERROR -> blog_webpack
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-- 2007-10-27 92 9.1 J30 xc3s1000-4 503 2021 119 - t 18.7
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-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 534 2091 119 1170 s 19.3
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-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 557 2186 119 - s 18.6
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-06-20 307 1.4.1 add CP_ADDR_racc, CP_ADDR_be port
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-- 2010-06-13 305 1.4 add CP_ADDR_... in ports; add CP_CNTL_rnum in port
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-- 2010-06-11 303 1.3.9 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-07-12 233 1.3.8 adapt to ibdr_minisys interface changes
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-- 2009-05-10 214 1.3.7 use pdp11_tmu_sb instead of pdp11_tmu
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-- 2008-08-22 161 1.3.6 use iblib, ibdlib
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-- 2008-05-03 143 1.3.5 rename _cpursta->_cpurust
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-- 2008-04-27 140 1.3.4 use cpursta interface, remove cpufail
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-- 2008-04-19 137 1.3.3 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
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-- 2008-04-18 136 1.3.2 add RESET for ibdr_minisys
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-- 2008-02-23 118 1.3.1 use sys_conf for bram size
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-- 2008-02-17 117 1.3 adapt to em_ core interface; use pdp11_bram
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-- 2008-01-20 112 1.2.1 rename clkgen->clkdivce; use ibdr_minisys, BRESET;
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-- 2008-01-06 111 1.2 add some external devices: KW11L, DL11, RK11
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-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
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-- 2007-09-23 85 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.genlib.all;
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use work.iblib.all;
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use work.ibdlib.all;
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use work.pdp11.all;
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use work.sys_conf.all;
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entity tbd_pdp11_core is -- full core [no records]
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CP_CNTL_req : in slbit; -- console control port
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CP_CNTL_func : in slv5; -- console control port
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CP_CNTL_rnum : in slv3; -- console control port
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CP_ADDR_addr : in slv22_1; -- console address port
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CP_ADDR_racc : in slbit; -- console address port
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CP_ADDR_be : in slv2; -- console address port
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CP_ADDR_ena_22bit : in slbit; -- console address port
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CP_ADDR_ena_ubmap : in slbit; -- console address port
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CP_DIN : in slv16; -- console data in
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CP_STAT_cmdbusy : out slbit; -- console status port
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CP_STAT_cmdack : out slbit; -- console status port
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CP_STAT_cmderr : out slbit; -- console status port
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CP_STAT_cmdmerr : out slbit; -- console status port
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CP_STAT_cpugo : out slbit; -- console status port
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CP_STAT_cpuhalt : out slbit; -- console status port
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CP_STAT_cpustep : out slbit; -- console status port
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CP_STAT_cpurust : out slv4; -- console status port
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CP_DOUT : out slv16 -- console data out
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);
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end tbd_pdp11_core;
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architecture syn of tbd_pdp11_core is
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signal CE_USEC : slbit := '0';
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signal EI_PRI : slv3 := (others=>'0');
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signal EI_VECT : slv9_2 := (others=>'0');
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signal EI_ACKM : slbit := '0';
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signal CP_CNTL : cp_cntl_type := cp_cntl_init;
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signal CP_ADDR : cp_addr_type := cp_addr_init;
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signal CP_STAT : cp_stat_type := cp_stat_init;
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signal EM_MREQ : em_mreq_type := em_mreq_init;
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signal EM_SRES : em_sres_type := em_sres_init;
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signal BRESET : slbit := '0';
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signal IB_MREQ_M : ib_mreq_type := ib_mreq_init;
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signal IB_SRES_M : ib_sres_type := ib_sres_init;
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signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
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signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
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signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
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signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
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begin
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CP_CNTL.req <= CP_CNTL_req;
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CP_CNTL.func <= CP_CNTL_func;
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CP_CNTL.rnum <= CP_CNTL_rnum;
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CP_ADDR.addr <= CP_ADDR_addr;
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CP_ADDR.racc <= CP_ADDR_racc;
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CP_ADDR.be <= CP_ADDR_be;
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CP_ADDR.ena_22bit <= CP_ADDR_ena_22bit;
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CP_ADDR.ena_ubmap <= CP_ADDR_ena_ubmap;
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CP_STAT_cmdbusy <= CP_STAT.cmdbusy;
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CP_STAT_cmdack <= CP_STAT.cmdack;
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CP_STAT_cmderr <= CP_STAT.cmderr;
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CP_STAT_cmdmerr <= CP_STAT.cmdmerr;
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CP_STAT_cpugo <= CP_STAT.cpugo;
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CP_STAT_cpuhalt <= CP_STAT.cpuhalt;
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CP_STAT_cpustep <= CP_STAT.cpustep;
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CP_STAT_cpurust <= CP_STAT.cpurust;
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CLKDIV : clkdivce
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generic map (
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CDUWIDTH => 6,
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USECDIV => 50,
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MSECDIV => 1000)
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port map (
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_MSEC => open
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);
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PDP11 : pdp11_core
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port map (
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CLK => CLK,
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RESET => RESET,
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CP_CNTL => CP_CNTL,
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CP_ADDR => CP_ADDR,
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CP_DIN => CP_DIN,
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CP_STAT => CP_STAT,
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CP_DOUT => CP_DOUT,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT,
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EI_ACKM => EI_ACKM,
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EM_MREQ => EM_MREQ,
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EM_SRES => EM_SRES,
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BRESET => BRESET,
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IB_MREQ_M => IB_MREQ_M,
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IB_SRES_M => IB_SRES_M,
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DM_STAT_DP => DM_STAT_DP,
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DM_STAT_VM => DM_STAT_VM,
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DM_STAT_CO => DM_STAT_CO
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);
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MEM : pdp11_bram
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generic map (
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AWIDTH => sys_conf_bram_awidth)
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port map (
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CLK => CLK,
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GRESET => RESET,
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EM_MREQ => EM_MREQ,
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EM_SRES => EM_SRES
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);
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IBDR_SYS : ibdr_minisys
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port map (
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
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RESET => RESET,
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BRESET => BRESET,
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RRI_LAM => open,
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IB_MREQ => IB_MREQ_M,
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IB_SRES => IB_SRES_M,
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EI_ACKM => EI_ACKM,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT,
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DISPREG => open
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);
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-- synthesis translate_off
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DM_STAT_SY.emmreq <= EM_MREQ;
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DM_STAT_SY.emsres <= EM_SRES;
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DM_STAT_SY.chit <= '0';
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TMU : pdp11_tmu_sb
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generic map (
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ENAPIN => 13)
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port map (
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CLK => CLK,
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DM_STAT_DP => DM_STAT_DP,
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DM_STAT_VM => DM_STAT_VM,
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DM_STAT_CO => DM_STAT_CO,
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DM_STAT_SY => DM_STAT_SY
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);
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-- synthesis translate_on
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end syn;
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