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# $Id: README.txt 351 2010-12-30 21:50:54Z mueller $
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Release notes for w11a
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  Table of content:
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  1. Documentation
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  2. Files
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  3. Change Log
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1. Documentation -------------------------------------------------------------
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  More detailed information on installation, build and test can be found
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  in the doc directory, specifically
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    * README.txt: release notes
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    * INSTALL.txt: installation and building test benches and systems
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    * w11a_tb_guide.txt: running test benches
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    * w11a_os_guide.txt: booting operating systems
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    * w11a_known_issues.txt: known differences, limitations and issues
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2. Files ---------------------------------------------------------------------
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   doc                          Documentation
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   rtl                          VHDL sources
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   rtl/bplib                    - board and component support libs
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   rtl/bplib/issi                 - for ISSI parts
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   rtl/bplib/micron               - for Micron parts
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   rtl/bplib/nexys2               - for Digilent Nexsy2 board
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   rtl/bplib/s3board              - for Digilent S3BOARD
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   rtl/ibus                     - ibus devices (UNIBUS peripherals)
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   rtl/sys_gen                  - top level designs
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   rtl/sys_gen/w11a               - top level designs for w11a SoC
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   rtl/sys_gen/w11a/nexys2          - w11a SoC for Digilent Nexsy2
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   rtl/sys_gen/w11a/s3board         - w11a SoC for Digilent S3BOARD
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   rtl/vlib                     - VHDL component libs
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   rtl/vlib/comlib                - communication
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   rtl/vlib/genlib                - general
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   rtl/vlib/memlib                - memory
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   rtl/vlib/rbus                  - rri: rbus
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   rtl/vlib/rlink                 - rri: rlink
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   rtl/vlib/serport               - serial port (UART)
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   rtl/vlib/simlib                - simulation helper lib
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   rtl/vlib/xlib                  - Xilinx specific components
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   rtl/w11a                     - w11a core
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   tools                        helper programs
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   tools/bin                    - scripts and binaries
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3. Change Log ----------------------------------------------------------------
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- trunk (2011-01-02: svn rev 9(oc) 352(wfjm); untagged w11a_V0.52) +++++++++
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  - Summary
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    - Introduced rbus protocol V3
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    - reorganize rbus and rlink modules, many renames
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  - Changes
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    - module renames:
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      - the rri (remote-register-interface) components were re-organized and
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        cleanly separated into rbus and rlink components:
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          rri/rb_sres_or_*              -> rbus/rb_sres_or_*
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          rri/rri_core                  -> rlink/rlink_core
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          rri/rri_base_serport          -> rlink/rlink_base_serport
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          rri/rrilib                    -> rbus/rblib
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                                        -> rlink/rlinklib
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          rri/rri_serport               -> rlink/rlink_serport
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          rri/tb/rritb_sres_or_mon      -> rbus/rb_sres_or_mon
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      - the rri test bench monitors were reorganized and renamed
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          rri/tb/rritb_cpmon            -> rlink/rlink_mon
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          rri/tb/rritb_cpmon_sb         -> rlink/rlink_mon_sb
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          rri/tb/rritb_rbmon            -> rbus/rb_mon
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          rri/tb/rritb_rbmon_sb         -> rbus/rb_mon_sb
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      - the rri low level test bench were also renamed
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          rri/tb/tb_rri                 -> rlink/tb/tb_rlink
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          rri/tb/tb_rri_core            -> rlink/tb/tb_rlink_direct
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          rri/tb/tb_rri_serport         -> rlink/tb/tb_rlink_serport
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      - the base modules for rlink+cext based test benches were renamed
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          rri/tb/rritb_core_cm          -> rlink/tb/tbcore_rlink_dcm
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          rri/tb/rritb_core             -> rlink/tb/tbcore_rlink
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          rri/tb/vhpi_rriext            -> rlink/tb/rlink_cext_vhpi
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          rri/tb/cext_rriext.c          -> rlink/tb/rlink_cext.c
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      - other rri/rbus related renames
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          bplib/s3board/s3_humanio_rri  -> s3_humanio_rbus
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          w11a/pdp11_core_rri           -> pdp11_core_rbus
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      - other renames
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          w11a/tb/tb_pdp11_core         -> tb_pdp11core
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    - signal renames:
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      - rlink interface (defined in rlink/rlinklib.vhd):
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        - rename rlink port signals:
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          CP_*  -> RL_*
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        - rename status bit names to better reflect their usage in v3:
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          ccrc  -> cerr   - indicates cmd crc error or other cmd level abort
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          dcrc  -> derr   - indicates data crc error or other data level abort
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          ioto  -> rbnak  - indicates rbus abort, either no ack or timeout
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          ioerr -> rberr  - indicates that rbus err flag was set
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    - migrate to rbus protocol verion 3
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      - in rb_mreq use now aval,re,we instead of req,we
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      - basic rbus transaction now takes 2 cycles, one for address select, one
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        for data exchange. Same concept and reasoning behind as in ibus V2.
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    - vlib/rlink/rlink_core
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      - cerr and derr state flags now set on command or data crc errors as well
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        as on eop/nak aborts when command or wblk data is received.
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      - has now 'monitor port', RL_MONI.
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      - RL_FLUSH port removed, the flush logic is now in rlink_serport
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    - restructured rlink modules
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      - rlink_core is the rlink protocol engine with a 9 bit wide interface
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      - rlink_rlb2rl (new) is an adapter to a byte wide interface
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      - rlink_base (new) combines rlink_core and rlink_rlb2rl
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      - rlink_serport (re-written) is an adapter to a serial interface
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      - rlink_base_serport (renamed) combines rlink_base and rlink_serport
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  - New features
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    - vlib/rbus
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      - added several rbus devices useful for debugging
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        - rbd_tester: test target, used for example in test benches
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- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) ++++++++
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  - Summary
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    - Introduced ibus protocol V2
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    - Nexys2 systems use DCM
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    - sys_w11a_n2 now runs with 58 MHz
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  - Changes
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    - module renames:
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      - in future 'box' is used for large autonomous blocks, therefore use
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        the term unit for purely sequential logic modules:
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          pdp11_abox -> pdp11_ounit
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          pdp11_dbox -> pdp11_aunit
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          pdp11_lbox -> pdp11_lunit
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          pdp11_mbox -> pdp11_munit
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    - signal renames:
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      - renamed RRI_LAM -> RB_LAM in all ibus devices
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      - renamed CLK     -> I_CLK50 in all top level nexys2 and s3board designs
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    - migrate to ibus protocol verion 2
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      - in ib_mreq use now aval,re,we,rmw instead of req,we,dip
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      - basic ibus transaction now takes 2 cycles, one for address select, one
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        for data exchange. This avoids too long logic paths in the ibus logic.
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  - New features
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    - ibus
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      - added ib_sres_or_mon to check for miss-behaving ibus devices
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      - added ib_sel to encapsulate address select logic
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    - nexys2 systems
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      - now DCM derived system clock supported
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      - sys_gen/w11a/nexys2
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        - sys_w11a_n2 now runs with 58 MHz clksys
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  - Bug fixes
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    - rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
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- w11a_V0.5 (2010-07-23) ++++++++++++++++++++++++++++++++++++++++++++++++++
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  Initial release with
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  - w11a CPU core
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  - basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
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  - just for fun: iist (not fully implemented and tested yet)
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  - two complete system configurations with
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    - for a Digilent S3BOARD    rtl/sys_gen/w11a/s3board/sys_w11a_s3
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    - for a Digilent Nexys2     rtl/sys_gen/w11a/nexys2/sys_w11a_n2

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