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# $Id: w11a_tb_guide.txt 352 2011-01-02 13:01:37Z mueller $
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Guide to running w11a test benches
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Table of content:
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1. Unit tests benches
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2. Available unit tests benches
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3. System tests benches
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4. Available system tests benches
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1. Unit tests benches -----------------------------------------------------
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All unit test benches have the same simple structure:
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- a stimulus process reads test patterns as well as the expected
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responses from a stimulus file
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- the responses are checked in very simple cases by the stimulus process,
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in general by a monitoring process
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- the test bench produces a comprehensive log file. For each checked
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response the line contains the word "CHECK" and either an "OK" or a
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"FAIL", in the later case in general with an indication of whats wrong.
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Other unexpected behaviour, like timeouts, will also result in a line
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containing the word "FAIL".
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- at the end a line with the word "DONE" is printed.
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- the test bench is run like
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tbw [stimfile] | tee | egrep "(FAIL|DONE)"
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where
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- 'tbw' is a small perl script setting up a symbolic link to the
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stimulus file, the default extracted from the file tbw.dat, if
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an optional file name is give this one will be used instead.
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- 'tee' ensured that the full log is saved
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- 'egrep' filters FAIL and DONE lines, a successful run will
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produce a single DONE line
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- Most tests can be run against
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- the functional model
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- gate level models at three stages
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- the post-xst model (produced by netgen from ngc xst output)
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- the post-map model (produced by netgen from ncd ngdbuild output)
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- the post-par model (produced by netgen from ncd par output)
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This is simply done using
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make _ssim for post-xst
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make _fsim for post-map
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make _tsim for post-par
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all the rest is handled by the build environment.
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An example of a post-synthesis model is given for the w11a core test.
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2. Available unit tests benches -------------------------------------------
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In the following the available tests are listed with
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- the 'make' command to build them
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- the pipe setup to run them
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- the expected output (the run time measured on a 3 GHz system)
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- serport receiver test
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cd $RETROBASE/rtl/vlib/serport/tb
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make tb_serport_uart_rx
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time tbw tb_serport_uart_rx |\
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tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
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-> 1269955.0 ns 63488: DONE
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-> real 0m1.178s user 0m1.172s sys 0m0.020s
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- serport receiver/transmitter test
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make tb_serport_uart_rxtx
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time tbw tb_serport_uart_rxtx |\
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tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
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-> 52335.0 ns 2607: DONE
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-> real 0m0.094s user 0m0.092s sys 0m0.008s
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- serport autobauder test
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make tb_serport_autobaud
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time tbw tb_serport_autobaud |\
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tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)"
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-> 367475.0 ns 18364: DONE
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-> real 0m0.610s user 0m0.612s sys 0m0.004s
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- rlink core test
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cd $RETROBASE/rtl/vlib/rlink/tb
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make tb_rlink_direct
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time tbw tb_rlink_direct |\
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tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
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-> 142355.0 ns 7108: DONE
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-> real 0m0.317s user 0m0.324s sys 0m0.028s
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- rlink core test via serial port interface
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make tb_rlink_serport
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time tbw tb_rlink_serport tb_rlink_serport_stim.dat |\
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tee tb_rlink_serport_stim2_dsim.log | egrep "(FAIL|DONE)"
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-> 72735.0 ns 3627: DONE
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-> real 0m0.266s user 0m0.264s sys 0m0.008s
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time tbw tb_rlink_serport tb_rlink_stim.dat |\
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tee tb_rlink_serport_dsim.log | egrep "(FAIL|DONE)"
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-> 536155.0 ns 26798: DONE
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-> real 0m1.714s user 0m1.704s sys 0m0.044s
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- w11a core test (using behavioural model)
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cd $RETROBASE/rtl/w11a/tb
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make tb_pdp11core
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time tbw tb_pdp11core |\
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tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
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-> 1220255.0 ns 61003: DONE
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-> real 0m10.736s user 0m10.713s sys 0m0.060s
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- w11a core test (using post-synthesis model)
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make ghdl_tmp_clean tb_pdp11core_ssim
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time tbw tb_pdp11core_ssim |\
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tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
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-> 1220255.0 ns 61003: DONE
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-> real 1m9.738s user 1m9.588s sys 0m0.096s
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3. System tests benches ---------------------------------------------------
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The system tests allow to verify to verify the full 11/70 SoC design.
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In this case vhdl test bench code contains
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- (simple) models of the memories used on the FPGA boards
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- drivers for the rlink connection (currently just serialport)
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- code to interface the rlink data stream to a UNIX 'named pipe',
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implemented with a C routine which is called via VHPI from VHDL.
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This way the whole ghdl simulation can be controlled via a di-directional
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byte stream.
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The rlink backend process, currently a perl script named pi_rri, can connect
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either via a named pipe to a ghdl simulation, or via a serial port to a
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FPGA board. This way the same tests can be executed in simulation and
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on real hardware.
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4. Available system tests benches -----------------------------------------
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The stimulus file used in the w11a core test can be executed in the
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full system context (both s3board and nexys2 versions) with the
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following commands. Note that the cycle number printed in the DONE
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line can now vary slightly because the response time of the rlink
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backend process and thus scheduling of backend vs. ghdl process
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can affect the result.
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- sys_w11a_s3 system test
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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make tb_w11a_s3
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time pi_rri --fifo --timeout=40. --cmax=3 \
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--run="tbw tb_w11a_s3" -- \
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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-> 7757655.0 ns 387873: DONE
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-> real 0m49.835s user 0m50.203s sys 0m0.696s
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- sys_w11a_n2 system test
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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make tb_w11a_n2
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time pi_rri --fifo --timeout=40. --cmax=3 \
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--run="tbw tb_w11a_n2" -- \
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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-> 6673237.2 ns 387035: DONE
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-> real 0m56.173s user 0m56.612s sys 0m0.604s
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