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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [bplib/] [nxcramlib/] [nx_cram_dummy.vhd] - Blame information for rev 2

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1 2 wfjm
-- $Id: n2_cram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for complete details.
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-- 
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------------------------------------------------------------------------------
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-- Module Name:    n2_cram_dummy - syn
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-- Description:    nexys2: CRAM protection dummy
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--
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-- Dependencies:   -
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-- Test bench:     -
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-- Target Devices: generic
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-- Tool versions:  xst 11.4; ghdl 0.26
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-- Revision History: 
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-- Date         Rev Version  Comment
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-- 2010-05-28   295   1.0.1  use _ADV_N
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-- 2010-05-21   292   1.0    Initial version 
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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entity n2_cram_dummy is                 -- CRAM protection dummy
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  port (
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    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
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    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
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    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
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    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
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    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)
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    O_MEM_CLK : out slbit;              -- cram: clock
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    O_MEM_CRE : out slbit;              -- cram: command register enable
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    I_MEM_WAIT : in slbit;              -- cram: mem wait
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    O_FLA_CE_N : out slbit;             -- flash ce..          (act.low)
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    O_MEM_ADDR  : out slv23;            -- cram: address lines
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    IO_MEM_DATA : inout slv16           -- cram: data lines
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  );
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end n2_cram_dummy;
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architecture syn of n2_cram_dummy is
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begin
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  O_MEM_CE_N  <= '1';                    -- disable cram chip
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  O_MEM_BE_N  <= "11";
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  O_MEM_WE_N  <= '1';
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  O_MEM_OE_N  <= '1';
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  O_MEM_ADV_N <= '1';
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  O_MEM_CLK   <= '0';
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  O_MEM_CRE   <= '0';
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  O_FLA_CE_N  <= '1';
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  O_MEM_ADDR  <= (others=>'0');
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  IO_MEM_DATA <= (others=>'0');
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end syn;

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