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-- $Id: nxcramlib.vhd 433 2011-11-27 22:04:39Z mueller $
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: nxcramlib
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-- Description: Nexys 2/3 CRAM drivers
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--
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-- Dependencies: -
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-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package nxcramlib is
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component nx_cram_dummy is -- CRAM protection dummy
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port (
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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);
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end component;
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component nx_cram_memctl_as is -- CRAM driver (async+page mode)
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generic (
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READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
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READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
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WRITEDELAY : positive := 3); -- write delay in clock cycles
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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REQ : in slbit; -- request
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WE : in slbit; -- write enable
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BUSY : out slbit; -- controller busy
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ACK_R : out slbit; -- acknowledge read
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ACK_W : out slbit; -- acknowledge write
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ACT_R : out slbit; -- signal active read
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ACT_W : out slbit; -- signal active write
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ADDR : in slv22; -- address (32 bit word address)
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BE : in slv4; -- byte enable
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DI : in slv32; -- data in (memory view)
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DO : out slv32; -- data out (memory view)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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);
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end component;
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end package nxcramlib;
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