1 |
21 |
wfjm |
-- $Id: ibdr_pc11.vhd 515 2013-05-04 17:28:59Z mueller $
|
2 |
2 |
wfjm |
--
|
3 |
21 |
wfjm |
-- Copyright 2009-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
2 |
wfjm |
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Module Name: ibdr_pc11 - syn
|
16 |
|
|
-- Description: ibus dev(rem): PC11
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: -
|
19 |
|
|
-- Test bench: xxdp: zpcae0
|
20 |
|
|
-- Target Devices: generic
|
21 |
21 |
wfjm |
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.3; ghdl 0.18-0.29
|
22 |
2 |
wfjm |
--
|
23 |
|
|
-- Synthesized (xst):
|
24 |
|
|
-- Date Rev ise Target flop lutl lutm slic t peri
|
25 |
9 |
wfjm |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
|
26 |
|
|
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
|
27 |
2 |
wfjm |
--
|
28 |
|
|
-- Revision History:
|
29 |
|
|
-- Date Rev Version Comment
|
30 |
21 |
wfjm |
-- 2013-05-04 515 1.3 BUGFIX: r.rbuf was immediately cleared ! Was broken
|
31 |
|
|
-- since ibus V2 update, never tested afterwards...
|
32 |
13 |
wfjm |
-- 2011-11-18 427 1.2.2 now numeric_std clean
|
33 |
8 |
wfjm |
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
|
34 |
|
|
-- 2010-10-17 333 1.2 use ibus V2 interface
|
35 |
2 |
wfjm |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
|
36 |
|
|
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
|
37 |
|
|
-- causes interrupt, if enabled; validated with zpcae0
|
38 |
|
|
-- 2009-06-01 221 0.9 Initial version (untested)
|
39 |
|
|
------------------------------------------------------------------------------
|
40 |
|
|
|
41 |
|
|
library ieee;
|
42 |
|
|
use ieee.std_logic_1164.all;
|
43 |
13 |
wfjm |
use ieee.numeric_std.all;
|
44 |
2 |
wfjm |
|
45 |
|
|
use work.slvtypes.all;
|
46 |
|
|
use work.iblib.all;
|
47 |
|
|
|
48 |
|
|
-- ----------------------------------------------------------------------------
|
49 |
|
|
entity ibdr_pc11 is -- ibus dev(rem): PC11
|
50 |
|
|
-- fixed address: 177550
|
51 |
|
|
port (
|
52 |
|
|
CLK : in slbit; -- clock
|
53 |
|
|
RESET : in slbit; -- system reset
|
54 |
|
|
BRESET : in slbit; -- ibus reset
|
55 |
8 |
wfjm |
RB_LAM : out slbit; -- remote attention
|
56 |
2 |
wfjm |
IB_MREQ : in ib_mreq_type; -- ibus request
|
57 |
|
|
IB_SRES : out ib_sres_type; -- ibus response
|
58 |
|
|
EI_REQ_PTR : out slbit; -- interrupt request, reader
|
59 |
|
|
EI_REQ_PTP : out slbit; -- interrupt request, punch
|
60 |
|
|
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
|
61 |
|
|
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
|
62 |
|
|
);
|
63 |
|
|
end ibdr_pc11;
|
64 |
|
|
|
65 |
|
|
architecture syn of ibdr_pc11 is
|
66 |
|
|
|
67 |
13 |
wfjm |
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
|
68 |
2 |
wfjm |
|
69 |
|
|
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
|
70 |
|
|
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
|
71 |
|
|
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
|
72 |
|
|
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
|
73 |
|
|
|
74 |
|
|
constant rcsr_ibf_rerr : integer := 15;
|
75 |
|
|
constant rcsr_ibf_rbusy : integer := 11;
|
76 |
|
|
constant rcsr_ibf_rdone : integer := 7;
|
77 |
|
|
constant rcsr_ibf_rie : integer := 6;
|
78 |
|
|
constant rcsr_ibf_renb : integer := 0;
|
79 |
|
|
|
80 |
|
|
constant pcsr_ibf_perr : integer := 15;
|
81 |
|
|
constant pcsr_ibf_prdy : integer := 7;
|
82 |
|
|
constant pcsr_ibf_pie : integer := 6;
|
83 |
|
|
|
84 |
|
|
constant pbuf_ibf_pval : integer := 8;
|
85 |
|
|
constant pbuf_ibf_rbusy : integer := 9;
|
86 |
|
|
|
87 |
|
|
type regs_type is record -- state registers
|
88 |
8 |
wfjm |
ibsel : slbit; -- ibus select
|
89 |
2 |
wfjm |
rerr : slbit; -- rcsr: reader error
|
90 |
|
|
rbusy : slbit; -- rcsr: reader busy
|
91 |
|
|
rdone : slbit; -- rcsr: reader done
|
92 |
|
|
rie : slbit; -- rcsr: reader interrupt enable
|
93 |
|
|
rbuf : slv8; -- rbuf:
|
94 |
|
|
rintreq : slbit; -- ptr interrupt request
|
95 |
|
|
perr : slbit; -- pcsr: punch error
|
96 |
|
|
prdy : slbit; -- pcsr: punch ready
|
97 |
|
|
pie : slbit; -- pcsr: punch interrupt enable
|
98 |
|
|
pbuf : slv8; -- pbuf:
|
99 |
|
|
pintreq : slbit; -- ptp interrupt request
|
100 |
|
|
end record regs_type;
|
101 |
|
|
|
102 |
|
|
constant regs_init : regs_type := (
|
103 |
8 |
wfjm |
'0', -- ibsel
|
104 |
2 |
wfjm |
'1', -- rerr (init=1!)
|
105 |
|
|
'0','0','0', -- rbusy,rdone,rie
|
106 |
|
|
(others=>'0'), -- rbuf
|
107 |
|
|
'0', -- rintreq
|
108 |
|
|
'1', -- perr (init=1!)
|
109 |
|
|
'1', -- prdy (init=1!)
|
110 |
|
|
'0', -- pie
|
111 |
|
|
(others=>'0'), -- pbuf
|
112 |
|
|
'0' -- pintreq
|
113 |
|
|
);
|
114 |
|
|
|
115 |
|
|
signal R_REGS : regs_type := regs_init;
|
116 |
|
|
signal N_REGS : regs_type := regs_init;
|
117 |
|
|
|
118 |
|
|
begin
|
119 |
|
|
|
120 |
|
|
proc_regs: process (CLK)
|
121 |
|
|
begin
|
122 |
13 |
wfjm |
if rising_edge(CLK) then
|
123 |
2 |
wfjm |
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
|
124 |
|
|
R_REGS <= regs_init; --
|
125 |
|
|
if RESET = '0' then -- if RESET=0 we do just an ibus reset
|
126 |
|
|
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
|
127 |
|
|
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
|
128 |
|
|
end if;
|
129 |
8 |
wfjm |
else
|
130 |
2 |
wfjm |
R_REGS <= N_REGS;
|
131 |
|
|
end if;
|
132 |
|
|
end if;
|
133 |
|
|
end process proc_regs;
|
134 |
|
|
|
135 |
|
|
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
|
136 |
|
|
variable r : regs_type := regs_init;
|
137 |
|
|
variable n : regs_type := regs_init;
|
138 |
|
|
variable idout : slv16 := (others=>'0');
|
139 |
8 |
wfjm |
variable ibreq : slbit := '0';
|
140 |
2 |
wfjm |
variable ibrd : slbit := '0';
|
141 |
|
|
variable ibw0 : slbit := '0';
|
142 |
|
|
variable ibw1 : slbit := '0';
|
143 |
|
|
variable ilam : slbit := '0';
|
144 |
|
|
begin
|
145 |
|
|
|
146 |
|
|
r := R_REGS;
|
147 |
|
|
n := R_REGS;
|
148 |
|
|
|
149 |
8 |
wfjm |
idout := (others=>'0');
|
150 |
|
|
ibreq := IB_MREQ.re or IB_MREQ.we;
|
151 |
|
|
ibrd := IB_MREQ.re;
|
152 |
|
|
ibw0 := IB_MREQ.we and IB_MREQ.be0;
|
153 |
|
|
ibw1 := IB_MREQ.we and IB_MREQ.be1;
|
154 |
|
|
ilam := '0';
|
155 |
2 |
wfjm |
|
156 |
|
|
-- ibus address decoder
|
157 |
8 |
wfjm |
n.ibsel := '0';
|
158 |
|
|
if IB_MREQ.aval='1' and
|
159 |
2 |
wfjm |
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
|
160 |
8 |
wfjm |
n.ibsel := '1';
|
161 |
2 |
wfjm |
end if;
|
162 |
|
|
|
163 |
|
|
-- ibus transactions
|
164 |
8 |
wfjm |
if r.ibsel = '1' then
|
165 |
2 |
wfjm |
case IB_MREQ.addr(2 downto 1) is
|
166 |
|
|
|
167 |
|
|
when ibaddr_rcsr => -- RCSR -- reader control status -----
|
168 |
|
|
|
169 |
|
|
idout(rcsr_ibf_rerr) := r.rerr;
|
170 |
|
|
idout(rcsr_ibf_rbusy) := r.rbusy;
|
171 |
|
|
idout(rcsr_ibf_rdone) := r.rdone;
|
172 |
|
|
idout(rcsr_ibf_rie) := r.rie;
|
173 |
|
|
|
174 |
|
|
if IB_MREQ.racc = '0' then -- cpu ---------------------
|
175 |
|
|
if ibw0 = '1' then
|
176 |
|
|
n.rie := IB_MREQ.din(rcsr_ibf_rie);
|
177 |
|
|
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
|
178 |
|
|
if r.rie = '0' and -- IE 0->1 transition
|
179 |
|
|
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
|
180 |
|
|
(r.rerr='1' or r.rdone='1') then -- but err or done set
|
181 |
|
|
n.rintreq := '1'; -- request interrupt
|
182 |
|
|
end if;
|
183 |
|
|
else -- set IE to 0
|
184 |
|
|
n.rintreq := '0'; -- cancel interrupts
|
185 |
|
|
end if;
|
186 |
|
|
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
|
187 |
|
|
if r.rerr = '0' then -- if not in error state
|
188 |
|
|
n.rbusy := '1'; -- set busy
|
189 |
|
|
n.rdone := '0'; -- clear done
|
190 |
|
|
n.rbuf := (others=>'0'); -- clear buffer
|
191 |
|
|
n.rintreq := '0'; -- cancel interrupt
|
192 |
|
|
ilam := '1'; -- rri lam
|
193 |
|
|
else -- if in error state
|
194 |
|
|
if r.rie = '1' then -- if interrupts on
|
195 |
|
|
n.rintreq := '1'; -- request interrupt
|
196 |
|
|
end if;
|
197 |
|
|
end if;
|
198 |
|
|
end if;
|
199 |
|
|
end if;
|
200 |
|
|
|
201 |
|
|
else -- rri ---------------------
|
202 |
|
|
if ibw1 = '1' then
|
203 |
|
|
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
|
204 |
|
|
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
|
205 |
|
|
and r.rerr='0' then
|
206 |
|
|
n.rbusy := '0'; -- clear busy
|
207 |
|
|
n.rdone := '0'; -- clear done
|
208 |
|
|
if r.rie = '1' then -- if interrupts on
|
209 |
|
|
n.rintreq := '1'; -- request interrupt
|
210 |
|
|
end if;
|
211 |
|
|
end if;
|
212 |
|
|
end if;
|
213 |
|
|
end if;
|
214 |
|
|
|
215 |
|
|
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
|
216 |
|
|
|
217 |
|
|
idout(r.rbuf'range) := r.rbuf;
|
218 |
|
|
|
219 |
|
|
if IB_MREQ.racc = '0' then -- cpu ---------------------
|
220 |
21 |
wfjm |
if ibreq = '1' then -- !! PC11 is unusual !!
|
221 |
|
|
n.rdone := '0'; -- *any* read or write will clear done
|
222 |
2 |
wfjm |
n.rbuf := (others=>'0'); -- and the reader buffer
|
223 |
|
|
n.rintreq := '0'; -- also interrupt is canceled
|
224 |
|
|
end if;
|
225 |
|
|
|
226 |
|
|
else -- rri ---------------------
|
227 |
|
|
if ibw0 = '1' then
|
228 |
|
|
n.rbuf := IB_MREQ.din(n.rbuf'range);
|
229 |
|
|
n.rbusy := '0';
|
230 |
|
|
n.rdone := '1';
|
231 |
|
|
if r.rie = '1' then
|
232 |
|
|
n.rintreq := '1';
|
233 |
|
|
end if;
|
234 |
|
|
end if;
|
235 |
|
|
end if;
|
236 |
|
|
|
237 |
|
|
when ibaddr_pcsr => -- PCSR -- punch control status ------
|
238 |
|
|
|
239 |
|
|
idout(pcsr_ibf_perr) := r.perr;
|
240 |
|
|
idout(pcsr_ibf_prdy) := r.prdy;
|
241 |
|
|
idout(pcsr_ibf_pie) := r.pie;
|
242 |
|
|
|
243 |
|
|
if IB_MREQ.racc = '0' then -- cpu ---------------------
|
244 |
|
|
if ibw0 = '1' then
|
245 |
|
|
n.pie := IB_MREQ.din(pcsr_ibf_pie);
|
246 |
|
|
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
|
247 |
|
|
if r.pie='0' and -- IE 0->1 transition
|
248 |
|
|
(r.perr='1' or r.prdy='1') then -- but err or done set
|
249 |
|
|
n.pintreq := '1'; -- request interrupt
|
250 |
|
|
end if;
|
251 |
|
|
else -- set IE to 0
|
252 |
|
|
n.pintreq := '0'; -- cancel interrupts
|
253 |
|
|
end if;
|
254 |
|
|
end if;
|
255 |
|
|
|
256 |
|
|
else -- rri ---------------------
|
257 |
|
|
if ibw1 = '1' then
|
258 |
|
|
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
|
259 |
|
|
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
|
260 |
|
|
and r.perr='0' then
|
261 |
|
|
n.prdy := '1'; -- set ready
|
262 |
|
|
if r.pie = '1' then -- if interrupts on
|
263 |
|
|
n.pintreq := '1'; -- request interrupt
|
264 |
|
|
end if;
|
265 |
|
|
end if;
|
266 |
|
|
end if;
|
267 |
|
|
end if;
|
268 |
|
|
|
269 |
|
|
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
|
270 |
|
|
|
271 |
|
|
if IB_MREQ.racc = '0' then -- cpu ---------------------
|
272 |
|
|
if ibw0 = '1' then
|
273 |
|
|
if r.perr = '0' then -- if not in error state
|
274 |
|
|
n.pbuf := IB_MREQ.din(n.pbuf'range);
|
275 |
|
|
n.prdy := '0'; -- clear ready
|
276 |
|
|
n.pintreq := '0'; -- cancel interrupts
|
277 |
|
|
ilam := '1'; -- rri lam
|
278 |
|
|
else -- if in error state
|
279 |
|
|
if r.pie = '1' then -- if interrupts on
|
280 |
|
|
n.pintreq := '1'; -- request interrupt
|
281 |
|
|
end if;
|
282 |
|
|
end if;
|
283 |
|
|
end if;
|
284 |
|
|
|
285 |
|
|
else -- rri ---------------------
|
286 |
|
|
idout(r.pbuf'range) := r.pbuf;
|
287 |
|
|
idout(pbuf_ibf_pval) := not r.prdy;
|
288 |
|
|
idout(pbuf_ibf_rbusy) := r.rbusy;
|
289 |
|
|
if ibrd = '1' then
|
290 |
|
|
n.prdy := '1';
|
291 |
|
|
if r.pie = '1' then
|
292 |
|
|
n.pintreq := '1';
|
293 |
|
|
end if;
|
294 |
|
|
end if;
|
295 |
|
|
end if;
|
296 |
|
|
|
297 |
|
|
when others => null;
|
298 |
|
|
end case;
|
299 |
|
|
|
300 |
|
|
end if;
|
301 |
|
|
|
302 |
|
|
-- other state changes
|
303 |
|
|
if EI_ACK_PTR = '1' then
|
304 |
|
|
n.rintreq := '0';
|
305 |
|
|
end if;
|
306 |
|
|
if EI_ACK_PTP = '1' then
|
307 |
|
|
n.pintreq := '0';
|
308 |
|
|
end if;
|
309 |
|
|
|
310 |
|
|
N_REGS <= n;
|
311 |
|
|
|
312 |
|
|
IB_SRES.dout <= idout;
|
313 |
8 |
wfjm |
IB_SRES.ack <= r.ibsel and ibreq;
|
314 |
2 |
wfjm |
IB_SRES.busy <= '0';
|
315 |
|
|
|
316 |
8 |
wfjm |
RB_LAM <= ilam;
|
317 |
2 |
wfjm |
EI_REQ_PTR <= r.rintreq;
|
318 |
|
|
EI_REQ_PTP <= r.pintreq;
|
319 |
|
|
|
320 |
|
|
end process proc_next;
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
end syn;
|