OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [make/] [syn_s3_speed.opt] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 wfjm
FLOWTYPE = FPGA_SYNTHESIS;
2
#########################################################
3
## Filename: xst_vhdl.opt
4
##
5
## VHDL Option File for XST targeted for speed
6
## This works for FPGA devices.
7
##
8
## Version: 8.1.1
9
## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_vhdl_speed.opt,v 1.13 2004/10/01 22:29:20 rvklair Exp $
10
#########################################################
11
# Options for XST
12
#
13
#
14
#
15
Program xst
16
-ifn _xst.scr;            # input XST script file
17
-ofn _xst.log;            # output XST log file
18
-intstyle xflow;                  # Message Reporting Style: ise, xflow, or silent
19
#
20
# The options listed under ParamFile are the XST Properties that can be set by the
21
# user. To turn on an option, uncomment by removing the '#' in front of the switch.
22
#
23
ParamFile: _xst.scr
24
"run";
25
#
26
# Global Synthesis Options
27
#
28
"-ifn ";             # Input/Project File Name
29
"-ifmt VHDL";                     # Input Format
30
"-ofn ";                  # Output File Name
31
"-ofmt ngc";                      # Output File Format
32
"-p ";                  # Target Device
33
"-opt_mode SPEED";                # Optimization Criteria # AREA or SPEED
34
"-opt_level 2";
35
"-uc .xcf";               # Constraint File name
36
#"-case maintain";                # Specifies how to handle source name case
37
                                  # upper, lower
38
#"-keep_hierarchy NO";            # Prevents optimization across module boundaries
39
                                  # CPLD default YES, FPGA default NO
40
#"-write_timing_constraints NO";  # Write Timing Constraints
41
                                  # YES, NO
42
#"-cross_clock_analysis NO";      # Cross Clock Option
43
                                  # YES, NO
44
#"-iobuf YES";                    # Add I/O Buffers to top level portS
45
                                  # YES, NO
46
#
47
# The following are HDL Options
48
#
49
# The following are Xilinx FPGA specific options for Virtex, VirtexE, Virtex-II and Spartan2
50
#
51
#"-register_balancing NO";        # Register Balancing
52
                                  # YES, NO, Forward, Backward
53
#"-move_first_stage YES";         # Move First Flip-Flop Stage
54
                                  # YES, NO
55
#"-move_last_stage YES";          # Move Last Flip-Flop Stage
56
                                  # YES, NO
57
End ParamFile
58
End Program xst
59
#
60
# See XST USER Guide Chapter 8 (Command Line Mode) for all XST options
61
#
62
 
63
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.