| 1 |
17 |
wfjm |
-- $Id: sys_tst_fx2loop_n2.vhd 461 2012-04-09 21:17:54Z mueller $
|
| 2 |
|
|
--
|
| 3 |
|
|
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
| 4 |
|
|
--
|
| 5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
| 6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
| 7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
| 8 |
|
|
--
|
| 9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
| 10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
| 11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 12 |
|
|
-- for complete details.
|
| 13 |
|
|
--
|
| 14 |
|
|
------------------------------------------------------------------------------
|
| 15 |
|
|
-- Module Name: sys_tst_fx2loop_n2 - syn
|
| 16 |
|
|
-- Description: test of Cypress EZ-USB FX2 controller
|
| 17 |
|
|
--
|
| 18 |
|
|
-- Dependencies: vlib/xlib/dcm_sfs
|
| 19 |
|
|
-- vlib/genlib/clkdivce
|
| 20 |
|
|
-- bpgen/sn_humanio
|
| 21 |
|
|
-- tst_fx2loop_hiomap
|
| 22 |
|
|
-- tst_fx2loop
|
| 23 |
|
|
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
|
| 24 |
|
|
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
|
| 25 |
|
|
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
|
| 26 |
|
|
-- bplib/nxcramlib/nx_cram_dummy
|
| 27 |
|
|
--
|
| 28 |
|
|
-- Test bench: -
|
| 29 |
|
|
--
|
| 30 |
|
|
-- Target Devices: generic
|
| 31 |
|
|
-- Tool versions: xst 13.3; ghdl 0.29
|
| 32 |
|
|
--
|
| 33 |
|
|
-- Synthesized (xst):
|
| 34 |
|
|
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
|
| 35 |
|
|
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100
|
| 36 |
|
|
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100
|
| 37 |
|
|
-- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100
|
| 38 |
|
|
--
|
| 39 |
|
|
-- Revision History:
|
| 40 |
|
|
-- Date Rev Version Comment
|
| 41 |
|
|
-- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers
|
| 42 |
|
|
-- 2011-12-26 445 1.0 Initial version
|
| 43 |
|
|
------------------------------------------------------------------------------
|
| 44 |
|
|
|
| 45 |
|
|
library ieee;
|
| 46 |
|
|
use ieee.std_logic_1164.all;
|
| 47 |
|
|
use ieee.numeric_std.all;
|
| 48 |
|
|
|
| 49 |
|
|
use work.slvtypes.all;
|
| 50 |
|
|
use work.xlib.all;
|
| 51 |
|
|
use work.genlib.all;
|
| 52 |
|
|
use work.bpgenlib.all;
|
| 53 |
|
|
use work.tst_fx2looplib.all;
|
| 54 |
|
|
use work.fx2lib.all;
|
| 55 |
|
|
use work.nxcramlib.all;
|
| 56 |
|
|
use work.sys_conf.all;
|
| 57 |
|
|
|
| 58 |
|
|
-- ----------------------------------------------------------------------------
|
| 59 |
|
|
|
| 60 |
|
|
entity sys_tst_fx2loop_n2 is -- top level
|
| 61 |
|
|
-- implements nexys2_aif + fx2 pins
|
| 62 |
|
|
port (
|
| 63 |
|
|
I_CLK50 : in slbit; -- 50 MHz board clock
|
| 64 |
|
|
I_RXD : in slbit; -- receive data (board view)
|
| 65 |
|
|
O_TXD : out slbit; -- transmit data (board view)
|
| 66 |
|
|
I_SWI : in slv8; -- n2 switches
|
| 67 |
|
|
I_BTN : in slv4; -- n2 buttons
|
| 68 |
|
|
O_LED : out slv8; -- n2 leds
|
| 69 |
|
|
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
|
| 70 |
|
|
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
|
| 71 |
|
|
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
|
| 72 |
|
|
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
|
| 73 |
|
|
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
|
| 74 |
|
|
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
|
| 75 |
|
|
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
|
| 76 |
|
|
O_MEM_CLK : out slbit; -- cram: clock
|
| 77 |
|
|
O_MEM_CRE : out slbit; -- cram: command register enable
|
| 78 |
|
|
I_MEM_WAIT : in slbit; -- cram: mem wait
|
| 79 |
|
|
O_MEM_ADDR : out slv23; -- cram: address lines
|
| 80 |
|
|
IO_MEM_DATA : inout slv16; -- cram: data lines
|
| 81 |
|
|
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
|
| 82 |
|
|
I_FX2_IFCLK : in slbit; -- fx2: interface clock
|
| 83 |
|
|
O_FX2_FIFO : out slv2; -- fx2: fifo address
|
| 84 |
|
|
I_FX2_FLAG : in slv4; -- fx2: fifo flags
|
| 85 |
|
|
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
|
| 86 |
|
|
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
|
| 87 |
|
|
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
|
| 88 |
|
|
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
|
| 89 |
|
|
IO_FX2_DATA : inout slv8 -- fx2: data lines
|
| 90 |
|
|
);
|
| 91 |
|
|
end sys_tst_fx2loop_n2;
|
| 92 |
|
|
|
| 93 |
|
|
architecture syn of sys_tst_fx2loop_n2 is
|
| 94 |
|
|
|
| 95 |
|
|
signal CLK : slbit := '0';
|
| 96 |
|
|
signal RESET : slbit := '0';
|
| 97 |
|
|
|
| 98 |
|
|
signal CE_USEC : slbit := '0';
|
| 99 |
|
|
signal CE_MSEC : slbit := '0';
|
| 100 |
|
|
|
| 101 |
|
|
signal SWI : slv8 := (others=>'0');
|
| 102 |
|
|
signal BTN : slv4 := (others=>'0');
|
| 103 |
|
|
signal LED : slv8 := (others=>'0');
|
| 104 |
|
|
signal DSP_DAT : slv16 := (others=>'0');
|
| 105 |
|
|
signal DSP_DP : slv4 := (others=>'0');
|
| 106 |
|
|
|
| 107 |
|
|
signal LED_MAP : slv8 := (others=>'0');
|
| 108 |
|
|
|
| 109 |
|
|
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
|
| 110 |
|
|
signal HIO_STAT : hio_stat_type := hio_stat_init;
|
| 111 |
|
|
|
| 112 |
|
|
signal FX2_RXDATA : slv8 := (others=>'0');
|
| 113 |
|
|
signal FX2_RXVAL : slbit := '0';
|
| 114 |
|
|
signal FX2_RXHOLD : slbit := '0';
|
| 115 |
|
|
signal FX2_RXAEMPTY : slbit := '0';
|
| 116 |
|
|
signal FX2_TXDATA : slv8 := (others=>'0');
|
| 117 |
|
|
signal FX2_TXENA : slbit := '0';
|
| 118 |
|
|
signal FX2_TXBUSY : slbit := '0';
|
| 119 |
|
|
signal FX2_TXAFULL : slbit := '0';
|
| 120 |
|
|
signal FX2_TX2DATA : slv8 := (others=>'0');
|
| 121 |
|
|
signal FX2_TX2ENA : slbit := '0';
|
| 122 |
|
|
signal FX2_TX2BUSY : slbit := '1';
|
| 123 |
|
|
signal FX2_TX2AFULL : slbit := '0';
|
| 124 |
|
|
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
|
| 125 |
|
|
|
| 126 |
|
|
begin
|
| 127 |
|
|
|
| 128 |
|
|
assert (sys_conf_clksys mod 1000000) = 0
|
| 129 |
|
|
report "assert sys_conf_clksys on MHz grid"
|
| 130 |
|
|
severity failure;
|
| 131 |
|
|
|
| 132 |
|
|
DCM : dcm_sfs
|
| 133 |
|
|
generic map (
|
| 134 |
|
|
CLKFX_DIVIDE => sys_conf_clkfx_divide,
|
| 135 |
|
|
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
|
| 136 |
|
|
CLKIN_PERIOD => 20.0)
|
| 137 |
|
|
port map (
|
| 138 |
|
|
CLKIN => I_CLK50,
|
| 139 |
|
|
CLKFX => CLK,
|
| 140 |
|
|
LOCKED => open
|
| 141 |
|
|
);
|
| 142 |
|
|
|
| 143 |
|
|
CLKDIV : clkdivce
|
| 144 |
|
|
generic map (
|
| 145 |
|
|
CDUWIDTH => 7, -- good for up to 127 MHz !
|
| 146 |
|
|
USECDIV => sys_conf_clksys_mhz,
|
| 147 |
|
|
MSECDIV => 1000)
|
| 148 |
|
|
port map (
|
| 149 |
|
|
CLK => CLK,
|
| 150 |
|
|
CE_USEC => CE_USEC,
|
| 151 |
|
|
CE_MSEC => CE_MSEC
|
| 152 |
|
|
);
|
| 153 |
|
|
|
| 154 |
|
|
HIO : sn_humanio
|
| 155 |
|
|
generic map (
|
| 156 |
|
|
DEBOUNCE => sys_conf_hio_debounce)
|
| 157 |
|
|
port map (
|
| 158 |
|
|
CLK => CLK,
|
| 159 |
|
|
RESET => '0',
|
| 160 |
|
|
CE_MSEC => CE_MSEC,
|
| 161 |
|
|
SWI => SWI,
|
| 162 |
|
|
BTN => BTN,
|
| 163 |
|
|
LED => LED,
|
| 164 |
|
|
DSP_DAT => DSP_DAT,
|
| 165 |
|
|
DSP_DP => DSP_DP,
|
| 166 |
|
|
I_SWI => I_SWI,
|
| 167 |
|
|
I_BTN => I_BTN,
|
| 168 |
|
|
O_LED => O_LED,
|
| 169 |
|
|
O_ANO_N => O_ANO_N,
|
| 170 |
|
|
O_SEG_N => O_SEG_N
|
| 171 |
|
|
);
|
| 172 |
|
|
|
| 173 |
|
|
RESET <= BTN(0); -- BTN(0) will reset tester !!
|
| 174 |
|
|
|
| 175 |
|
|
HIOMAP : tst_fx2loop_hiomap
|
| 176 |
|
|
port map (
|
| 177 |
|
|
CLK => CLK,
|
| 178 |
|
|
RESET => RESET,
|
| 179 |
|
|
HIO_CNTL => HIO_CNTL,
|
| 180 |
|
|
HIO_STAT => HIO_STAT,
|
| 181 |
|
|
FX2_MONI => FX2_MONI,
|
| 182 |
|
|
SWI => SWI,
|
| 183 |
|
|
BTN => BTN,
|
| 184 |
|
|
LED => LED_MAP,
|
| 185 |
|
|
DSP_DAT => DSP_DAT,
|
| 186 |
|
|
DSP_DP => DSP_DP
|
| 187 |
|
|
);
|
| 188 |
|
|
|
| 189 |
|
|
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
|
| 190 |
|
|
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
|
| 191 |
|
|
begin
|
| 192 |
|
|
|
| 193 |
|
|
if SWI(4) = '1' then
|
| 194 |
|
|
LED(7) <= '0';
|
| 195 |
|
|
LED(6) <= '0';
|
| 196 |
|
|
LED(5) <= FX2_TX2BUSY;
|
| 197 |
|
|
LED(4) <= FX2_TX2ENA;
|
| 198 |
|
|
LED(3) <= FX2_TXBUSY;
|
| 199 |
|
|
LED(2) <= FX2_TXENA;
|
| 200 |
|
|
LED(1) <= FX2_RXHOLD;
|
| 201 |
|
|
LED(0) <= FX2_RXVAL;
|
| 202 |
|
|
else
|
| 203 |
|
|
LED <= LED_MAP;
|
| 204 |
|
|
end if;
|
| 205 |
|
|
|
| 206 |
|
|
end process proc_led;
|
| 207 |
|
|
|
| 208 |
|
|
|
| 209 |
|
|
TST : tst_fx2loop
|
| 210 |
|
|
port map (
|
| 211 |
|
|
CLK => CLK,
|
| 212 |
|
|
RESET => RESET,
|
| 213 |
|
|
CE_MSEC => CE_MSEC,
|
| 214 |
|
|
HIO_CNTL => HIO_CNTL,
|
| 215 |
|
|
HIO_STAT => HIO_STAT,
|
| 216 |
|
|
FX2_MONI => FX2_MONI,
|
| 217 |
|
|
RXDATA => FX2_RXDATA,
|
| 218 |
|
|
RXVAL => FX2_RXVAL,
|
| 219 |
|
|
RXHOLD => FX2_RXHOLD,
|
| 220 |
|
|
TXDATA => FX2_TXDATA,
|
| 221 |
|
|
TXENA => FX2_TXENA,
|
| 222 |
|
|
TXBUSY => FX2_TXBUSY,
|
| 223 |
|
|
TX2DATA => FX2_TX2DATA,
|
| 224 |
|
|
TX2ENA => FX2_TX2ENA,
|
| 225 |
|
|
TX2BUSY => FX2_TX2BUSY
|
| 226 |
|
|
);
|
| 227 |
|
|
|
| 228 |
|
|
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
|
| 229 |
|
|
CNTL : fx2_2fifoctl_as
|
| 230 |
|
|
generic map (
|
| 231 |
|
|
RXFAWIDTH => 5,
|
| 232 |
|
|
TXFAWIDTH => 5,
|
| 233 |
|
|
CCWIDTH => sys_conf_fx2_ccwidth,
|
| 234 |
|
|
RXAEMPTY_THRES => 1,
|
| 235 |
|
|
TXAFULL_THRES => 1,
|
| 236 |
|
|
PETOWIDTH => sys_conf_fx2_petowidth,
|
| 237 |
|
|
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
|
| 238 |
|
|
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
|
| 239 |
|
|
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
|
| 240 |
|
|
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
|
| 241 |
|
|
FLAGDELAY => sys_conf_fx2_flagdelay)
|
| 242 |
|
|
port map (
|
| 243 |
|
|
CLK => CLK,
|
| 244 |
|
|
CE_USEC => CE_USEC,
|
| 245 |
|
|
RESET => RESET,
|
| 246 |
|
|
RXDATA => FX2_RXDATA,
|
| 247 |
|
|
RXVAL => FX2_RXVAL,
|
| 248 |
|
|
RXHOLD => FX2_RXHOLD,
|
| 249 |
|
|
RXAEMPTY => FX2_RXAEMPTY,
|
| 250 |
|
|
TXDATA => FX2_TXDATA,
|
| 251 |
|
|
TXENA => FX2_TXENA,
|
| 252 |
|
|
TXBUSY => FX2_TXBUSY,
|
| 253 |
|
|
TXAFULL => FX2_TXAFULL,
|
| 254 |
|
|
MONI => FX2_MONI,
|
| 255 |
|
|
I_FX2_IFCLK => I_FX2_IFCLK,
|
| 256 |
|
|
O_FX2_FIFO => O_FX2_FIFO,
|
| 257 |
|
|
I_FX2_FLAG => I_FX2_FLAG,
|
| 258 |
|
|
O_FX2_SLRD_N => O_FX2_SLRD_N,
|
| 259 |
|
|
O_FX2_SLWR_N => O_FX2_SLWR_N,
|
| 260 |
|
|
O_FX2_SLOE_N => O_FX2_SLOE_N,
|
| 261 |
|
|
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
|
| 262 |
|
|
IO_FX2_DATA => IO_FX2_DATA
|
| 263 |
|
|
);
|
| 264 |
|
|
end generate FX2_CNTL_AS;
|
| 265 |
|
|
|
| 266 |
|
|
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
|
| 267 |
|
|
CNTL : fx2_2fifoctl_ic
|
| 268 |
|
|
generic map (
|
| 269 |
|
|
RXFAWIDTH => 5,
|
| 270 |
|
|
TXFAWIDTH => 5,
|
| 271 |
|
|
PETOWIDTH => sys_conf_fx2_petowidth,
|
| 272 |
|
|
CCWIDTH => sys_conf_fx2_ccwidth,
|
| 273 |
|
|
RXAEMPTY_THRES => 1,
|
| 274 |
|
|
TXAFULL_THRES => 1)
|
| 275 |
|
|
port map (
|
| 276 |
|
|
CLK => CLK,
|
| 277 |
|
|
RESET => RESET,
|
| 278 |
|
|
RXDATA => FX2_RXDATA,
|
| 279 |
|
|
RXVAL => FX2_RXVAL,
|
| 280 |
|
|
RXHOLD => FX2_RXHOLD,
|
| 281 |
|
|
RXAEMPTY => FX2_RXAEMPTY,
|
| 282 |
|
|
TXDATA => FX2_TXDATA,
|
| 283 |
|
|
TXENA => FX2_TXENA,
|
| 284 |
|
|
TXBUSY => FX2_TXBUSY,
|
| 285 |
|
|
TXAFULL => FX2_TXAFULL,
|
| 286 |
|
|
MONI => FX2_MONI,
|
| 287 |
|
|
I_FX2_IFCLK => I_FX2_IFCLK,
|
| 288 |
|
|
O_FX2_FIFO => O_FX2_FIFO,
|
| 289 |
|
|
I_FX2_FLAG => I_FX2_FLAG,
|
| 290 |
|
|
O_FX2_SLRD_N => O_FX2_SLRD_N,
|
| 291 |
|
|
O_FX2_SLWR_N => O_FX2_SLWR_N,
|
| 292 |
|
|
O_FX2_SLOE_N => O_FX2_SLOE_N,
|
| 293 |
|
|
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
|
| 294 |
|
|
IO_FX2_DATA => IO_FX2_DATA
|
| 295 |
|
|
);
|
| 296 |
|
|
end generate FX2_CNTL_IC;
|
| 297 |
|
|
|
| 298 |
|
|
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
|
| 299 |
|
|
CNTL : fx2_3fifoctl_ic
|
| 300 |
|
|
generic map (
|
| 301 |
|
|
RXFAWIDTH => 5,
|
| 302 |
|
|
TXFAWIDTH => 5,
|
| 303 |
|
|
PETOWIDTH => sys_conf_fx2_petowidth,
|
| 304 |
|
|
CCWIDTH => sys_conf_fx2_ccwidth,
|
| 305 |
|
|
RXAEMPTY_THRES => 1,
|
| 306 |
|
|
TXAFULL_THRES => 1,
|
| 307 |
|
|
TX2AFULL_THRES => 1)
|
| 308 |
|
|
port map (
|
| 309 |
|
|
CLK => CLK,
|
| 310 |
|
|
RESET => RESET,
|
| 311 |
|
|
RXDATA => FX2_RXDATA,
|
| 312 |
|
|
RXVAL => FX2_RXVAL,
|
| 313 |
|
|
RXHOLD => FX2_RXHOLD,
|
| 314 |
|
|
RXAEMPTY => FX2_RXAEMPTY,
|
| 315 |
|
|
TXDATA => FX2_TXDATA,
|
| 316 |
|
|
TXENA => FX2_TXENA,
|
| 317 |
|
|
TXBUSY => FX2_TXBUSY,
|
| 318 |
|
|
TXAFULL => FX2_TXAFULL,
|
| 319 |
|
|
TX2DATA => FX2_TX2DATA,
|
| 320 |
|
|
TX2ENA => FX2_TX2ENA,
|
| 321 |
|
|
TX2BUSY => FX2_TX2BUSY,
|
| 322 |
|
|
TX2AFULL => FX2_TX2AFULL,
|
| 323 |
|
|
MONI => FX2_MONI,
|
| 324 |
|
|
I_FX2_IFCLK => I_FX2_IFCLK,
|
| 325 |
|
|
O_FX2_FIFO => O_FX2_FIFO,
|
| 326 |
|
|
I_FX2_FLAG => I_FX2_FLAG,
|
| 327 |
|
|
O_FX2_SLRD_N => O_FX2_SLRD_N,
|
| 328 |
|
|
O_FX2_SLWR_N => O_FX2_SLWR_N,
|
| 329 |
|
|
O_FX2_SLOE_N => O_FX2_SLOE_N,
|
| 330 |
|
|
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
|
| 331 |
|
|
IO_FX2_DATA => IO_FX2_DATA
|
| 332 |
|
|
);
|
| 333 |
|
|
end generate FX2_CNTL_IC3;
|
| 334 |
|
|
|
| 335 |
|
|
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
|
| 336 |
|
|
port map (
|
| 337 |
|
|
O_MEM_CE_N => O_MEM_CE_N,
|
| 338 |
|
|
O_MEM_BE_N => O_MEM_BE_N,
|
| 339 |
|
|
O_MEM_WE_N => O_MEM_WE_N,
|
| 340 |
|
|
O_MEM_OE_N => O_MEM_OE_N,
|
| 341 |
|
|
O_MEM_ADV_N => O_MEM_ADV_N,
|
| 342 |
|
|
O_MEM_CLK => O_MEM_CLK,
|
| 343 |
|
|
O_MEM_CRE => O_MEM_CRE,
|
| 344 |
|
|
I_MEM_WAIT => I_MEM_WAIT,
|
| 345 |
|
|
O_MEM_ADDR => O_MEM_ADDR,
|
| 346 |
|
|
IO_MEM_DATA => IO_MEM_DATA
|
| 347 |
|
|
);
|
| 348 |
|
|
|
| 349 |
|
|
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
|
| 350 |
|
|
|
| 351 |
|
|
O_TXD <= I_RXD; -- loop-back in serial port...
|
| 352 |
|
|
|
| 353 |
|
|
end syn;
|
| 354 |
|
|
|
