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-- $Id: tb_tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tb_tst_serloop - sim
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-- Description: Generic test bench for sys_tst_serloop_xx
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--
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-- Dependencies: vlib/serport/serport_uart_rxtx
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-- vlib/serport/serport_xontx
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--
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-- To test: sys_tst_serloop_xx
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--
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-- Target Devices: generic
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-13 425 1.0 Initial version
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-- 2011-11-06 420 0.5 First draft
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.serport.all;
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entity tb_tst_serloop is
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port (
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CLKS : in slbit; -- clock for serport
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CLKH : in slbit; -- clock for humanio
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CLK_STOP : out slbit; -- clock stop
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P0_RXD : out slbit; -- port 0 receive data (board view)
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P0_TXD : in slbit; -- port 0 transmit data (board view)
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P0_RTS_N : in slbit; -- port 0 rts_n
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P0_CTS_N : out slbit; -- port 0 cts_n
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P1_RXD : out slbit; -- port 1 receive data (board view)
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P1_TXD : in slbit; -- port 1 transmit data (board view)
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P1_RTS_N : in slbit; -- port 1 rts_n
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P1_CTS_N : out slbit; -- port 1 cts_n
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SWI : out slv8; -- hio switches
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BTN : out slv4 -- hio buttons
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);
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end tb_tst_serloop;
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architecture sim of tb_tst_serloop is
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signal CLK_STOP_L : slbit := '0';
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signal CLK_CYCLE : slv31 := (others=>'0');
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signal UART_RESET : slbit := '0';
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signal UART_RXD : slbit := '1';
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signal UART_TXD : slbit := '1';
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signal CTS_N : slbit := '0';
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signal RTS_N : slbit := '0';
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signal CLKDIV : slv13 := (others=>'0');
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signal RXDATA : slv8 := (others=>'0');
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signal RXVAL : slbit := '0';
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signal RXERR : slbit := '0';
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signal RXACT : slbit := '0';
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signal TXDATA : slv8 := (others=>'0');
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signal TXENA : slbit := '0';
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signal TXBUSY : slbit := '0';
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signal UART_TXDATA : slv8 := (others=>'0');
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signal UART_TXENA : slbit := '0';
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signal UART_TXBUSY : slbit := '0';
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signal ACTPORT : slbit := '0';
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signal BREAK : slbit := '0';
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signal CTS_CYCLE : integer := 0;
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signal CTS_FRACT : integer := 0;
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signal XON_CYCLE : integer := 0;
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signal XON_FRACT : integer := 0;
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signal S2M_ACTIVE : slbit := '0';
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signal S2M_SIZE : integer := 0;
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signal S2M_ENAESC : slbit := '0';
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signal S2M_ENAXON : slbit := '0';
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signal M2S_XONSEEN : slbit := '0';
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signal M2S_XOFFSEEN : slbit := '0';
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signal R_XONRXOK : slbit := '1';
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signal R_XONTXOK : slbit := '1';
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begin
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proc_cycle: process (CLKS)
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begin
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if rising_edge(CLKS) then
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CLK_CYCLE <= slv(unsigned(CLK_CYCLE) + 1);
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end if;
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end process proc_cycle;
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UART : serport_uart_rxtx
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generic map (
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CDWIDTH => 13)
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port map (
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CLK => CLKS,
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RESET => UART_RESET,
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CLKDIV => CLKDIV,
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RXSD => UART_RXD,
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RXDATA => RXDATA,
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RXVAL => RXVAL,
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RXERR => RXERR,
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RXACT => RXACT,
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TXSD => UART_TXD,
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TXDATA => UART_TXDATA,
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TXENA => UART_TXENA,
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TXBUSY => UART_TXBUSY
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);
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XONTX : serport_xontx
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port map (
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CLK => CLKS,
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RESET => UART_RESET,
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ENAXON => S2M_ENAXON,
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ENAESC => S2M_ENAESC,
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UART_TXDATA => UART_TXDATA,
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UART_TXENA => UART_TXENA,
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UART_TXBUSY => UART_TXBUSY,
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TXDATA => TXDATA,
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TXENA => TXENA,
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TXBUSY => TXBUSY,
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RXOK => R_XONRXOK,
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TXOK => R_XONTXOK
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);
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proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
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P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
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variable eff_txd : slbit := '0';
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begin
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if BREAK = '0' then -- if no break active
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eff_txd := UART_TXD; -- send uart
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else -- otherwise
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eff_txd := '0'; -- force '0'
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end if;
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if ACTPORT = '0' then -- use port 0
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P0_RXD <= eff_txd; -- write port 0 inputs
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P0_CTS_N <= CTS_N;
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UART_RXD <= P0_TXD; -- get port 0 outputs
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RTS_N <= P0_RTS_N;
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P1_RXD <= '1'; -- port 1 inputs to idle state
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P1_CTS_N <= '0';
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else -- use port 1
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P1_RXD <= eff_txd; -- write port 1 inputs
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P1_CTS_N <= CTS_N;
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UART_RXD <= P1_TXD; -- get port 1 outputs
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RTS_N <= P1_RTS_N;
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P0_RXD <= '1'; -- port 0 inputs to idle state
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P0_CTS_N <= '0';
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end if;
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end process proc_port_mux;
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proc_cts: process(CLKS)
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variable cts_timer : integer := 0;
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begin
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if rising_edge(CLKS) then
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if CTS_CYCLE = 0 then -- if cts throttle off
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CTS_N <= '0'; -- cts permanently asserted
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else -- otherwise determine throttling
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if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
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cts_timer := cts_timer - 1; -- decrement
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else
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cts_timer := CTS_CYCLE-1; -- otherwise reload
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end if;
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if cts_timer < cts_fract then -- if in lower 'fract' counts
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CTS_N <= '1'; -- throttle: deassert CTS
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else -- otherwise
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CTS_N <= '0'; -- let go: assert CTS
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end if;
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end if;
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end if;
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end process proc_cts;
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proc_xonrxok: process(CLKS)
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variable xon_timer : integer := 0;
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begin
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if rising_edge(CLKS) then
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if XON_CYCLE = 0 then -- if xon throttle off
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R_XONRXOK <= '1'; -- xonrxok permanently asserted
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else -- otherwise determine throttling
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if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
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xon_timer := xon_timer - 1; -- decrement
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else
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xon_timer := XON_CYCLE-1; -- otherwise reload
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end if;
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if xon_timer < xon_fract then -- if in lower 'fract' counts
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R_XONRXOK <= '0'; -- throttle: deassert xonrxok
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else -- otherwise
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R_XONRXOK <= '1'; -- let go: assert xonrxok
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end if;
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end if;
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end if;
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end process proc_xonrxok;
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proc_xontxok: process(CLKS)
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begin
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if rising_edge(CLKS) then
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if M2S_XONSEEN = '1' then
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R_XONTXOK <= '1';
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elsif M2S_XOFFSEEN = '1' then
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R_XONTXOK <= '0';
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end if;
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end if;
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end process proc_xontxok;
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proc_stim: process
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file fstim : text open read_mode is "tb_tst_serloop_stim";
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variable iline : line;
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variable oline : line;
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variable idelta : integer := 0;
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variable iactport : slbit := '0';
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variable iswi : slv8 := (others=>'0');
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variable btn_num : integer := 0;
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variable i_cycle : integer := 0;
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variable i_fract : integer := 0;
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variable nbyte : integer := 0;
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variable enaesc : slbit := '0';
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variable enaxon : slbit := '0';
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variable bcnt : integer := 0;
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variable itxdata : slv8 := (others=>'0');
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variable ok : boolean;
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variable dname : string(1 to 6) := (others=>' ');
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procedure waitclk(ncyc : in integer) is
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begin
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for i in 1 to ncyc loop
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wait until rising_edge(CLKS);
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end loop; -- i
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end procedure waitclk;
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begin
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-- initialize some top level out signals
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SWI <= (others=>'0');
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BTN <= (others=>'0');
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wait until rising_edge(CLKS);
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file_loop: while not endfile(fstim) loop
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readline (fstim, iline);
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readcomment(iline, ok);
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next file_loop when ok;
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readword(iline, dname, ok);
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if ok then
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case dname is
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when "wait " => -- wait
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read_ea(iline, idelta);
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writetimestamp(oline, CLK_CYCLE, ": wait ");
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write(oline, idelta, right, 5);
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writeline(output, oline);
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waitclk(idelta);
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| 286 |
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when "port " => -- switch rs232 port
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read_ea(iline, iactport);
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ACTPORT <= iactport;
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writetimestamp(oline, CLK_CYCLE, ": port ");
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write(oline, iactport, right, 5);
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writeline(output, oline);
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when "cts " => -- setup cts throttling
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read_ea(iline, i_cycle);
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read_ea(iline, i_fract);
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CTS_CYCLE <= i_cycle;
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CTS_FRACT <= i_fract;
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writetimestamp(oline, CLK_CYCLE, ": cts ");
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write(oline, i_cycle, right, 5);
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write(oline, i_fract, right, 5);
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writeline(output, oline);
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when "xon " => -- setup xon throttling
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read_ea(iline, i_cycle);
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read_ea(iline, i_fract);
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XON_CYCLE <= i_cycle;
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XON_FRACT <= i_fract;
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writetimestamp(oline, CLK_CYCLE, ": cts ");
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| 309 |
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write(oline, i_cycle, right, 5);
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| 310 |
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write(oline, i_fract, right, 5);
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writeline(output, oline);
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| 312 |
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| 313 |
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when "swi " => -- new SWI settings
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| 314 |
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read_ea(iline, iswi);
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read_ea(iline, idelta);
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| 316 |
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writetimestamp(oline, CLK_CYCLE, ": swi ");
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| 317 |
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write(oline, iswi, right, 10);
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| 318 |
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write(oline, idelta, right, 5);
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| 319 |
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writeline(output, oline);
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| 320 |
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wait until rising_edge(CLKH);
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| 321 |
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SWI <= iswi;
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| 322 |
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wait until rising_edge(CLKS);
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| 323 |
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waitclk(idelta);
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| 324 |
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| 325 |
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when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
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| 326 |
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read_ea(iline, btn_num);
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| 327 |
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read_ea(iline, idelta);
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| 328 |
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if btn_num>=0 and btn_num<=3 then
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| 329 |
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writetimestamp(oline, CLK_CYCLE, ": btn ");
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| 330 |
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write(oline, btn_num, right, 5);
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| 331 |
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write(oline, idelta, right, 5);
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| 332 |
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writeline(output, oline);
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| 333 |
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wait until rising_edge(CLKH);
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| 334 |
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BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
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| 335 |
|
|
wait until rising_edge(CLKH);
|
| 336 |
|
|
wait until rising_edge(CLKH);
|
| 337 |
|
|
wait until rising_edge(CLKH);
|
| 338 |
|
|
BTN(btn_num) <= '0';
|
| 339 |
|
|
wait until rising_edge(CLKH);
|
| 340 |
|
|
wait until rising_edge(CLKH);
|
| 341 |
|
|
wait until rising_edge(CLKH);
|
| 342 |
|
|
wait until rising_edge(CLKS);
|
| 343 |
|
|
waitclk(idelta);
|
| 344 |
|
|
else
|
| 345 |
|
|
write(oline, string'("!! btn: btn number out of range"));
|
| 346 |
|
|
writeline(output, oline);
|
| 347 |
|
|
end if;
|
| 348 |
|
|
|
| 349 |
|
|
when "expect" => -- expect n bytes data
|
| 350 |
|
|
read_ea(iline, nbyte);
|
| 351 |
|
|
read_ea(iline, enaesc);
|
| 352 |
|
|
read_ea(iline, enaxon);
|
| 353 |
|
|
writetimestamp(oline, CLK_CYCLE, ": expect");
|
| 354 |
|
|
write(oline, nbyte, right, 5);
|
| 355 |
|
|
write(oline, enaesc, right, 3);
|
| 356 |
|
|
write(oline, enaxon, right, 3);
|
| 357 |
|
|
writeline(output, oline);
|
| 358 |
|
|
|
| 359 |
|
|
if nbyte > 0 then
|
| 360 |
|
|
S2M_ACTIVE <= '1';
|
| 361 |
|
|
S2M_SIZE <= nbyte;
|
| 362 |
|
|
else
|
| 363 |
|
|
S2M_ACTIVE <= '0';
|
| 364 |
|
|
end if;
|
| 365 |
|
|
S2M_ENAESC <= enaesc;
|
| 366 |
|
|
S2M_ENAXON <= enaxon;
|
| 367 |
|
|
wait until rising_edge(CLKS);
|
| 368 |
|
|
|
| 369 |
|
|
when "send " => -- send n bytes data
|
| 370 |
|
|
read_ea(iline, nbyte);
|
| 371 |
|
|
read_ea(iline, enaesc);
|
| 372 |
|
|
read_ea(iline, enaxon);
|
| 373 |
|
|
writetimestamp(oline, CLK_CYCLE, ": send ");
|
| 374 |
|
|
write(oline, nbyte, right, 5);
|
| 375 |
|
|
write(oline, enaesc, right, 3);
|
| 376 |
|
|
write(oline, enaxon, right, 3);
|
| 377 |
|
|
writeline(output, oline);
|
| 378 |
|
|
bcnt := 0;
|
| 379 |
|
|
itxdata := (others=>'0');
|
| 380 |
|
|
|
| 381 |
|
|
wait until falling_edge(CLKS);
|
| 382 |
|
|
while bcnt < nbyte loop
|
| 383 |
|
|
while TXBUSY='1' or RTS_N='1' loop
|
| 384 |
|
|
wait until falling_edge(CLKS);
|
| 385 |
|
|
end loop;
|
| 386 |
|
|
|
| 387 |
|
|
TXDATA <= itxdata;
|
| 388 |
|
|
itxdata := slv(unsigned(itxdata) + 1);
|
| 389 |
|
|
bcnt := bcnt + 1;
|
| 390 |
|
|
|
| 391 |
|
|
TXENA <= '1';
|
| 392 |
|
|
wait until falling_edge(CLKS);
|
| 393 |
|
|
TXENA <= '0';
|
| 394 |
|
|
wait until falling_edge(CLKS);
|
| 395 |
|
|
end loop;
|
| 396 |
|
|
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
|
| 397 |
|
|
wait until falling_edge(CLKS);
|
| 398 |
|
|
end loop;
|
| 399 |
|
|
wait until rising_edge(CLKS);
|
| 400 |
|
|
|
| 401 |
|
|
when "break " => -- send a break for n cycles
|
| 402 |
|
|
read_ea(iline, idelta);
|
| 403 |
|
|
writetimestamp(oline, CLK_CYCLE, ": break ");
|
| 404 |
|
|
write(oline, idelta, right, 5);
|
| 405 |
|
|
writeline(output, oline);
|
| 406 |
|
|
-- send break for n cycles
|
| 407 |
|
|
BREAK <= '1';
|
| 408 |
|
|
waitclk(idelta);
|
| 409 |
|
|
BREAK <= '0';
|
| 410 |
|
|
-- wait for 3 bit cell width
|
| 411 |
|
|
waitclk(3*to_integer(unsigned(CLKDIV)+1));
|
| 412 |
|
|
-- send 'sync' character
|
| 413 |
|
|
wait until falling_edge(CLKS);
|
| 414 |
|
|
TXDATA <= "10000000";
|
| 415 |
|
|
TXENA <= '1';
|
| 416 |
|
|
wait until falling_edge(CLKS);
|
| 417 |
|
|
TXENA <= '0';
|
| 418 |
|
|
wait until rising_edge(CLKS);
|
| 419 |
|
|
|
| 420 |
|
|
when "clkdiv" => -- set new clock divider
|
| 421 |
|
|
read_ea(iline, idelta);
|
| 422 |
|
|
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
|
| 423 |
|
|
write(oline, idelta, right, 5);
|
| 424 |
|
|
writeline(output, oline);
|
| 425 |
|
|
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
|
| 426 |
|
|
UART_RESET <= '1';
|
| 427 |
|
|
wait until rising_edge(CLKS);
|
| 428 |
|
|
UART_RESET <= '0';
|
| 429 |
|
|
|
| 430 |
|
|
when others => -- unknown command
|
| 431 |
|
|
write(oline, string'("?? unknown command: "));
|
| 432 |
|
|
write(oline, dname);
|
| 433 |
|
|
writeline(output, oline);
|
| 434 |
|
|
report "aborting" severity failure;
|
| 435 |
|
|
end case;
|
| 436 |
|
|
|
| 437 |
|
|
else
|
| 438 |
|
|
report "failed to find command" severity failure;
|
| 439 |
|
|
|
| 440 |
|
|
end if;
|
| 441 |
|
|
|
| 442 |
|
|
testempty_ea(iline);
|
| 443 |
|
|
end loop; -- file_loop
|
| 444 |
|
|
|
| 445 |
|
|
writetimestamp(oline, CLK_CYCLE, ": DONE ");
|
| 446 |
|
|
writeline(output, oline);
|
| 447 |
|
|
|
| 448 |
|
|
-- extra wait for at least two character times (20 bit times)
|
| 449 |
|
|
-- to allow tx and rx of the last character
|
| 450 |
|
|
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
|
| 451 |
|
|
|
| 452 |
|
|
CLK_STOP_L <= '1';
|
| 453 |
|
|
|
| 454 |
|
|
wait for 500 ns; -- allows dcm's to stop
|
| 455 |
|
|
|
| 456 |
|
|
wait; -- suspend proc_stim forever
|
| 457 |
|
|
-- clock is stopped, sim will end
|
| 458 |
|
|
|
| 459 |
|
|
end process proc_stim;
|
| 460 |
|
|
|
| 461 |
|
|
CLK_STOP <= CLK_STOP_L;
|
| 462 |
|
|
|
| 463 |
|
|
proc_moni: process
|
| 464 |
|
|
variable oline : line;
|
| 465 |
|
|
variable dclk : integer := 0;
|
| 466 |
|
|
variable active_1 : slbit := '0';
|
| 467 |
|
|
variable irxdata : slv8 := (others=>'0');
|
| 468 |
|
|
variable irxeff : slv8 := (others=>'0');
|
| 469 |
|
|
variable irxval : slbit := '0';
|
| 470 |
|
|
variable doesc : slbit := '0';
|
| 471 |
|
|
variable bcnt : integer := 0;
|
| 472 |
|
|
variable xseen : slbit := '0';
|
| 473 |
|
|
begin
|
| 474 |
|
|
|
| 475 |
|
|
loop
|
| 476 |
|
|
wait until falling_edge(CLKS);
|
| 477 |
|
|
|
| 478 |
|
|
M2S_XONSEEN <= '0';
|
| 479 |
|
|
M2S_XOFFSEEN <= '0';
|
| 480 |
|
|
|
| 481 |
|
|
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
|
| 482 |
|
|
irxdata := (others=>'0');
|
| 483 |
|
|
bcnt := 0;
|
| 484 |
|
|
end if;
|
| 485 |
|
|
|
| 486 |
|
|
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
|
| 487 |
|
|
if bcnt = S2M_SIZE then
|
| 488 |
|
|
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
|
| 489 |
|
|
else
|
| 490 |
|
|
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
|
| 491 |
|
|
write(oline, bcnt, right, 5);
|
| 492 |
|
|
write(oline, string'(" expect="));
|
| 493 |
|
|
write(oline, S2M_SIZE, right, 5);
|
| 494 |
|
|
end if;
|
| 495 |
|
|
writeline(output, oline);
|
| 496 |
|
|
end if;
|
| 497 |
|
|
|
| 498 |
|
|
active_1 := S2M_ACTIVE;
|
| 499 |
|
|
|
| 500 |
|
|
if RXVAL = '1' then
|
| 501 |
|
|
writetimestamp(oline, CLK_CYCLE, ": char: ");
|
| 502 |
|
|
write(oline, RXDATA, right, 10);
|
| 503 |
|
|
write(oline, string'(" ("));
|
| 504 |
|
|
writeoct(oline, RXDATA, right, 3);
|
| 505 |
|
|
write(oline, string'(") dt="));
|
| 506 |
|
|
write(oline, dclk, right, 4);
|
| 507 |
|
|
|
| 508 |
|
|
irxeff := RXDATA;
|
| 509 |
|
|
irxval := '1';
|
| 510 |
|
|
if doesc = '1' then
|
| 511 |
|
|
irxeff := not RXDATA;
|
| 512 |
|
|
irxval := '1';
|
| 513 |
|
|
doesc := '0';
|
| 514 |
|
|
write(oline, string'(" eff="));
|
| 515 |
|
|
write(oline, irxeff, right, 10);
|
| 516 |
|
|
write(oline, string'(" ("));
|
| 517 |
|
|
writeoct(oline, irxeff, right, 3);
|
| 518 |
|
|
write(oline, string'(")"));
|
| 519 |
|
|
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
|
| 520 |
|
|
doesc := '1';
|
| 521 |
|
|
irxval := '0';
|
| 522 |
|
|
write(oline, string'(" XESC seen"));
|
| 523 |
|
|
end if;
|
| 524 |
|
|
|
| 525 |
|
|
xseen := '0';
|
| 526 |
|
|
if S2M_ENAXON = '1' then
|
| 527 |
|
|
if RXDATA = c_serport_xon then
|
| 528 |
|
|
write(oline, string'(" XON seen"));
|
| 529 |
|
|
M2S_XONSEEN <= '1';
|
| 530 |
|
|
xseen := '1';
|
| 531 |
|
|
elsif RXDATA = c_serport_xoff then
|
| 532 |
|
|
write(oline, string'(" XOFF seen"));
|
| 533 |
|
|
M2S_XOFFSEEN <= '1';
|
| 534 |
|
|
xseen := '1';
|
| 535 |
|
|
end if;
|
| 536 |
|
|
end if;
|
| 537 |
|
|
|
| 538 |
|
|
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
|
| 539 |
|
|
if irxeff = irxdata then
|
| 540 |
|
|
write(oline, string'(" OK"));
|
| 541 |
|
|
else
|
| 542 |
|
|
write(oline, string'(" FAIL: expect="));
|
| 543 |
|
|
write(oline, irxdata, right, 10);
|
| 544 |
|
|
end if;
|
| 545 |
|
|
irxdata := slv(unsigned(irxdata) + 1);
|
| 546 |
|
|
bcnt := bcnt + 1;
|
| 547 |
|
|
end if;
|
| 548 |
|
|
|
| 549 |
|
|
writeline(output, oline);
|
| 550 |
|
|
dclk := 0;
|
| 551 |
|
|
|
| 552 |
|
|
end if;
|
| 553 |
|
|
|
| 554 |
|
|
if RXERR = '1' then
|
| 555 |
|
|
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
|
| 556 |
|
|
writeline(output, oline);
|
| 557 |
|
|
end if;
|
| 558 |
|
|
|
| 559 |
|
|
dclk := dclk + 1;
|
| 560 |
|
|
|
| 561 |
|
|
end loop;
|
| 562 |
|
|
|
| 563 |
|
|
end process proc_moni;
|
| 564 |
|
|
|
| 565 |
|
|
end sim;
|
