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-- $Id: sys_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name:    sys_w11a_n2 - syn
-- Description:    w11a test design for nexys2
--
-- Dependencies:   vlib/genlib/clkdivce
--                 bplib/s3board/s3_rs232_iob_int_ext
--                 bplib/s3board/s3_humanio_rri
--                 vlib/rri/rri_core_serport
--                 vlib/rri/rb_sres_or_3
--                 w11a/pdp11_core_rri
--                 w11a/pdp11_core
--                 w11a/pdp11_bram
--                 vlib/nexys2/n2_cram_dummy
--                 w11a/pdp11_cache
--                 w11a/pdp11_mem70
--                 bplib/nexys2/n2_cram_memctl
--                 ibus/ib_sres_or_2
--                 ibus/ibdr_minisys
--                 ibus/ibdr_maxisys
--                 w11a/pdp11_tmu_sb           [sim only]
--
-- Test bench:     tb/tb_s3board_w11a_n2
--
-- Target Devices: generic
-- Tool versions:  xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26 - 0.29
--
-- Synthesized (xst):
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
-- 2010-06-27   310 12.1    M53d xc3s1200e-4 1337 4307  242 2630 ok: LP+PC+DL+I
-- 2010-06-26   309 11.4    L68  xc3s1200e-4 1318 4293  242 2612 ok: LP+PC+DL+II
-- 2010-06-18   306 12.1    M53d xc3s1200e-4 1319 4300  242 2624 ok: LP+PC+DL+II
-- "            306 11.4    L68  xc3s1200e-4 1319 4286  242 2618 ok: LP+PC+DL+II
-- "            306 10.1.02 K39  xc3s1200e-4 1309 4311  242 2665 ok: LP+PC+DL+II
-- "            306  9.2.02 J40  xc3s1200e-4 1316 4259  242 2656 ok: LP+PC+DL+II
-- "            306  9.1    J30  xc3s1200e-4 1311 4260  242 2643 ok: LP+PC+DL+II
-- "            306  8.2.03 I34  xc3s1200e-4 1371 4394  242 2765 ok: LP+PC+DL+II
-- 2010-06-13   305 11.4    L68  xc3s1200e-4 1318 4360  242 2629 ok: LP+PC+DL+II
-- 2010-06-12   304 11.4    L68  xc3s1200e-4 1323 4201  242 2574 ok: LP+PC+DL+II
-- 2010-06-03   300 11.4    L68  xc3s1200e-4 1318 4181  242 2572 ok: LP+PC+DL+II
-- 2010-06-03   299 11.4    L68  xc3s1200e-4 1250 4071  224 2489 ok: LP+PC+DL+II
-- 2010-05-26   296 11.4    L68  xc3s1200e-4 1284 4079  224 2492 ok: LP+PC+DL+II
--
-- Revision History: 
-- Date         Rev Version  Comment
-- 2010-06-26   309   1.1.4  use constants for rbus addresses (rbaddr_...)
--                           BUGFIX: resolve rbus address clash hio<->ibr
-- 2010-06-18   306   1.1.3  change proc_led sensitivity list to avoid xst warn;
--                           rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
--                           remove pdp11_ibdr_rri
-- 2010-06-13   305   1.1.2  add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-12   304   1.1.1  re-do LED driver logic (show cpu modes or cpurust)
-- 2010-06-11   303   1.1    use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03   300   1.0.2  use default FAWIDTH for rri_core_serport
--                           use s3_humanio_rri
-- 2010-05-30   297   1.0.1  put MEM_ACT_(R|W) on LED 6,7
-- 2010-05-28   295   1.0    Initial version (derived from sys_w11a_s3)
------------------------------------------------------------------------------
--
-- w11a test design for nexys2
--    w11a + rri + serport
--
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
--    SWI(0):   0 -> main board RS232 port
--              1 -> Pmod B/top RS232 port
--    
--    LED(0:4): if cpugo=1 show cpu mode activity
--                  (0) user mode
--                  (1) supervisor mode
--                  (2) kernel mode, wait
--                  (3) kernel mode, pri=0
--                  (4) kernel mode, pri>0
--              if cpugo=0 shows cpurust
--                (3:0) cpurust code
--                  (4) '1'
--         (5)  cmdbusy (all rri access, mostly rdma)
--         (6)  MEM_ACT_R
--         (7)  MEM_ACT_W
--
--    DP(0):    RXSD   (inverted to signal activity)
--    DP(1):    RTS_N  (shows rx back preasure)
--    DP(2):    TXSD   (inverted to signal activity)
--    DP(3):    CTS_N  (shows tx back preasure)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.rrilib.all;
use work.s3boardlib.all;
use work.nexys2lib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_w11a_n2 is                   -- top level
                                        -- implements nexys2_fusp_aif
  port (
    CLK : in slbit;                     -- clock
    I_RXD : in slbit;                   -- receive data (board view)
    O_TXD : out slbit;                  -- transmit data (board view)
    I_SWI : in slv8;                    -- s3 switches
    I_BTN : in slv4;                    -- s3 buttons
    O_LED : out slv8;                   -- s3 leds
    O_ANO_N : out slv4;                 -- 7 segment disp: anodes   (act.low)
    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)
    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)
    O_MEM_CLK : out slbit;              -- cram: clock
    O_MEM_CRE : out slbit;              -- cram: command register enable
    I_MEM_WAIT : in slbit;              -- cram: mem wait
    O_FLA_CE_N : out slbit;             -- flash ce..          (act.low)
    O_MEM_ADDR  : out slv23;            -- cram: address lines
    IO_MEM_DATA : inout slv16;          -- cram: data lines
    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n
    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n
    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx
    O_FUSP_TXD : out slbit              -- fusp: rs232 tx
  );
end sys_w11a_n2;
 
architecture syn of sys_w11a_n2 is
 
  signal RXD :   slbit := '1';
  signal TXD :   slbit := '0';
  signal RTS_N : slbit := '0';
  signal CTS_N : slbit := '0';
 
  signal SWI     : slv8  := (others=>'0');
  signal BTN     : slv4  := (others=>'0');
  signal LED     : slv8  := (others=>'0');
  signal DSP_DAT : slv16 := (others=>'0');
  signal DSP_DP  : slv4  := (others=>'0');
 
  signal RB_LAM  : slv16 := (others=>'0');
  signal RB_STAT : slv3  := (others=>'0');
 
  signal RB_MREQ     : rb_mreq_type := rb_mreq_init;
  signal RB_SRES     : rb_sres_type := rb_sres_init;
  signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
  signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
  signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
 
  signal RESET   : slbit := '0';
  signal CE_USEC : slbit := '0';
  signal CE_MSEC : slbit := '0';
 
  signal CPU_RESET : slbit := '0';
  signal CP_CNTL : cp_cntl_type := cp_cntl_init;
  signal CP_ADDR : cp_addr_type := cp_addr_init;
  signal CP_DIN  : slv16 := (others=>'0');
  signal CP_STAT : cp_stat_type := cp_stat_init;
  signal CP_DOUT : slv16 := (others=>'0');
 
  signal EI_PRI  : slv3   := (others=>'0');
  signal EI_VECT : slv9_2 := (others=>'0');
  signal EI_ACKM : slbit  := '0';
 
  signal EM_MREQ : em_mreq_type := em_mreq_init;
  signal EM_SRES : em_sres_type := em_sres_init;
 
  signal HM_ENA      : slbit := '0';
  signal MEM70_FMISS : slbit := '0';
  signal CACHE_FMISS : slbit := '0';
  signal CACHE_CHIT  : slbit := '0';
 
  signal MEM_REQ   : slbit := '0';
  signal MEM_WE    : slbit := '0';
  signal MEM_BUSY  : slbit := '0';
  signal MEM_ACK_R : slbit := '0';
  signal MEM_ACT_R : slbit := '0';
  signal MEM_ACT_W : slbit := '0';
  signal MEM_ADDR  : slv20 := (others=>'0');
  signal MEM_BE    : slv4  := (others=>'0');
  signal MEM_DI    : slv32 := (others=>'0');
  signal MEM_DO    : slv32 := (others=>'0');
 
  signal MEM_ADDR_EXT : slv22 := (others=>'0');
 
  signal BRESET  : slbit := '0';
  signal IB_MREQ : ib_mreq_type := ib_mreq_init;
  signal IB_SRES : ib_sres_type := ib_sres_init;
 
  signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
  signal IB_SRES_IBDR  : ib_sres_type := ib_sres_init;
 
  signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
  signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
  signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
  signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
 
  signal DISPREG : slv16 := (others=>'0');
 
  constant rbaddr_core0 : slv8 := "00000000";
  constant rbaddr_ibus  : slv8 := "10000000";
  constant rbaddr_hio   : slv8 := "11000000";
 
begin
 
  CLKDIV : clkdivce
    generic map (
      CDUWIDTH => 6,
      USECDIV  => 50,
      MSECDIV  => 1000)
    port map (
      CLK     => CLK,
      CE_USEC => CE_USEC,
      CE_MSEC => CE_MSEC
    );
 
  IOB_RS232 : s3_rs232_iob_int_ext
    port map (
      CLK      => CLK,
      SEL      => SWI(0),
      RXD      => RXD,
      TXD      => TXD,
      CTS_N    => CTS_N,
      RTS_N    => RTS_N,
      I_RXD0   => I_RXD,
      O_TXD0   => O_TXD,
      I_RXD1   => I_FUSP_RXD,
      O_TXD1   => O_FUSP_TXD,
      I_CTS1_N => I_FUSP_CTS_N,
      O_RTS1_N => O_FUSP_RTS_N
    );
 
  HIO : s3_humanio_rri
    generic map (
      DEBOUNCE => sys_conf_hio_debounce,
      RB_ADDR  => rbaddr_hio)
    port map (
      CLK     => CLK,
      RESET   => RESET,
      CE_MSEC => CE_MSEC,
      RB_MREQ => RB_MREQ,
      RB_SRES => RB_SRES_HIO,
      SWI     => SWI,
      BTN     => BTN,
      LED     => LED,
      DSP_DAT => DSP_DAT,
      DSP_DP  => DSP_DP,
      I_SWI   => I_SWI,
      I_BTN   => I_BTN,
      O_LED   => O_LED,
      O_ANO_N => O_ANO_N,
      O_SEG_N => O_SEG_N
    );
 
  RRI : rri_core_serport
    generic map (
      ATOWIDTH =>  6,                   -- 64 cycles access timeout
      ITOWIDTH =>  6,                   -- 64 periods max idle timeout
      CDWIDTH  => 13,
      CDINIT   => sys_conf_ser2rri_cdinit)
    port map (
      CLK      => CLK,
      CE_USEC  => CE_USEC,
      CE_MSEC  => CE_MSEC,
      CE_INT   => CE_MSEC,
      RESET    => RESET,
      RXSD     => RXD,
      TXSD     => TXD,
      CTS_N    => CTS_N,
      RTS_N    => RTS_N,
      RB_MREQ  => RB_MREQ,
      RB_SRES  => RB_SRES,
      RB_LAM   => RB_LAM,
      RB_STAT  => RB_STAT
    );
 
  RB_SRES_OR : rb_sres_or_3
    port map (
      RB_SRES_1  => RB_SRES_CPU,
      RB_SRES_2  => RB_SRES_IBD,
      RB_SRES_3  => RB_SRES_HIO,
      RB_SRES_OR => RB_SRES
    );
 
  RB2CP : pdp11_core_rri
    generic map (
      RB_ADDR_CORE => rbaddr_core0,
      RB_ADDR_IBUS => rbaddr_ibus)
    port map (
      CLK       => CLK,
      RESET     => RESET,
      RB_MREQ   => RB_MREQ,
      RB_SRES   => RB_SRES_CPU,
      RB_STAT   => RB_STAT,
      RRI_LAM   => RB_LAM(0),
      CPU_RESET => CPU_RESET,
      CP_CNTL   => CP_CNTL,
      CP_ADDR   => CP_ADDR,
      CP_DIN    => CP_DIN,
      CP_STAT   => CP_STAT,
      CP_DOUT   => CP_DOUT
    );
 
  CORE : pdp11_core
    port map (
      CLK       => CLK,
      RESET     => CPU_RESET,
      CP_CNTL   => CP_CNTL,
      CP_ADDR   => CP_ADDR,
      CP_DIN    => CP_DIN,
      CP_STAT   => CP_STAT,
      CP_DOUT   => CP_DOUT,
      EI_PRI    => EI_PRI,
      EI_VECT   => EI_VECT,
      EI_ACKM   => EI_ACKM,
      EM_MREQ   => EM_MREQ,
      EM_SRES   => EM_SRES,
      BRESET    => BRESET,
      IB_MREQ_M => IB_MREQ,
      IB_SRES_M => IB_SRES,
      DM_STAT_DP => DM_STAT_DP,
      DM_STAT_VM => DM_STAT_VM,
      DM_STAT_CO => DM_STAT_CO
    );
 
  MEM_BRAM: if sys_conf_bram > 0 generate
    signal HM_VAL_BRAM : slbit := '0';
  begin
 
    MEM : pdp11_bram
      generic map (
        AWIDTH => sys_conf_bram_awidth)
      port map (
        CLK     => CLK,
        GRESET  => CPU_RESET,
        EM_MREQ => EM_MREQ,
        EM_SRES => EM_SRES
      );
 
    HM_VAL_BRAM <= not EM_MREQ.we;        -- assume hit if read, miss if write
 
    MEM70: pdp11_mem70
      port map (
        CLK         => CLK,
        CRESET      => BRESET,
        HM_ENA      => EM_MREQ.req,
        HM_VAL      => HM_VAL_BRAM,
        CACHE_FMISS => MEM70_FMISS,
        IB_MREQ     => IB_MREQ,
        IB_SRES     => IB_SRES_MEM70
      );
 
    SRAM_PROT : n2_cram_dummy            -- connect CRAM to protection dummy
      port map (
        O_MEM_CE_N  => O_MEM_CE_N,
        O_MEM_BE_N  => O_MEM_BE_N,
        O_MEM_WE_N  => O_MEM_WE_N,
        O_MEM_OE_N  => O_MEM_OE_N,
        O_MEM_ADV_N => O_MEM_ADV_N,
        O_MEM_CLK   => O_MEM_CLK,
        O_MEM_CRE   => O_MEM_CRE,
        I_MEM_WAIT  => I_MEM_WAIT,
        O_FLA_CE_N  => O_FLA_CE_N,
        O_MEM_ADDR  => O_MEM_ADDR,
        IO_MEM_DATA => IO_MEM_DATA
      );
 
  end generate MEM_BRAM;
 
  MEM_SRAM: if sys_conf_bram = 0 generate
 
    CACHE: pdp11_cache
      port map (
        CLK       => CLK,
        GRESET    => CPU_RESET,
        EM_MREQ   => EM_MREQ,
        EM_SRES   => EM_SRES,
        FMISS     => CACHE_FMISS,
        CHIT      => CACHE_CHIT,
        MEM_REQ   => MEM_REQ,
        MEM_WE    => MEM_WE,
        MEM_BUSY  => MEM_BUSY,
        MEM_ACK_R => MEM_ACK_R,
        MEM_ADDR  => MEM_ADDR,
        MEM_BE    => MEM_BE,
        MEM_DI    => MEM_DI,
        MEM_DO    => MEM_DO
      );
 
    MEM70: pdp11_mem70
      port map (
        CLK         => CLK,
        CRESET      => BRESET,
        HM_ENA      => HM_ENA,
        HM_VAL      => CACHE_CHIT,
        CACHE_FMISS => MEM70_FMISS,
        IB_MREQ     => IB_MREQ,
        IB_SRES     => IB_SRES_MEM70
      );
 
    HM_ENA      <= EM_SRES.ack_r or EM_SRES.ack_w;
    CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
 
    MEM_ADDR_EXT <= "00" & MEM_ADDR;    -- just use lower 4 MB (of 16 MB)
 
    SRAM_CTL: n2_cram_memctl_as
      generic map (
        READ0DELAY => 2,
        READ1DELAY => 2,
        WRITEDELAY => 3)
      port map (
        CLK         => CLK,
        RESET       => CPU_RESET,
        REQ         => MEM_REQ,
        WE          => MEM_WE,
        BUSY        => MEM_BUSY,
        ACK_R       => MEM_ACK_R,
        ACK_W       => open,
        ACT_R       => MEM_ACT_R,
        ACT_W       => MEM_ACT_W,
        ADDR        => MEM_ADDR_EXT,
        BE          => MEM_BE,
        DI          => MEM_DI,
        DO          => MEM_DO,
        O_MEM_CE_N  => O_MEM_CE_N,
        O_MEM_BE_N  => O_MEM_BE_N,
        O_MEM_WE_N  => O_MEM_WE_N,
        O_MEM_OE_N  => O_MEM_OE_N,
        O_MEM_ADV_N => O_MEM_ADV_N,
        O_MEM_CLK   => O_MEM_CLK,
        O_MEM_CRE   => O_MEM_CRE,
        I_MEM_WAIT  => I_MEM_WAIT,
        O_FLA_CE_N  => O_FLA_CE_N,
        O_MEM_ADDR  => O_MEM_ADDR,
        IO_MEM_DATA => IO_MEM_DATA
      );
 
  end generate MEM_SRAM;
 
  IB_SRES_OR : ib_sres_or_2
    port map (
      IB_SRES_1  => IB_SRES_MEM70,
      IB_SRES_2  => IB_SRES_IBDR,
      IB_SRES_OR => IB_SRES
    );
 
  IBD_MINI : if false generate
  begin
    IBDR_SYS : ibdr_minisys
      port map (
        CLK      => CLK,
        CE_USEC  => CE_USEC,
        CE_MSEC  => CE_MSEC,
        RESET    => CPU_RESET,
        BRESET   => BRESET,
        RRI_LAM  => RB_LAM(15 downto 1),
        IB_MREQ  => IB_MREQ,
        IB_SRES  => IB_SRES_IBDR,
        EI_ACKM  => EI_ACKM,
        EI_PRI   => EI_PRI,
        EI_VECT  => EI_VECT,
        DISPREG  => DISPREG
      );
  end generate IBD_MINI;
 
  IBD_MAXI : if true generate
  begin
    IBDR_SYS : ibdr_maxisys
      port map (
        CLK      => CLK,
        CE_USEC  => CE_USEC,
        CE_MSEC  => CE_MSEC,
        RESET    => CPU_RESET,
        BRESET   => BRESET,
        RRI_LAM  => RB_LAM(15 downto 1),
        IB_MREQ  => IB_MREQ,
        IB_SRES  => IB_SRES_IBDR,
        EI_ACKM  => EI_ACKM,
        EI_PRI   => EI_PRI,
        EI_VECT  => EI_VECT,
        DISPREG  => DISPREG
      );
  end generate IBD_MAXI;
 
  DSP_DAT(15 downto 0) <= DISPREG;
  DSP_DP(0) <= not RXD;
  DSP_DP(1) <= RTS_N;
  DSP_DP(2) <= not TXD;
  DSP_DP(3) <= CTS_N;
 
  proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
    variable iled : slv8 := (others=>'0');
  begin
    iled := (others=>'0');
    iled(7) := MEM_ACT_W;
    iled(6) := MEM_ACT_R;
    iled(5) := CP_STAT.cmdbusy;
    if CP_STAT.cpugo = '1' then
      case DM_STAT_DP.psw.cmode is
        when c_psw_kmode =>
          if CP_STAT.cpuwait = '1' then
            iled(2) := '1';
          elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
            iled(3) := '1';
          else
            iled(4) := '1';
          end if;
        when c_psw_smode =>
          iled(1) := '1';
        when c_psw_umode =>
          iled(0) := '1';
        when others => null;
      end case;
    else
      iled(4) := '1';
      iled(3 downto 0) := CP_STAT.cpurust;
    end if;
    LED <= iled;
  end process;
 
-- synthesis translate_off
  DM_STAT_SY.emmreq <= EM_MREQ;
  DM_STAT_SY.emsres <= EM_SRES;
  DM_STAT_SY.chit   <= CACHE_CHIT;
 
  TMU : pdp11_tmu_sb
    generic map (
      ENAPIN => 13)
    port map (
      CLK        => CLK,
      DM_STAT_DP => DM_STAT_DP,
      DM_STAT_VM => DM_STAT_VM,
      DM_STAT_CO => DM_STAT_CO,
      DM_STAT_SY => DM_STAT_SY
    );
 
-- synthesis translate_on
end syn;

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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [sys_gen/] [w11a/] [nexys2/] [sys_w11a_n2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	wfjm	`-- $Id: sys_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $`
2			`--`
3			`-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Module Name: sys_w11a_n2 - syn`
16			`-- Description: w11a test design for nexys2`
17			`--`
18			`-- Dependencies: vlib/genlib/clkdivce`
19			`-- bplib/s3board/s3_rs232_iob_int_ext`
20			`-- bplib/s3board/s3_humanio_rri`
21			`-- vlib/rri/rri_core_serport`
22			`-- vlib/rri/rb_sres_or_3`
23			`-- w11a/pdp11_core_rri`
24			`-- w11a/pdp11_core`
25			`-- w11a/pdp11_bram`
26			`-- vlib/nexys2/n2_cram_dummy`
27			`-- w11a/pdp11_cache`
28			`-- w11a/pdp11_mem70`
29			`-- bplib/nexys2/n2_cram_memctl`
30			`-- ibus/ib_sres_or_2`
31			`-- ibus/ibdr_minisys`
32			`-- ibus/ibdr_maxisys`
33			`-- w11a/pdp11_tmu_sb [sim only]`
34			`--`
35			`-- Test bench: tb/tb_s3board_w11a_n2`
36			`--`
37			`-- Target Devices: generic`
38			`-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26 - 0.29`
39			`--`
40			`-- Synthesized (xst):`
41			`-- Date Rev ise Target flop lutl lutm slic t peri`
42			`-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+I`
43			`-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II`
44			`-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II`
45			`-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II`
46			`-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II`
47			`-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II`
48			`-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II`
49			`-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II`
50			`-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II`
51			`-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II`
52			`-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II`
53			`-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II`
54			`-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II`
55			`--`
56			`-- Revision History:`
57			`-- Date Rev Version Comment`
58			`-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)`
59			`-- BUGFIX: resolve rbus address clash hio<->ibr`
60			`-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;`
61			`-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;`
62			`-- remove pdp11_ibdr_rri`
63			`-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core`
64			`-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust)`
65			`-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ`
66			`-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport`
67			`-- use s3_humanio_rri`
68			`-- 2010-05-30 297 1.0.1 put MEM_ACT_(R\|W) on LED 6,7`
69			`-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)`
70			`------------------------------------------------------------------------------`
71			`--`
72			`-- w11a test design for nexys2`
73			`-- w11a + rri + serport`
74			`--`
75			`-- Usage of Nexys 2 Switches, Buttons, LEDs:`
76			`--`
77			`-- SWI(0): 0 -> main board RS232 port`
78			`-- 1 -> Pmod B/top RS232 port`
79			`--`
80			`-- LED(0:4): if cpugo=1 show cpu mode activity`
81			`-- (0) user mode`
82			`-- (1) supervisor mode`
83			`-- (2) kernel mode, wait`
84			`-- (3) kernel mode, pri=0`
85			`-- (4) kernel mode, pri>0`
86			`-- if cpugo=0 shows cpurust`
87			`-- (3:0) cpurust code`
88			`-- (4) '1'`
89			`-- (5) cmdbusy (all rri access, mostly rdma)`
90			`-- (6) MEM_ACT_R`
91			`-- (7) MEM_ACT_W`
92			`--`
93			`-- DP(0): RXSD (inverted to signal activity)`
94			`-- DP(1): RTS_N (shows rx back preasure)`
95			`-- DP(2): TXSD (inverted to signal activity)`
96			`-- DP(3): CTS_N (shows tx back preasure)`
97
98			`library ieee;`
99			`use ieee.std_logic_1164.all;`
100			`use ieee.std_logic_arith.all;`
101
102			`use work.slvtypes.all;`
103			`use work.genlib.all;`
104			`use work.rrilib.all;`
105			`use work.s3boardlib.all;`
106			`use work.nexys2lib.all;`
107			`use work.iblib.all;`
108			`use work.ibdlib.all;`
109			`use work.pdp11.all;`
110			`use work.sys_conf.all;`
111
112			`-- ----------------------------------------------------------------------------`
113
114			`entity sys_w11a_n2 is -- top level`
115			`-- implements nexys2_fusp_aif`
116			`port (`
117			`CLK : in slbit; -- clock`
118			`I_RXD : in slbit; -- receive data (board view)`
119			`O_TXD : out slbit; -- transmit data (board view)`
120			`I_SWI : in slv8; -- s3 switches`
121			`I_BTN : in slv4; -- s3 buttons`
122			`O_LED : out slv8; -- s3 leds`
123			`O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)`
124			`O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)`
125			`O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)`
126			`O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)`
127			`O_MEM_WE_N : out slbit; -- cram: write enable (act.low)`
128			`O_MEM_OE_N : out slbit; -- cram: output enable (act.low)`
129			`O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)`
130			`O_MEM_CLK : out slbit; -- cram: clock`
131			`O_MEM_CRE : out slbit; -- cram: command register enable`
132			`I_MEM_WAIT : in slbit; -- cram: mem wait`
133			`O_FLA_CE_N : out slbit; -- flash ce.. (act.low)`
134			`O_MEM_ADDR : out slv23; -- cram: address lines`
135			`IO_MEM_DATA : inout slv16; -- cram: data lines`
136			`O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n`
137			`I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n`
138			`I_FUSP_RXD : in slbit; -- fusp: rs232 rx`
139			`O_FUSP_TXD : out slbit -- fusp: rs232 tx`
140			`);`
141			`end sys_w11a_n2;`
142
143			`architecture syn of sys_w11a_n2 is`
144
145			`signal RXD : slbit := '1';`
146			`signal TXD : slbit := '0';`
147			`signal RTS_N : slbit := '0';`
148			`signal CTS_N : slbit := '0';`
149
150			`signal SWI : slv8 := (others=>'0');`
151			`signal BTN : slv4 := (others=>'0');`
152			`signal LED : slv8 := (others=>'0');`
153			`signal DSP_DAT : slv16 := (others=>'0');`
154			`signal DSP_DP : slv4 := (others=>'0');`
155
156			`signal RB_LAM : slv16 := (others=>'0');`
157			`signal RB_STAT : slv3 := (others=>'0');`
158
159			`signal RB_MREQ : rb_mreq_type := rb_mreq_init;`
160			`signal RB_SRES : rb_sres_type := rb_sres_init;`
161			`signal RB_SRES_CPU : rb_sres_type := rb_sres_init;`
162			`signal RB_SRES_IBD : rb_sres_type := rb_sres_init;`
163			`signal RB_SRES_HIO : rb_sres_type := rb_sres_init;`
164
165			`signal RESET : slbit := '0';`
166			`signal CE_USEC : slbit := '0';`
167			`signal CE_MSEC : slbit := '0';`
168
169			`signal CPU_RESET : slbit := '0';`
170			`signal CP_CNTL : cp_cntl_type := cp_cntl_init;`
171			`signal CP_ADDR : cp_addr_type := cp_addr_init;`
172			`signal CP_DIN : slv16 := (others=>'0');`
173			`signal CP_STAT : cp_stat_type := cp_stat_init;`
174			`signal CP_DOUT : slv16 := (others=>'0');`
175
176			`signal EI_PRI : slv3 := (others=>'0');`
177			`signal EI_VECT : slv9_2 := (others=>'0');`
178			`signal EI_ACKM : slbit := '0';`
179
180			`signal EM_MREQ : em_mreq_type := em_mreq_init;`
181			`signal EM_SRES : em_sres_type := em_sres_init;`
182
183			`signal HM_ENA : slbit := '0';`
184			`signal MEM70_FMISS : slbit := '0';`
185			`signal CACHE_FMISS : slbit := '0';`
186			`signal CACHE_CHIT : slbit := '0';`
187
188			`signal MEM_REQ : slbit := '0';`
189			`signal MEM_WE : slbit := '0';`
190			`signal MEM_BUSY : slbit := '0';`
191			`signal MEM_ACK_R : slbit := '0';`
192			`signal MEM_ACT_R : slbit := '0';`
193			`signal MEM_ACT_W : slbit := '0';`
194			`signal MEM_ADDR : slv20 := (others=>'0');`
195			`signal MEM_BE : slv4 := (others=>'0');`
196			`signal MEM_DI : slv32 := (others=>'0');`
197			`signal MEM_DO : slv32 := (others=>'0');`
198
199			`signal MEM_ADDR_EXT : slv22 := (others=>'0');`
200
201			`signal BRESET : slbit := '0';`
202			`signal IB_MREQ : ib_mreq_type := ib_mreq_init;`
203			`signal IB_SRES : ib_sres_type := ib_sres_init;`
204
205			`signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;`
206			`signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;`
207
208			`signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;`
209			`signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;`
210			`signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;`
211			`signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;`
212
213			`signal DISPREG : slv16 := (others=>'0');`
214
215			`constant rbaddr_core0 : slv8 := "00000000";`
216			`constant rbaddr_ibus : slv8 := "10000000";`
217			`constant rbaddr_hio : slv8 := "11000000";`
218
219			`begin`
220
221			`CLKDIV : clkdivce`
222			`generic map (`
223			`CDUWIDTH => 6,`
224			`USECDIV => 50,`
225			`MSECDIV => 1000)`
226			`port map (`
227			`CLK => CLK,`
228			`CE_USEC => CE_USEC,`
229			`CE_MSEC => CE_MSEC`
230			`);`
231
232			`IOB_RS232 : s3_rs232_iob_int_ext`
233			`port map (`
234			`CLK => CLK,`
235			`SEL => SWI(0),`
236			`RXD => RXD,`
237			`TXD => TXD,`
238			`CTS_N => CTS_N,`
239			`RTS_N => RTS_N,`
240			`I_RXD0 => I_RXD,`
241			`O_TXD0 => O_TXD,`
242			`I_RXD1 => I_FUSP_RXD,`
243			`O_TXD1 => O_FUSP_TXD,`
244			`I_CTS1_N => I_FUSP_CTS_N,`
245			`O_RTS1_N => O_FUSP_RTS_N`
246			`);`
247
248			`HIO : s3_humanio_rri`
249			`generic map (`
250			`DEBOUNCE => sys_conf_hio_debounce,`
251			`RB_ADDR => rbaddr_hio)`
252			`port map (`
253			`CLK => CLK,`
254			`RESET => RESET,`
255			`CE_MSEC => CE_MSEC,`
256			`RB_MREQ => RB_MREQ,`
257			`RB_SRES => RB_SRES_HIO,`
258			`SWI => SWI,`
259			`BTN => BTN,`
260			`LED => LED,`
261			`DSP_DAT => DSP_DAT,`
262			`DSP_DP => DSP_DP,`
263			`I_SWI => I_SWI,`
264			`I_BTN => I_BTN,`
265			`O_LED => O_LED,`
266			`O_ANO_N => O_ANO_N,`
267			`O_SEG_N => O_SEG_N`
268			`);`
269
270			`RRI : rri_core_serport`
271			`generic map (`
272			`ATOWIDTH => 6, -- 64 cycles access timeout`
273			`ITOWIDTH => 6, -- 64 periods max idle timeout`
274			`CDWIDTH => 13,`
275			`CDINIT => sys_conf_ser2rri_cdinit)`
276			`port map (`
277			`CLK => CLK,`
278			`CE_USEC => CE_USEC,`
279			`CE_MSEC => CE_MSEC,`
280			`CE_INT => CE_MSEC,`
281			`RESET => RESET,`
282			`RXSD => RXD,`
283			`TXSD => TXD,`
284			`CTS_N => CTS_N,`
285			`RTS_N => RTS_N,`
286			`RB_MREQ => RB_MREQ,`
287			`RB_SRES => RB_SRES,`
288			`RB_LAM => RB_LAM,`
289			`RB_STAT => RB_STAT`
290			`);`
291
292			`RB_SRES_OR : rb_sres_or_3`
293			`port map (`
294			`RB_SRES_1 => RB_SRES_CPU,`
295			`RB_SRES_2 => RB_SRES_IBD,`
296			`RB_SRES_3 => RB_SRES_HIO,`
297			`RB_SRES_OR => RB_SRES`
298			`);`
299
300			`RB2CP : pdp11_core_rri`
301			`generic map (`
302			`RB_ADDR_CORE => rbaddr_core0,`
303			`RB_ADDR_IBUS => rbaddr_ibus)`
304			`port map (`
305			`CLK => CLK,`
306			`RESET => RESET,`
307			`RB_MREQ => RB_MREQ,`
308			`RB_SRES => RB_SRES_CPU,`
309			`RB_STAT => RB_STAT,`
310			`RRI_LAM => RB_LAM(0),`
311			`CPU_RESET => CPU_RESET,`
312			`CP_CNTL => CP_CNTL,`
313			`CP_ADDR => CP_ADDR,`
314			`CP_DIN => CP_DIN,`
315			`CP_STAT => CP_STAT,`
316			`CP_DOUT => CP_DOUT`
317			`);`
318
319			`CORE : pdp11_core`
320			`port map (`
321			`CLK => CLK,`
322			`RESET => CPU_RESET,`
323			`CP_CNTL => CP_CNTL,`
324			`CP_ADDR => CP_ADDR,`
325			`CP_DIN => CP_DIN,`
326			`CP_STAT => CP_STAT,`
327			`CP_DOUT => CP_DOUT,`
328			`EI_PRI => EI_PRI,`
329			`EI_VECT => EI_VECT,`
330			`EI_ACKM => EI_ACKM,`
331			`EM_MREQ => EM_MREQ,`
332			`EM_SRES => EM_SRES,`
333			`BRESET => BRESET,`
334			`IB_MREQ_M => IB_MREQ,`
335			`IB_SRES_M => IB_SRES,`
336			`DM_STAT_DP => DM_STAT_DP,`
337			`DM_STAT_VM => DM_STAT_VM,`
338			`DM_STAT_CO => DM_STAT_CO`
339			`);`
340
341			`MEM_BRAM: if sys_conf_bram > 0 generate`
342			`signal HM_VAL_BRAM : slbit := '0';`
343			`begin`
344
345			`MEM : pdp11_bram`
346			`generic map (`
347			`AWIDTH => sys_conf_bram_awidth)`
348			`port map (`
349			`CLK => CLK,`
350			`GRESET => CPU_RESET,`
351			`EM_MREQ => EM_MREQ,`
352			`EM_SRES => EM_SRES`
353			`);`
354
355			`HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write`
356
357			`MEM70: pdp11_mem70`
358			`port map (`
359			`CLK => CLK,`
360			`CRESET => BRESET,`
361			`HM_ENA => EM_MREQ.req,`
362			`HM_VAL => HM_VAL_BRAM,`
363			`CACHE_FMISS => MEM70_FMISS,`
364			`IB_MREQ => IB_MREQ,`
365			`IB_SRES => IB_SRES_MEM70`
366			`);`
367
368			`SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy`
369			`port map (`
370			`O_MEM_CE_N => O_MEM_CE_N,`
371			`O_MEM_BE_N => O_MEM_BE_N,`
372			`O_MEM_WE_N => O_MEM_WE_N,`
373			`O_MEM_OE_N => O_MEM_OE_N,`
374			`O_MEM_ADV_N => O_MEM_ADV_N,`
375			`O_MEM_CLK => O_MEM_CLK,`
376			`O_MEM_CRE => O_MEM_CRE,`
377			`I_MEM_WAIT => I_MEM_WAIT,`
378			`O_FLA_CE_N => O_FLA_CE_N,`
379			`O_MEM_ADDR => O_MEM_ADDR,`
380			`IO_MEM_DATA => IO_MEM_DATA`
381			`);`
382
383			`end generate MEM_BRAM;`
384
385			`MEM_SRAM: if sys_conf_bram = 0 generate`
386
387			`CACHE: pdp11_cache`
388			`port map (`
389			`CLK => CLK,`
390			`GRESET => CPU_RESET,`
391			`EM_MREQ => EM_MREQ,`
392			`EM_SRES => EM_SRES,`
393			`FMISS => CACHE_FMISS,`
394			`CHIT => CACHE_CHIT,`
395			`MEM_REQ => MEM_REQ,`
396			`MEM_WE => MEM_WE,`
397			`MEM_BUSY => MEM_BUSY,`
398			`MEM_ACK_R => MEM_ACK_R,`
399			`MEM_ADDR => MEM_ADDR,`
400			`MEM_BE => MEM_BE,`
401			`MEM_DI => MEM_DI,`
402			`MEM_DO => MEM_DO`
403			`);`
404
405			`MEM70: pdp11_mem70`
406			`port map (`
407			`CLK => CLK,`
408			`CRESET => BRESET,`
409			`HM_ENA => HM_ENA,`
410			`HM_VAL => CACHE_CHIT,`
411			`CACHE_FMISS => MEM70_FMISS,`
412			`IB_MREQ => IB_MREQ,`
413			`IB_SRES => IB_SRES_MEM70`
414			`);`
415
416			`HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;`
417			`CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;`
418
419			`MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)`
420
421			`SRAM_CTL: n2_cram_memctl_as`
422			`generic map (`
423			`READ0DELAY => 2,`
424			`READ1DELAY => 2,`
425			`WRITEDELAY => 3)`
426			`port map (`
427			`CLK => CLK,`
428			`RESET => CPU_RESET,`
429			`REQ => MEM_REQ,`
430			`WE => MEM_WE,`
431			`BUSY => MEM_BUSY,`
432			`ACK_R => MEM_ACK_R,`
433			`ACK_W => open,`
434			`ACT_R => MEM_ACT_R,`
435			`ACT_W => MEM_ACT_W,`
436			`ADDR => MEM_ADDR_EXT,`
437			`BE => MEM_BE,`
438			`DI => MEM_DI,`
439			`DO => MEM_DO,`
440			`O_MEM_CE_N => O_MEM_CE_N,`
441			`O_MEM_BE_N => O_MEM_BE_N,`
442			`O_MEM_WE_N => O_MEM_WE_N,`
443			`O_MEM_OE_N => O_MEM_OE_N,`
444			`O_MEM_ADV_N => O_MEM_ADV_N,`
445			`O_MEM_CLK => O_MEM_CLK,`
446			`O_MEM_CRE => O_MEM_CRE,`
447			`I_MEM_WAIT => I_MEM_WAIT,`
448			`O_FLA_CE_N => O_FLA_CE_N,`
449			`O_MEM_ADDR => O_MEM_ADDR,`
450			`IO_MEM_DATA => IO_MEM_DATA`
451			`);`
452
453			`end generate MEM_SRAM;`
454
455			`IB_SRES_OR : ib_sres_or_2`
456			`port map (`
457			`IB_SRES_1 => IB_SRES_MEM70,`
458			`IB_SRES_2 => IB_SRES_IBDR,`
459			`IB_SRES_OR => IB_SRES`
460			`);`
461
462			`IBD_MINI : if false generate`
463			`begin`
464			`IBDR_SYS : ibdr_minisys`
465			`port map (`
466			`CLK => CLK,`
467			`CE_USEC => CE_USEC,`
468			`CE_MSEC => CE_MSEC,`
469			`RESET => CPU_RESET,`
470			`BRESET => BRESET,`
471			`RRI_LAM => RB_LAM(15 downto 1),`
472			`IB_MREQ => IB_MREQ,`
473			`IB_SRES => IB_SRES_IBDR,`
474			`EI_ACKM => EI_ACKM,`
475			`EI_PRI => EI_PRI,`
476			`EI_VECT => EI_VECT,`
477			`DISPREG => DISPREG`
478			`);`
479			`end generate IBD_MINI;`
480
481			`IBD_MAXI : if true generate`
482			`begin`
483			`IBDR_SYS : ibdr_maxisys`
484			`port map (`
485			`CLK => CLK,`
486			`CE_USEC => CE_USEC,`
487			`CE_MSEC => CE_MSEC,`
488			`RESET => CPU_RESET,`
489			`BRESET => BRESET,`
490			`RRI_LAM => RB_LAM(15 downto 1),`
491			`IB_MREQ => IB_MREQ,`
492			`IB_SRES => IB_SRES_IBDR,`
493			`EI_ACKM => EI_ACKM,`
494			`EI_PRI => EI_PRI,`
495			`EI_VECT => EI_VECT,`
496			`DISPREG => DISPREG`
497			`);`
498			`end generate IBD_MAXI;`
499
500			`DSP_DAT(15 downto 0) <= DISPREG;`
501			`DSP_DP(0) <= not RXD;`
502			`DSP_DP(1) <= RTS_N;`
503			`DSP_DP(2) <= not TXD;`
504			`DSP_DP(3) <= CTS_N;`
505
506			`proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)`
507			`variable iled : slv8 := (others=>'0');`
508			`begin`
509			`iled := (others=>'0');`
510			`iled(7) := MEM_ACT_W;`
511			`iled(6) := MEM_ACT_R;`
512			`iled(5) := CP_STAT.cmdbusy;`
513			`if CP_STAT.cpugo = '1' then`
514			`case DM_STAT_DP.psw.cmode is`
515			`when c_psw_kmode =>`
516			`if CP_STAT.cpuwait = '1' then`
517			`iled(2) := '1';`
518			`elsif unsigned(DM_STAT_DP.psw.pri) = 0 then`
519			`iled(3) := '1';`
520			`else`
521			`iled(4) := '1';`
522			`end if;`
523			`when c_psw_smode =>`
524			`iled(1) := '1';`
525			`when c_psw_umode =>`
526			`iled(0) := '1';`
527			`when others => null;`
528			`end case;`
529			`else`
530			`iled(4) := '1';`
531			`iled(3 downto 0) := CP_STAT.cpurust;`
532			`end if;`
533			`LED <= iled;`
534			`end process;`
535
536			`-- synthesis translate_off`
537			`DM_STAT_SY.emmreq <= EM_MREQ;`
538			`DM_STAT_SY.emsres <= EM_SRES;`
539			`DM_STAT_SY.chit <= CACHE_CHIT;`
540
541			`TMU : pdp11_tmu_sb`
542			`generic map (`
543			`ENAPIN => 13)`
544			`port map (`
545			`CLK => CLK,`
546			`DM_STAT_DP => DM_STAT_DP,`
547			`DM_STAT_VM => DM_STAT_VM,`
548			`DM_STAT_CO => DM_STAT_CO,`
549			`DM_STAT_SY => DM_STAT_SY`
550			`);`
551
552			`-- synthesis translate_on`
553			`end syn;`