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-- $Id: sys_w11a_s3.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name:    sys_w11a_s3 - syn
-- Description:    w11a test design for s3board
--
-- Dependencies:   vlib/genlib/clkdivce
--                 bplib/bpgen/bp_rs232_2l4l_iob
--                 bplib/bpgen/sn_humanio
--                 vlib/rlink/rlink_base_serport
--                 vlib/rbus/rb_sres_or_2
--                 w11a/pdp11_core_rbus
--                 w11a/pdp11_core
--                 w11a/pdp11_bram
--                 vlib/s3board/s3_sram_dummy
--                 w11a/pdp11_cache
--                 w11a/pdp11_mem70
--                 bplib/s3board/s3_sram_memctl
--                 ibus/ib_sres_or_2
--                 ibus/ibdr_minisys
--                 ibus/ibdr_maxisys
--                 w11a/pdp11_tmu_sb           [sim only]
--
-- Test bench:     tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions:  xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
-- 2011-11-19   427 13.1    O40d xc3s1000-4  1322 4298  242 2616 OK: LP+PC+DL+II
-- 2010-12-30   351 12.1    M53d xc3s1000-4  1316 4291  242 2609 OK: LP+PC+DL+II
-- 2010-11-06   336 12.1    M53d xc3s1000-4  1284 4253* 242 2575 OK: LP+PC+DL+II
-- 2010-10-24   335 12.1    M53d xc3s1000-4  1284 4495  242 2575 OK: LP+PC+DL+II
-- 2010-05-01   285 11.4    L68  xc3s1000-4  1239 4086  224 2471 OK: LP+PC+DL+II
-- 2010-04-26   283 11.4    L68  xc3s1000-4  1245 4083  224 2474 OK: LP+PC+DL+II
-- 2009-07-12   233 11.2    L46  xc3s1000-4  1245 4078  224 2472 OK: LP+PC+DL+II
-- 2009-07-12   233 10.1.03 K39  xc3s1000-4  1250 4097  224 2494 OK: LP+PC+DL+II
-- 2009-06-01   221 10.1.03 K39  xc3s1000-4  1209 3986  224 2425 OK: LP+PC+DL+II
-- 2009-05-17   216 10.1.03 K39  xc3s1000-4  1039 3542  224 2116 m+p; TIME OK
-- 2009-05-09   213 10.1.03 K39  xc3s1000-4  1037 3500  224 2100 m+p; TIME OK
-- 2009-04-26   209  8.2.03 I34  xc3s1000-4  1099 3557  224 2264 m+p; TIME OK
-- 2008-12-13   176  8.2.03 I34  xc3s1000-4  1116 3672  224 2280 m+p; TIME OK
-- 2008-12-06   174 10.1.02 K37  xc3s1000-4  1038 3503  224 2100 m+p; TIME OK
-- 2008-12-06   174  8.2.03 I34  xc3s1000-4  1116 3682  224 2281 m+p; TIME OK
-- 2008-08-22   161  8.2.03 I34  xc3s1000-4  1118 3677  224 2288 m+p; TIME OK
-- 2008-08-22   161 10.1.02 K37  xc3s1000-4  1035 3488  224 2086 m+p; TIME OK
-- 2008-05-01   140  8.2.03 I34  xc3s1000-4  1057 3344  224 2119 m+p; 21ns;BR-32
-- 2008-05-01   140  8.2.03 I34  xc3s1000-4  1057 3357  224 2128 m+p; 21ns;BR-16
-- 2008-05-01   140  8.2.03 I34  xc3s1000-4  1057 3509  224 2220 m+p; TIME OK
-- 2008-05-01   140  9.2.04 J40  xc3s200-4   1009 3195  224 1918 m+p; T-OK;BR-16
-- 2008-03-19   127  8.2.03 I34  xc3s1000-4  1077 3471  224 2207 m+p; TIME OK
-- 2008-03-02   122  8.2.03 I34  xc3s1000-4  1068 3448  224 2179 m+p; TIME OK
-- 2008-03-02   121  8.2.03 I34  xc3s1000-4  1064 3418  224 2148 m+p; TIME FAIL
-- 2008-02-24   119  8.2.03 I34  xc3s1000-4  1071 3372  224 2141 m+p; TIME OK
-- 2008-02-23   118  8.2.03 I34  xc3s1000-4  1035 3301  182 1996 m+p; TIME OK
-- 2008-01-06   111  8.2.03 I34  xc3s1000-4   971 2898  182 1831 m+p; TIME OK
-- 2007-12-30   107  8.2.03 I34  xc3s1000-4   891 2719  137 1515 s 18.8
-- 2007-12-30   107  8.2.03 I34  xc3s1000-4   891 2661  137 1654 m+p; TIME OK
--   Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History: 
-- Date         Rev Version  Comment
-- 2011-11-19   427   1.4.3  now numeric_std clean
-- 2011-07-09   391   1.4.2  use now bp_rs232_2l4l_iob
-- 2011-07-08   390   1.4.1  use now sn_humanio
-- 2010-12-30   351   1.4    ported to rbv3
-- 2010-11-06   336   1.3.7  rename input pin CLK -> I_CLK50
-- 2010-10-23   335   1.3.3  rename RRI_LAM->RB_LAM;
-- 2010-06-26   309   1.3.2  use constants for rbus addresses (rbaddr_...)
-- 2010-06-18   306   1.3.1  rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
--                           remove pdp11_ibdr_rri
-- 2010-06-13   305   1.6.1  add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-11   303   1.6    use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03   300   1.5.6  use default FAWIDTH for rri_core_serport
-- 2010-05-28   295   1.5.5  rename sys_pdp11core -> sys_w11a_s3
-- 2010-05-21   292   1.5.4  rename _PM1_ -> _FUSP_
-- 2010-05-16   291   1.5.3  rename memctl_s3sram->s3_sram_memctl
-- 2010-05-05   288   1.5.2  add sys_conf_hio_debounce
-- 2010-05-02   287   1.5.1  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
--                           drop RP_IINT from interfaces; drop RTSFLUSH generic
--                           add pm1 rs232 (usp) support
-- 2010-05-01   285   1.5    port to rri V2 interface, use rri_core_serport
-- 2010-04-17   278   1.4.5  rename sram_dummy -> s3_sram_dummy
-- 2010-04-10   275   1.4.4  use s3_humanio; invert DP(1,3)
-- 2009-07-12   233   1.4.3  adapt to ibdr_(mini|maxi)sys interface changes
-- 2009-06-01   221   1.4.2  support ibdr_maxisys as well as _minisys
-- 2009-05-10   214   1.4.1  use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22   161   1.4.0  use iblib, ibdlib; renames
-- 2008-05-03   143   1.3.6  rename _cpursta->_cpurust
-- 2008-05-01   142   1.3.5  reassign LED(cpugo,halt,rust) and DISP(dispreg)
-- 2008-04-19   137   1.3.4  add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18   136   1.3.3  add RESET for ibdr_minisys
-- 2008-04-13   135   1.3.2  add _mem70 also for _bram configs
-- 2008-02-23   118   1.3.1  add _mem70
-- 2008-02-17   117   1.3    use ext. memory interface of _core; 
--                           use _cache + memctl or _bram (configurable)
-- 2008-01-20   113   1.2.1  finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)
-- 2008-01-20   112   1.2    rename clkgen->clkdivce; use ibdr_minisys, BRESET
--                           add _ib_mux2
-- 2008-01-06   111   1.1    use now iob_reg_*; remove rricp_pdp11core hack
--                           instanciate all parts directly
-- 2007-12-23   105   1.0.4  add rritb_cpmon_sb
-- 2007-12-16   101   1.0.3  use _N for active low; set IOB attribute to RI/RO
-- 2007-12-09   100   1.0.2  add sram memory signals, dummy handle them
-- 2007-10-19    90   1.0.1  init RI_RXD,RO_TXD=1 to avoid startup glitch
-- 2007-09-23    84   1.0    Initial version
------------------------------------------------------------------------------
--
-- w11a test design for s3board
--    w11a + rlink + serport
--
-- Usage of S3BOARD Switches, Buttons, LEDs:
--    LED(7..0):last RXDATA
--
--    DP(0):    RXSD   (inverted to signal activity)
--    DP(1):    RTS_N  (shows rx back preasure)
--    DP(2):    TXSD   (inverted to signal activity)
--    DP(3):    CTS_N  (shows tx back preasure)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_w11a_s3 is                   -- top level
                                        -- implements s3board_fusp_aif
  port (
    I_CLK50 : in slbit;                 -- 50 MHz board clock
    I_RXD : in slbit;                   -- receive data (board view)
    O_TXD : out slbit;                  -- transmit data (board view)
    I_SWI : in slv8;                    -- s3 switches
    I_BTN : in slv4;                    -- s3 buttons
    O_LED : out slv8;                   -- s3 leds
    O_ANO_N : out slv4;                 -- 7 segment disp: anodes   (act.low)
    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)
    O_MEM_CE_N : out slv2;              -- sram: chip enables  (act.low)
    O_MEM_BE_N : out slv4;              -- sram: byte enables  (act.low)
    O_MEM_WE_N : out slbit;             -- sram: write enable  (act.low)
    O_MEM_OE_N : out slbit;             -- sram: output enable (act.low)
    O_MEM_ADDR  : out slv18;            -- sram: address lines
    IO_MEM_DATA : inout slv32;          -- sram: data lines
    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n
    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n
    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx
    O_FUSP_TXD : out slbit              -- fusp: rs232 tx
  );
end sys_w11a_s3;
 
architecture syn of sys_w11a_s3 is
 
  signal CLK :   slbit := '0';
 
  signal RXD :   slbit := '1';
  signal TXD :   slbit := '0';
  signal RTS_N : slbit := '0';
  signal CTS_N : slbit := '0';
 
  signal SWI     : slv8  := (others=>'0');
  signal BTN     : slv4  := (others=>'0');
  signal LED     : slv8  := (others=>'0');
  signal DSP_DAT : slv16 := (others=>'0');
  signal DSP_DP  : slv4  := (others=>'0');
 
  signal RB_LAM  : slv16 := (others=>'0');
  signal RB_STAT : slv3  := (others=>'0');
 
  signal RB_MREQ     : rb_mreq_type := rb_mreq_init;
  signal RB_SRES     : rb_sres_type := rb_sres_init;
  signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
  signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
 
  signal RESET   : slbit := '0';
  signal CE_USEC : slbit := '0';
  signal CE_MSEC : slbit := '0';
 
  signal CPU_RESET : slbit := '0';
  signal CP_CNTL : cp_cntl_type := cp_cntl_init;
  signal CP_ADDR : cp_addr_type := cp_addr_init;
  signal CP_DIN  : slv16 := (others=>'0');
  signal CP_STAT : cp_stat_type := cp_stat_init;
  signal CP_DOUT : slv16 := (others=>'0');
 
  signal EI_PRI  : slv3   := (others=>'0');
  signal EI_VECT : slv9_2 := (others=>'0');
  signal EI_ACKM : slbit  := '0';
 
  signal EM_MREQ : em_mreq_type := em_mreq_init;
  signal EM_SRES : em_sres_type := em_sres_init;
 
  signal HM_ENA      : slbit := '0';
  signal MEM70_FMISS : slbit := '0';
  signal CACHE_FMISS : slbit := '0';
  signal CACHE_CHIT  : slbit := '0';
 
  signal MEM_REQ   : slbit := '0';
  signal MEM_WE    : slbit := '0';
  signal MEM_BUSY  : slbit := '0';
  signal MEM_ACK_R : slbit := '0';
  signal MEM_ADDR  : slv20 := (others=>'0');
  signal MEM_BE    : slv4  := (others=>'0');
  signal MEM_DI    : slv32 := (others=>'0');
  signal MEM_DO    : slv32 := (others=>'0');
 
  signal BRESET  : slbit := '0';
  signal IB_MREQ : ib_mreq_type := ib_mreq_init;
  signal IB_SRES : ib_sres_type := ib_sres_init;
 
  signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
  signal IB_SRES_IBDR  : ib_sres_type := ib_sres_init;
 
  signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
  signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
  signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
  signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
 
  signal DISPREG : slv16 := (others=>'0');
 
  constant rbaddr_core0 : slv8 := "00000000";
  constant rbaddr_ibus  : slv8 := "10000000";
  constant rbaddr_hio   : slv8 := "11000000";
 
begin
 
  CLK <= I_CLK50;                       -- use 50MHz as system clock
 
  CLKDIV : clkdivce
    generic map (
      CDUWIDTH => 6,
      USECDIV  => 50,
      MSECDIV  => 1000)
    port map (
      CLK     => CLK,
      CE_USEC => CE_USEC,
      CE_MSEC => CE_MSEC
    );
 
  IOB_RS232 : bp_rs232_2l4l_iob
    port map (
      CLK      => CLK,
      RESET    => '0',
      SEL      => SWI(0),
      RXD      => RXD,
      TXD      => TXD,
      CTS_N    => CTS_N,
      RTS_N    => RTS_N,
      I_RXD0   => I_RXD,
      O_TXD0   => O_TXD,
      I_RXD1   => I_FUSP_RXD,
      O_TXD1   => O_FUSP_TXD,
      I_CTS1_N => I_FUSP_CTS_N,
      O_RTS1_N => O_FUSP_RTS_N
    );
 
  HIO : sn_humanio
    generic map (
      DEBOUNCE => sys_conf_hio_debounce)
    port map (
      CLK     => CLK,
      RESET   => RESET,
      CE_MSEC => CE_MSEC,
      SWI     => SWI,
      BTN     => BTN,
      LED     => LED,
      DSP_DAT => DSP_DAT,
      DSP_DP  => DSP_DP,
      I_SWI   => I_SWI,
      I_BTN   => I_BTN,
      O_LED   => O_LED,
      O_ANO_N => O_ANO_N,
      O_SEG_N => O_SEG_N
    );
 
  RLINK : rlink_base_serport
    generic map (
      ATOWIDTH =>  6,                   -- 64 cycles access timeout
      ITOWIDTH =>  6,                   -- 64 periods max idle timeout
      IFAWIDTH =>  5,                   -- 32 word input fifo
      OFAWIDTH =>  0,                   -- no output fifo
      CDWIDTH  => 13,
      CDINIT   => sys_conf_ser2rri_cdinit)
    port map (
      CLK      => CLK,
      CE_USEC  => CE_USEC,
      CE_MSEC  => CE_MSEC,
      CE_INT   => CE_MSEC,
      RESET    => RESET,
      RXSD     => RXD,
      TXSD     => TXD,
      CTS_N    => CTS_N,
      RTS_N    => RTS_N,
      RB_MREQ  => RB_MREQ,
      RB_SRES  => RB_SRES,
      RB_LAM   => RB_LAM,
      RB_STAT  => RB_STAT,
      RL_MONI  => open,
      RL_SER_MONI => open
    );
 
  RB_SRES_OR : rb_sres_or_2
    port map (
      RB_SRES_1  => RB_SRES_CPU,
      RB_SRES_2  => RB_SRES_IBD,
      RB_SRES_OR => RB_SRES
    );
 
  RP2CP : pdp11_core_rbus
    generic map (
      RB_ADDR_CORE => rbaddr_core0,
      RB_ADDR_IBUS => rbaddr_ibus)
    port map (
      CLK       => CLK,
      RESET     => RESET,
      RB_MREQ   => RB_MREQ,
      RB_SRES   => RB_SRES_CPU,
      RB_STAT   => RB_STAT,
      RB_LAM    => RB_LAM(0),
      CPU_RESET => CPU_RESET,
      CP_CNTL   => CP_CNTL,
      CP_ADDR   => CP_ADDR,
      CP_DIN    => CP_DIN,
      CP_STAT   => CP_STAT,
      CP_DOUT   => CP_DOUT
    );
 
  CORE : pdp11_core
    port map (
      CLK       => CLK,
      RESET     => CPU_RESET,
      CP_CNTL   => CP_CNTL,
      CP_ADDR   => CP_ADDR,
      CP_DIN    => CP_DIN,
      CP_STAT   => CP_STAT,
      CP_DOUT   => CP_DOUT,
      EI_PRI    => EI_PRI,
      EI_VECT   => EI_VECT,
      EI_ACKM   => EI_ACKM,
      EM_MREQ   => EM_MREQ,
      EM_SRES   => EM_SRES,
      BRESET    => BRESET,
      IB_MREQ_M => IB_MREQ,
      IB_SRES_M => IB_SRES,
      DM_STAT_DP => DM_STAT_DP,
      DM_STAT_VM => DM_STAT_VM,
      DM_STAT_CO => DM_STAT_CO
    );
 
  MEM_BRAM: if sys_conf_bram > 0 generate
    signal HM_VAL_BRAM : slbit := '0';
  begin
 
    MEM : pdp11_bram
      generic map (
        AWIDTH => sys_conf_bram_awidth)
      port map (
        CLK     => CLK,
        GRESET  => CPU_RESET,
        EM_MREQ => EM_MREQ,
        EM_SRES => EM_SRES
      );
 
    HM_VAL_BRAM <= not EM_MREQ.we;        -- assume hit if read, miss if write
 
    MEM70: pdp11_mem70
      port map (
        CLK         => CLK,
        CRESET      => BRESET,
        HM_ENA      => EM_MREQ.req,
        HM_VAL      => HM_VAL_BRAM,
        CACHE_FMISS => MEM70_FMISS,
        IB_MREQ     => IB_MREQ,
        IB_SRES     => IB_SRES_MEM70
      );
 
    SRAM_PROT : s3_sram_dummy             -- connect SRAM to protection dummy
      port map (
        O_MEM_CE_N  => O_MEM_CE_N,
        O_MEM_BE_N  => O_MEM_BE_N,
        O_MEM_WE_N  => O_MEM_WE_N,
        O_MEM_OE_N  => O_MEM_OE_N,
        O_MEM_ADDR  => O_MEM_ADDR,
        IO_MEM_DATA => IO_MEM_DATA
      );
 
  end generate MEM_BRAM;
 
  MEM_SRAM: if sys_conf_bram = 0 generate
 
    CACHE: pdp11_cache
      port map (
        CLK       => CLK,
        GRESET    => CPU_RESET,
        EM_MREQ   => EM_MREQ,
        EM_SRES   => EM_SRES,
        FMISS     => CACHE_FMISS,
        CHIT      => CACHE_CHIT,
        MEM_REQ   => MEM_REQ,
        MEM_WE    => MEM_WE,
        MEM_BUSY  => MEM_BUSY,
        MEM_ACK_R => MEM_ACK_R,
        MEM_ADDR  => MEM_ADDR,
        MEM_BE    => MEM_BE,
        MEM_DI    => MEM_DI,
        MEM_DO    => MEM_DO
      );
 
    MEM70: pdp11_mem70
      port map (
        CLK         => CLK,
        CRESET      => BRESET,
        HM_ENA      => HM_ENA,
        HM_VAL      => CACHE_CHIT,
        CACHE_FMISS => MEM70_FMISS,
        IB_MREQ     => IB_MREQ,
        IB_SRES     => IB_SRES_MEM70
      );
 
    HM_ENA      <= EM_SRES.ack_r or EM_SRES.ack_w;
    CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
 
    SRAM_CTL: s3_sram_memctl
      port map (
        CLK         => CLK,
        RESET       => CPU_RESET,
        REQ         => MEM_REQ,
        WE          => MEM_WE,
        BUSY        => MEM_BUSY,
        ACK_R       => MEM_ACK_R,
        ACK_W       => open,
        ACT_R       => open,
        ACT_W       => open,
        ADDR        => MEM_ADDR(17 downto 0),
        BE          => MEM_BE,
        DI          => MEM_DI,
        DO          => MEM_DO,
        O_MEM_CE_N  => O_MEM_CE_N,
        O_MEM_BE_N  => O_MEM_BE_N,
        O_MEM_WE_N  => O_MEM_WE_N,
        O_MEM_OE_N  => O_MEM_OE_N,
        O_MEM_ADDR  => O_MEM_ADDR,
        IO_MEM_DATA => IO_MEM_DATA
      );
 
  end generate MEM_SRAM;
 
  IB_SRES_OR : ib_sres_or_2
    port map (
      IB_SRES_1  => IB_SRES_MEM70,
      IB_SRES_2  => IB_SRES_IBDR,
      IB_SRES_OR => IB_SRES);
 
  IBD_MINI : if false generate
  begin
    IBDR_SYS : ibdr_minisys
      port map (
        CLK      => CLK,
        CE_USEC  => CE_USEC,
        CE_MSEC  => CE_MSEC,
        RESET    => CPU_RESET,
        BRESET   => BRESET,
        RB_LAM   => RB_LAM(15 downto 1),
        IB_MREQ  => IB_MREQ,
        IB_SRES  => IB_SRES_IBDR,
        EI_ACKM  => EI_ACKM,
        EI_PRI   => EI_PRI,
        EI_VECT  => EI_VECT,
        DISPREG  => DISPREG);
  end generate IBD_MINI;
 
  IBD_MAXI : if true generate
  begin
    IBDR_SYS : ibdr_maxisys
      port map (
        CLK      => CLK,
        CE_USEC  => CE_USEC,
        CE_MSEC  => CE_MSEC,
        RESET    => CPU_RESET,
        BRESET   => BRESET,
        RB_LAM   => RB_LAM(15 downto 1),
        IB_MREQ  => IB_MREQ,
        IB_SRES  => IB_SRES_IBDR,
        EI_ACKM  => EI_ACKM,
        EI_PRI   => EI_PRI,
        EI_VECT  => EI_VECT,
        DISPREG  => DISPREG);
  end generate IBD_MAXI;
 
  DSP_DAT(15 downto 0) <= DISPREG;
  DSP_DP(0) <= not RXD;
  DSP_DP(1) <= RTS_N;
  DSP_DP(2) <= not TXD;
  DSP_DP(3) <= CTS_N;
 
  LED(0)          <= CP_STAT.cpugo;
  LED(1)          <= CP_STAT.cpuhalt;
  LED(5 downto 2) <= CP_STAT.cpurust;
  LED(6) <= SWI(0) or SWI(1) or SWI(2) or SWI(3) or
            SWI(4) or SWI(5) or SWI(6) or SWI(7);
  LED(7) <= BTN(0) or BTN(1) or BTN(2) or BTN(3);
 
-- synthesis translate_off
  DM_STAT_SY.emmreq <= EM_MREQ;
  DM_STAT_SY.emsres <= EM_SRES;
  DM_STAT_SY.chit   <= CACHE_CHIT;
 
  TMU : pdp11_tmu_sb
    generic map (
      ENAPIN => 13)
    port map (
      CLK        => CLK,
      DM_STAT_DP => DM_STAT_DP,
      DM_STAT_VM => DM_STAT_VM,
      DM_STAT_CO => DM_STAT_CO,
      DM_STAT_SY => DM_STAT_SY
    );
 
-- synthesis translate_on
end syn;

Line No.	Rev	Author	Line
1	13	wfjm	`-- $Id: sys_w11a_s3.vhd 427 2011-11-19 21:04:11Z mueller $`
2	2	wfjm	`--`
3	12	wfjm	`-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4	2	wfjm	`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Module Name: sys_w11a_s3 - syn`
16			`-- Description: w11a test design for s3board`
17			`--`
18			`-- Dependencies: vlib/genlib/clkdivce`
19	12	wfjm	`-- bplib/bpgen/bp_rs232_2l4l_iob`
20			`-- bplib/bpgen/sn_humanio`
21	9	wfjm	`-- vlib/rlink/rlink_base_serport`
22			`-- vlib/rbus/rb_sres_or_2`
23			`-- w11a/pdp11_core_rbus`
24	2	wfjm	`-- w11a/pdp11_core`
25			`-- w11a/pdp11_bram`
26			`-- vlib/s3board/s3_sram_dummy`
27			`-- w11a/pdp11_cache`
28			`-- w11a/pdp11_mem70`
29			`-- bplib/s3board/s3_sram_memctl`
30			`-- ibus/ib_sres_or_2`
31			`-- ibus/ibdr_minisys`
32			`-- ibus/ibdr_maxisys`
33			`-- w11a/pdp11_tmu_sb [sim only]`
34			`--`
35	12	wfjm	`-- Test bench: tb/tb_sys_w11a_s3`
36	2	wfjm	`--`
37			`-- Target Devices: generic`
38	13	wfjm	`-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.18-0.29`
39	2	wfjm	`--`
40			`-- Synthesized (xst):`
41			`-- Date Rev ise Target flop lutl lutm slic t peri`
42	13	wfjm	`-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II`
43	9	wfjm	`-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II`
44	8	wfjm	`-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II`
45			`-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II`
46	2	wfjm	`-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II`
47			`-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II`
48			`-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II`
49			`-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II`
50			`-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II`
51			`-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK`
52			`-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK`
53			`-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK`
54			`-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK`
55			`-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK`
56			`-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK`
57			`-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK`
58			`-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK`
59			`-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32`
60			`-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16`
61			`-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK`
62			`-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16`
63			`-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK`
64			`-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK`
65			`-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL`
66			`-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK`
67			`-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK`
68			`-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK`
69			`-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8`
70			`-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK`
71	8	wfjm	`-- Note: till 2010-10-24 lutm included 'route-thru', after only logic`
72	2	wfjm	`--`
73			`-- Revision History:`
74			`-- Date Rev Version Comment`
75	13	wfjm	`-- 2011-11-19 427 1.4.3 now numeric_std clean`
76	12	wfjm	`-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob`
77			`-- 2011-07-08 390 1.4.1 use now sn_humanio`
78	9	wfjm	`-- 2010-12-30 351 1.4 ported to rbv3`
79	8	wfjm	`-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50`
80			`-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;`
81	2	wfjm	`-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)`
82			`-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;`
83			`-- remove pdp11_ibdr_rri`
84			`-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core`
85			`-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ`
86			`-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport`
87			`-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3`
88			`-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_`
89			`-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl`
90			`-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce`
91			`-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM`
92			`-- drop RP_IINT from interfaces; drop RTSFLUSH generic`
93			`-- add pm1 rs232 (usp) support`
94			`-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport`
95			`-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy`
96			`-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3)`
97			`-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini\|maxi)sys interface changes`
98			`-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys`
99			`-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu`
100			`-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames`
101			`-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust`
102			`-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg)`
103			`-- 2008-04-19 137 1.3.4 add DM_STAT_(DP\|VM\|CO\|SY) signals, add pdp11_tmu`
104			`-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys`
105			`-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs`
106			`-- 2008-02-23 118 1.3.1 add _mem70`
107			`-- 2008-02-17 117 1.3 use ext. memory interface of _core;`
108			`-- use _cache + memctl or _bram (configurable)`
109			`-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)`
110			`-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET`
111			`-- add _ib_mux2`
112			`-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack`
113			`-- instanciate all parts directly`
114			`-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb`
115			`-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO`
116			`-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them`
117			`-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch`
118			`-- 2007-09-23 84 1.0 Initial version`
119			`------------------------------------------------------------------------------`
120			`--`
121			`-- w11a test design for s3board`
122	9	wfjm	`-- w11a + rlink + serport`
123	2	wfjm	`--`
124			`-- Usage of S3BOARD Switches, Buttons, LEDs:`
125			`-- LED(7..0):last RXDATA`
126			`--`
127			`-- DP(0): RXSD (inverted to signal activity)`
128			`-- DP(1): RTS_N (shows rx back preasure)`
129			`-- DP(2): TXSD (inverted to signal activity)`
130			`-- DP(3): CTS_N (shows tx back preasure)`
131
132			`library ieee;`
133			`use ieee.std_logic_1164.all;`
134	13	wfjm	`use ieee.numeric_std.all;`
135	2	wfjm
136			`use work.slvtypes.all;`
137			`use work.genlib.all;`
138	9	wfjm	`use work.rblib.all;`
139			`use work.rlinklib.all;`
140	12	wfjm	`use work.bpgenlib.all;`
141	2	wfjm	`use work.s3boardlib.all;`
142			`use work.iblib.all;`
143			`use work.ibdlib.all;`
144			`use work.pdp11.all;`
145			`use work.sys_conf.all;`
146
147			`-- ----------------------------------------------------------------------------`
148
149			`entity sys_w11a_s3 is -- top level`
150			`-- implements s3board_fusp_aif`
151			`port (`
152	8	wfjm	`I_CLK50 : in slbit; -- 50 MHz board clock`
153	2	wfjm	`I_RXD : in slbit; -- receive data (board view)`
154			`O_TXD : out slbit; -- transmit data (board view)`
155			`I_SWI : in slv8; -- s3 switches`
156			`I_BTN : in slv4; -- s3 buttons`
157			`O_LED : out slv8; -- s3 leds`
158			`O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)`
159			`O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)`
160			`O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)`
161			`O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)`
162			`O_MEM_WE_N : out slbit; -- sram: write enable (act.low)`
163			`O_MEM_OE_N : out slbit; -- sram: output enable (act.low)`
164			`O_MEM_ADDR : out slv18; -- sram: address lines`
165			`IO_MEM_DATA : inout slv32; -- sram: data lines`
166			`O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n`
167			`I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n`
168			`I_FUSP_RXD : in slbit; -- fusp: rs232 rx`
169			`O_FUSP_TXD : out slbit -- fusp: rs232 tx`
170			`);`
171			`end sys_w11a_s3;`
172
173			`architecture syn of sys_w11a_s3 is`
174
175	8	wfjm	`signal CLK : slbit := '0';`
176
177	2	wfjm	`signal RXD : slbit := '1';`
178			`signal TXD : slbit := '0';`
179			`signal RTS_N : slbit := '0';`
180			`signal CTS_N : slbit := '0';`
181
182			`signal SWI : slv8 := (others=>'0');`
183			`signal BTN : slv4 := (others=>'0');`
184			`signal LED : slv8 := (others=>'0');`
185			`signal DSP_DAT : slv16 := (others=>'0');`
186			`signal DSP_DP : slv4 := (others=>'0');`
187
188			`signal RB_LAM : slv16 := (others=>'0');`
189			`signal RB_STAT : slv3 := (others=>'0');`
190
191			`signal RB_MREQ : rb_mreq_type := rb_mreq_init;`
192			`signal RB_SRES : rb_sres_type := rb_sres_init;`
193			`signal RB_SRES_CPU : rb_sres_type := rb_sres_init;`
194			`signal RB_SRES_IBD : rb_sres_type := rb_sres_init;`
195
196			`signal RESET : slbit := '0';`
197			`signal CE_USEC : slbit := '0';`
198			`signal CE_MSEC : slbit := '0';`
199
200			`signal CPU_RESET : slbit := '0';`
201			`signal CP_CNTL : cp_cntl_type := cp_cntl_init;`
202			`signal CP_ADDR : cp_addr_type := cp_addr_init;`
203			`signal CP_DIN : slv16 := (others=>'0');`
204			`signal CP_STAT : cp_stat_type := cp_stat_init;`
205			`signal CP_DOUT : slv16 := (others=>'0');`
206
207			`signal EI_PRI : slv3 := (others=>'0');`
208			`signal EI_VECT : slv9_2 := (others=>'0');`
209			`signal EI_ACKM : slbit := '0';`
210
211			`signal EM_MREQ : em_mreq_type := em_mreq_init;`
212			`signal EM_SRES : em_sres_type := em_sres_init;`
213
214			`signal HM_ENA : slbit := '0';`
215			`signal MEM70_FMISS : slbit := '0';`
216			`signal CACHE_FMISS : slbit := '0';`
217			`signal CACHE_CHIT : slbit := '0';`
218
219			`signal MEM_REQ : slbit := '0';`
220			`signal MEM_WE : slbit := '0';`
221			`signal MEM_BUSY : slbit := '0';`
222			`signal MEM_ACK_R : slbit := '0';`
223			`signal MEM_ADDR : slv20 := (others=>'0');`
224			`signal MEM_BE : slv4 := (others=>'0');`
225			`signal MEM_DI : slv32 := (others=>'0');`
226			`signal MEM_DO : slv32 := (others=>'0');`
227
228			`signal BRESET : slbit := '0';`
229			`signal IB_MREQ : ib_mreq_type := ib_mreq_init;`
230			`signal IB_SRES : ib_sres_type := ib_sres_init;`
231
232			`signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;`
233			`signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;`
234
235			`signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;`
236			`signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;`
237			`signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;`
238			`signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;`
239
240			`signal DISPREG : slv16 := (others=>'0');`
241
242			`constant rbaddr_core0 : slv8 := "00000000";`
243			`constant rbaddr_ibus : slv8 := "10000000";`
244			`constant rbaddr_hio : slv8 := "11000000";`
245
246			`begin`
247
248	8	wfjm	`CLK <= I_CLK50; -- use 50MHz as system clock`
249
250	2	wfjm	`CLKDIV : clkdivce`
251			`generic map (`
252			`CDUWIDTH => 6,`
253			`USECDIV => 50,`
254			`MSECDIV => 1000)`
255			`port map (`
256			`CLK => CLK,`
257			`CE_USEC => CE_USEC,`
258			`CE_MSEC => CE_MSEC`
259			`);`
260
261	12	wfjm	`IOB_RS232 : bp_rs232_2l4l_iob`
262	2	wfjm	`port map (`
263			`CLK => CLK,`
264	12	wfjm	`RESET => '0',`
265	2	wfjm	`SEL => SWI(0),`
266			`RXD => RXD,`
267			`TXD => TXD,`
268			`CTS_N => CTS_N,`
269			`RTS_N => RTS_N,`
270			`I_RXD0 => I_RXD,`
271			`O_TXD0 => O_TXD,`
272			`I_RXD1 => I_FUSP_RXD,`
273			`O_TXD1 => O_FUSP_TXD,`
274			`I_CTS1_N => I_FUSP_CTS_N,`
275			`O_RTS1_N => O_FUSP_RTS_N`
276			`);`
277
278	12	wfjm	`HIO : sn_humanio`
279	2	wfjm	`generic map (`
280			`DEBOUNCE => sys_conf_hio_debounce)`
281			`port map (`
282			`CLK => CLK,`
283			`RESET => RESET,`
284			`CE_MSEC => CE_MSEC,`
285			`SWI => SWI,`
286			`BTN => BTN,`
287			`LED => LED,`
288			`DSP_DAT => DSP_DAT,`
289			`DSP_DP => DSP_DP,`
290			`I_SWI => I_SWI,`
291			`I_BTN => I_BTN,`
292			`O_LED => O_LED,`
293			`O_ANO_N => O_ANO_N,`
294			`O_SEG_N => O_SEG_N`
295			`);`
296
297	9	wfjm	`RLINK : rlink_base_serport`
298	2	wfjm	`generic map (`
299			`ATOWIDTH => 6, -- 64 cycles access timeout`
300			`ITOWIDTH => 6, -- 64 periods max idle timeout`
301	9	wfjm	`IFAWIDTH => 5, -- 32 word input fifo`
302			`OFAWIDTH => 0, -- no output fifo`
303	2	wfjm	`CDWIDTH => 13,`
304			`CDINIT => sys_conf_ser2rri_cdinit)`
305			`port map (`
306			`CLK => CLK,`
307			`CE_USEC => CE_USEC,`
308			`CE_MSEC => CE_MSEC,`
309			`CE_INT => CE_MSEC,`
310			`RESET => RESET,`
311			`RXSD => RXD,`
312			`TXSD => TXD,`
313			`CTS_N => CTS_N,`
314			`RTS_N => RTS_N,`
315			`RB_MREQ => RB_MREQ,`
316			`RB_SRES => RB_SRES,`
317			`RB_LAM => RB_LAM,`
318	9	wfjm	`RB_STAT => RB_STAT,`
319			`RL_MONI => open,`
320			`RL_SER_MONI => open`
321	2	wfjm	`);`
322
323			`RB_SRES_OR : rb_sres_or_2`
324			`port map (`
325			`RB_SRES_1 => RB_SRES_CPU,`
326			`RB_SRES_2 => RB_SRES_IBD,`
327			`RB_SRES_OR => RB_SRES`
328			`);`
329
330	9	wfjm	`RP2CP : pdp11_core_rbus`
331	2	wfjm	`generic map (`
332			`RB_ADDR_CORE => rbaddr_core0,`
333			`RB_ADDR_IBUS => rbaddr_ibus)`
334			`port map (`
335			`CLK => CLK,`
336			`RESET => RESET,`
337			`RB_MREQ => RB_MREQ,`
338			`RB_SRES => RB_SRES_CPU,`
339			`RB_STAT => RB_STAT,`
340	8	wfjm	`RB_LAM => RB_LAM(0),`
341	2	wfjm	`CPU_RESET => CPU_RESET,`
342			`CP_CNTL => CP_CNTL,`
343			`CP_ADDR => CP_ADDR,`
344			`CP_DIN => CP_DIN,`
345			`CP_STAT => CP_STAT,`
346			`CP_DOUT => CP_DOUT`
347			`);`
348
349			`CORE : pdp11_core`
350			`port map (`
351			`CLK => CLK,`
352			`RESET => CPU_RESET,`
353			`CP_CNTL => CP_CNTL,`
354			`CP_ADDR => CP_ADDR,`
355			`CP_DIN => CP_DIN,`
356			`CP_STAT => CP_STAT,`
357			`CP_DOUT => CP_DOUT,`
358			`EI_PRI => EI_PRI,`
359			`EI_VECT => EI_VECT,`
360			`EI_ACKM => EI_ACKM,`
361			`EM_MREQ => EM_MREQ,`
362			`EM_SRES => EM_SRES,`
363			`BRESET => BRESET,`
364			`IB_MREQ_M => IB_MREQ,`
365			`IB_SRES_M => IB_SRES,`
366			`DM_STAT_DP => DM_STAT_DP,`
367			`DM_STAT_VM => DM_STAT_VM,`
368			`DM_STAT_CO => DM_STAT_CO`
369			`);`
370
371			`MEM_BRAM: if sys_conf_bram > 0 generate`
372			`signal HM_VAL_BRAM : slbit := '0';`
373			`begin`
374
375			`MEM : pdp11_bram`
376			`generic map (`
377			`AWIDTH => sys_conf_bram_awidth)`
378			`port map (`
379			`CLK => CLK,`
380			`GRESET => CPU_RESET,`
381			`EM_MREQ => EM_MREQ,`
382			`EM_SRES => EM_SRES`
383			`);`
384
385			`HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write`
386
387			`MEM70: pdp11_mem70`
388			`port map (`
389			`CLK => CLK,`
390			`CRESET => BRESET,`
391			`HM_ENA => EM_MREQ.req,`
392			`HM_VAL => HM_VAL_BRAM,`
393			`CACHE_FMISS => MEM70_FMISS,`
394			`IB_MREQ => IB_MREQ,`
395			`IB_SRES => IB_SRES_MEM70`
396			`);`
397
398			`SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy`
399			`port map (`
400			`O_MEM_CE_N => O_MEM_CE_N,`
401			`O_MEM_BE_N => O_MEM_BE_N,`
402			`O_MEM_WE_N => O_MEM_WE_N,`
403			`O_MEM_OE_N => O_MEM_OE_N,`
404			`O_MEM_ADDR => O_MEM_ADDR,`
405			`IO_MEM_DATA => IO_MEM_DATA`
406			`);`
407
408			`end generate MEM_BRAM;`
409
410			`MEM_SRAM: if sys_conf_bram = 0 generate`
411
412			`CACHE: pdp11_cache`
413			`port map (`
414			`CLK => CLK,`
415			`GRESET => CPU_RESET,`
416			`EM_MREQ => EM_MREQ,`
417			`EM_SRES => EM_SRES,`
418			`FMISS => CACHE_FMISS,`
419			`CHIT => CACHE_CHIT,`
420			`MEM_REQ => MEM_REQ,`
421			`MEM_WE => MEM_WE,`
422			`MEM_BUSY => MEM_BUSY,`
423			`MEM_ACK_R => MEM_ACK_R,`
424			`MEM_ADDR => MEM_ADDR,`
425			`MEM_BE => MEM_BE,`
426			`MEM_DI => MEM_DI,`
427			`MEM_DO => MEM_DO`
428			`);`
429
430			`MEM70: pdp11_mem70`
431			`port map (`
432			`CLK => CLK,`
433			`CRESET => BRESET,`
434			`HM_ENA => HM_ENA,`
435			`HM_VAL => CACHE_CHIT,`
436			`CACHE_FMISS => MEM70_FMISS,`
437			`IB_MREQ => IB_MREQ,`
438			`IB_SRES => IB_SRES_MEM70`
439			`);`
440
441			`HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;`
442			`CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;`
443
444			`SRAM_CTL: s3_sram_memctl`
445			`port map (`
446			`CLK => CLK,`
447			`RESET => CPU_RESET,`
448			`REQ => MEM_REQ,`
449			`WE => MEM_WE,`
450			`BUSY => MEM_BUSY,`
451			`ACK_R => MEM_ACK_R,`
452			`ACK_W => open,`
453			`ACT_R => open,`
454			`ACT_W => open,`
455			`ADDR => MEM_ADDR(17 downto 0),`
456			`BE => MEM_BE,`
457			`DI => MEM_DI,`
458			`DO => MEM_DO,`
459			`O_MEM_CE_N => O_MEM_CE_N,`
460			`O_MEM_BE_N => O_MEM_BE_N,`
461			`O_MEM_WE_N => O_MEM_WE_N,`
462			`O_MEM_OE_N => O_MEM_OE_N,`
463			`O_MEM_ADDR => O_MEM_ADDR,`
464			`IO_MEM_DATA => IO_MEM_DATA`
465			`);`
466
467			`end generate MEM_SRAM;`
468
469			`IB_SRES_OR : ib_sres_or_2`
470			`port map (`
471			`IB_SRES_1 => IB_SRES_MEM70,`
472			`IB_SRES_2 => IB_SRES_IBDR,`
473			`IB_SRES_OR => IB_SRES);`
474
475			`IBD_MINI : if false generate`
476			`begin`
477			`IBDR_SYS : ibdr_minisys`
478			`port map (`
479			`CLK => CLK,`
480			`CE_USEC => CE_USEC,`
481			`CE_MSEC => CE_MSEC,`
482			`RESET => CPU_RESET,`
483			`BRESET => BRESET,`
484	8	wfjm	`RB_LAM => RB_LAM(15 downto 1),`
485	2	wfjm	`IB_MREQ => IB_MREQ,`
486			`IB_SRES => IB_SRES_IBDR,`
487			`EI_ACKM => EI_ACKM,`
488			`EI_PRI => EI_PRI,`
489			`EI_VECT => EI_VECT,`
490			`DISPREG => DISPREG);`
491			`end generate IBD_MINI;`
492
493			`IBD_MAXI : if true generate`
494			`begin`
495			`IBDR_SYS : ibdr_maxisys`
496			`port map (`
497			`CLK => CLK,`
498			`CE_USEC => CE_USEC,`
499			`CE_MSEC => CE_MSEC,`
500			`RESET => CPU_RESET,`

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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [sys_gen/] [w11a/] [s3board/] [sys_w11a_s3.vhd] - Blame information for rev 13