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-- $Id: gray_cnt_4.vhd 418 2011-10-23 20:11:40Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: gray_cnt_4 - syn
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-- Description: 4 bit Gray code counter (ROM based)
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-26 106 1.0 Initial version
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--
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-- Some synthesis results:
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-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
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-- LUT Flop clock(xst est.)
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-- 4 4 365MHz/ 2.76ns
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv4 -- data out
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);
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end entity gray_cnt_4;
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architecture syn of gray_cnt_4 is
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signal R_DATA : slv4 := (others=>'0');
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signal N_DATA : slv4 := (others=>'0');
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-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
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-- inferred. For 4 bit the coding was 'Gray', but see remarks in
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-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
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attribute fsm_extract : string;
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attribute fsm_extract of R_DATA : signal is "no";
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attribute rom_style : string;
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attribute rom_style of N_DATA : signal is "distributed";
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_DATA <= (others=>'0');
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elsif CE = '1' then
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R_DATA <= N_DATA;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_DATA)
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begin
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N_DATA <= (others=>'0');
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case R_DATA is
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when "0000" => N_DATA <= "0001"; -- 0
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when "0001" => N_DATA <= "0011"; -- 1
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when "0011" => N_DATA <= "0010"; -- 2
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when "0010" => N_DATA <= "0110"; -- 3
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when "0110" => N_DATA <= "0111"; -- 4
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when "0111" => N_DATA <= "0101"; -- 5
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when "0101" => N_DATA <= "0100"; -- 6
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when "0100" => N_DATA <= "1100"; -- 7
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when "1100" => N_DATA <= "1101"; -- 8
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when "1101" => N_DATA <= "1111"; -- 9
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when "1111" => N_DATA <= "1110"; -- 10
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when "1110" => N_DATA <= "1010"; -- 11
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when "1010" => N_DATA <= "1011"; -- 12
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when "1011" => N_DATA <= "1001"; -- 13
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when "1001" => N_DATA <= "1000"; -- 14
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when "1000" => N_DATA <= "0000"; -- 15
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when others => null;
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end case;
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end process proc_next;
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DATA <= R_DATA;
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end syn;
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