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-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name:    ram_1swsr_xfirst_gen_unisim - syn
-- Description:    Single-Port RAM with with one synchronous read/write port
--                 Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies:   -
-- Test bench:     -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History: 
-- Date         Rev Version  Comment
-- 2008-04-13   135   1.0.1  fix range error for AW_14_S1
-- 2008-03-08   123   1.0    Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_1swsr_xfirst_gen_unisim is   -- RAM, 1 sync r/w ports
  generic (
    AWIDTH : positive := 11;            -- address port width
    DWIDTH : positive :=  9;            -- data port width
    WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
  port(
    CLK   : in slbit;                   -- clock
    EN    : in slbit;                   -- enable
    WE    : in slbit;                   -- write enable
    ADDR  : in slv(AWIDTH-1 downto 0);  -- address
    DI    : in slv(DWIDTH-1 downto 0);  -- data in
    DO    : out slv(DWIDTH-1 downto 0)  -- data out
  );
end ram_1swsr_xfirst_gen_unisim;
 
 
architecture syn of ram_1swsr_xfirst_gen_unisim is
 
  constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+35)/36)=((DWIDTH+31)/32);
  constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
                                 ((DWIDTH+17)/18)=((DWIDTH+16)/16);
  constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+8)/9)=((DWIDTH+7)/8);
 
begin
 
  assert AWIDTH>=9 and AWIDTH<=14
    report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
    severity failure;
 
  AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
    constant dw_mem : positive := ((DWIDTH+35)/36)*36;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DI(DI'range) <= DI;
 
   GL: for i in dw_mem/36-1 downto 0 generate
      MEM : RAMB16_S36
        generic map (
          INIT       => O"000000000000",
          SRVAL      => O"000000000000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(36*i+31 downto 36*i),
          DOP  => L_DO(36*i+35 downto 36*i+32),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(36*i+31 downto 36*i),
          DIP  => L_DI(36*i+35 downto 36*i+32),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_09_S36;
 
  AW_09_S32: if AWIDTH=9 and ok_mod32 generate
    GL: for i in DWIDTH/32-1 downto 0 generate
      MEM : RAMB16_S36
        generic map (
          INIT       => X"00000000",
          SRVAL      => X"00000000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(32*i+31 downto 32*i),
          DOP  => open,
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(32*i+31 downto 32*i),
          DIP  => "0000",
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_09_S32;
 
  AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
    constant dw_mem : positive := ((DWIDTH+17)/18)*18;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/18-1 downto 0 generate
      MEM : RAMB16_S18
        generic map (
          INIT       => O"000000",
          SRVAL      => O"000000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(18*i+15 downto 18*i),
          DOP  => L_DO(18*i+17 downto 18*i+16),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(18*i+15 downto 18*i),
          DIP  => L_DI(18*i+17 downto 18*i+16),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_10_S18;
 
  AW_10_S16: if AWIDTH=10 and ok_mod16 generate
    GL: for i in DWIDTH/16-1 downto 0 generate
      MEM : RAMB16_S18
        generic map (
          INIT       => X"0000",
          SRVAL      => X"0000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(16*i+15 downto 16*i),
          DOP  => open,
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(16*i+15 downto 16*i),
          DIP  => "00",
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_10_S16;
 
  AW_11_S9: if AWIDTH=11  and not ok_mod08 generate
    constant dw_mem : positive := ((DWIDTH+8)/9)*9;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/9-1 downto 0 generate
      MEM : RAMB16_S9
        generic map (
          INIT       => O"000",
          SRVAL      => O"000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(9*i+7 downto 9*i),
          DOP  => L_DO(9*i+8 downto 9*i+8),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(9*i+7 downto 9*i),
          DIP  => L_DI(9*i+8 downto 9*i+8),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_11_S9;
 
  AW_11_S8: if AWIDTH=11 and ok_mod08 generate
    GL: for i in DWIDTH/8-1 downto 0 generate
      MEM : RAMB16_S9
        generic map (
          INIT       => X"00",
          SRVAL      => X"00",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(8*i+7 downto 8*i),
          DOP  => open,
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(8*i+7 downto 8*i),
          DIP  => "0",
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_11_S8;
 
  AW_12_S4: if AWIDTH = 12 generate
    constant dw_mem : positive := ((DWIDTH+3)/4)*4;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/4-1 downto 0 generate
      MEM : RAMB16_S4
        generic map (
          INIT       => X"0",
          SRVAL      => X"0",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(4*i+3 downto 4*i),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(4*i+3 downto 4*i),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_12_S4;
 
  AW_13_S2: if AWIDTH = 13 generate
    constant dw_mem : positive := ((DWIDTH+1)/2)*2;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/2-1 downto 0 generate
      MEM : RAMB16_S2
        generic map (
          INIT       => "00",
          SRVAL      => "00",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(2*i+1 downto 2*i),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(2*i+1 downto 2*i),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_13_S2;
 
  AW_14_S1: if AWIDTH = 14 generate
    GL: for i in DWIDTH-1 downto 0 generate
      MEM : RAMB16_S1
        generic map (
          INIT       => "0",
          SRVAL      => "0",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(i downto i),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(i downto i),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_14_S1;
 
 
end syn;
 
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
--       nonsense:  INIT_A : bit_vector := X"000";
--       This is a 12 bit value, while a 9 bit one is needed. Thus the
--       explicit definition above.

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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [memlib/] [ram_1swsr_xfirst_gen_unisim.vhd] - Blame information for rev 10

Line No.	Rev	Author	Line
1	10	wfjm	`-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $`
2			`--`
3			`-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Module Name: ram_1swsr_xfirst_gen_unisim - syn`
16			`-- Description: Single-Port RAM with with one synchronous read/write port`
17			`-- Direct instantiation of Xilinx UNISIM primitives`
18			`--`
19			`-- Dependencies: -`
20			`-- Test bench: -`
21			`-- Target Devices: Spartan-3, Virtex-2,-4`
22			`-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25`
23			`-- Revision History:`
24			`-- Date Rev Version Comment`
25			`-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1`
26			`-- 2008-03-08 123 1.0 Initial version`
27			`------------------------------------------------------------------------------`
28
29			`library ieee;`
30			`use ieee.std_logic_1164.all;`
31
32			`library unisim;`
33			`use unisim.vcomponents.ALL;`
34
35			`use work.slvtypes.all;`
36
37			`entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports`
38			`generic (`
39			`AWIDTH : positive := 11; -- address port width`
40			`DWIDTH : positive := 9; -- data port width`
41			`WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ\|WRITE)_FIRST`
42			`port(`
43			`CLK : in slbit; -- clock`
44			`EN : in slbit; -- enable`
45			`WE : in slbit; -- write enable`
46			`ADDR : in slv(AWIDTH-1 downto 0); -- address`
47			`DI : in slv(DWIDTH-1 downto 0); -- data in`
48			`DO : out slv(DWIDTH-1 downto 0) -- data out`
49			`);`
50			`end ram_1swsr_xfirst_gen_unisim;`
51
52
53			`architecture syn of ram_1swsr_xfirst_gen_unisim is`
54
55			`constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and`
56			`((DWIDTH+35)/36)=((DWIDTH+31)/32);`
57			`constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and`
58			`((DWIDTH+17)/18)=((DWIDTH+16)/16);`
59			`constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and`
60			`((DWIDTH+8)/9)=((DWIDTH+7)/8);`
61
62			`begin`
63
64			`assert AWIDTH>=9 and AWIDTH<=14`
65			`report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"`
66			`severity failure;`
67
68			`AW_09_S36: if AWIDTH=9 and not ok_mod32 generate`
69			`constant dw_mem : positive := ((DWIDTH+35)/36)*36;`
70			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
71			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
72			`begin`
73
74			`L_DI(DI'range) <= DI;`
75
76			`GL: for i in dw_mem/36-1 downto 0 generate`
77			`MEM : RAMB16_S36`
78			`generic map (`
79			`INIT => O"000000000000",`
80			`SRVAL => O"000000000000",`
81			`WRITE_MODE => WRITE_MODE)`
82			`port map (`
83			`DO => L_DO(36i+31 downto 36i),`
84			`DOP => L_DO(36i+35 downto 36i+32),`
85			`ADDR => ADDR,`
86			`CLK => CLK,`
87			`DI => L_DI(36i+31 downto 36i),`
88			`DIP => L_DI(36i+35 downto 36i+32),`
89			`EN => EN,`
90			`SSR => '0',`
91			`WE => WE`
92			`);`
93			`end generate GL;`
94
95			`DO <= L_DO(DO'range);`
96
97			`end generate AW_09_S36;`
98
99			`AW_09_S32: if AWIDTH=9 and ok_mod32 generate`
100			`GL: for i in DWIDTH/32-1 downto 0 generate`
101			`MEM : RAMB16_S36`
102			`generic map (`
103			`INIT => X"00000000",`
104			`SRVAL => X"00000000",`
105			`WRITE_MODE => WRITE_MODE)`
106			`port map (`
107			`DO => DO(32i+31 downto 32i),`
108			`DOP => open,`
109			`ADDR => ADDR,`
110			`CLK => CLK,`
111			`DI => DI(32i+31 downto 32i),`
112			`DIP => "0000",`
113			`EN => EN,`
114			`SSR => '0',`
115			`WE => WE`
116			`);`
117			`end generate GL;`
118			`end generate AW_09_S32;`
119
120			`AW_10_S18: if AWIDTH=10 and not ok_mod16 generate`
121			`constant dw_mem : positive := ((DWIDTH+17)/18)*18;`
122			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
123			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
124			`begin`
125
126			`L_DI(DI'range) <= DI;`
127
128			`GL: for i in dw_mem/18-1 downto 0 generate`
129			`MEM : RAMB16_S18`
130			`generic map (`
131			`INIT => O"000000",`
132			`SRVAL => O"000000",`
133			`WRITE_MODE => WRITE_MODE)`
134			`port map (`
135			`DO => L_DO(18i+15 downto 18i),`
136			`DOP => L_DO(18i+17 downto 18i+16),`
137			`ADDR => ADDR,`
138			`CLK => CLK,`
139			`DI => L_DI(18i+15 downto 18i),`
140			`DIP => L_DI(18i+17 downto 18i+16),`
141			`EN => EN,`
142			`SSR => '0',`
143			`WE => WE`
144			`);`
145			`end generate GL;`
146
147			`DO <= L_DO(DO'range);`
148
149			`end generate AW_10_S18;`
150
151			`AW_10_S16: if AWIDTH=10 and ok_mod16 generate`
152			`GL: for i in DWIDTH/16-1 downto 0 generate`
153			`MEM : RAMB16_S18`
154			`generic map (`
155			`INIT => X"0000",`
156			`SRVAL => X"0000",`
157			`WRITE_MODE => WRITE_MODE)`
158			`port map (`
159			`DO => DO(16i+15 downto 16i),`
160			`DOP => open,`
161			`ADDR => ADDR,`
162			`CLK => CLK,`
163			`DI => DI(16i+15 downto 16i),`
164			`DIP => "00",`
165			`EN => EN,`
166			`SSR => '0',`
167			`WE => WE`
168			`);`
169			`end generate GL;`
170			`end generate AW_10_S16;`
171
172			`AW_11_S9: if AWIDTH=11 and not ok_mod08 generate`
173			`constant dw_mem : positive := ((DWIDTH+8)/9)*9;`
174			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
175			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
176			`begin`
177
178			`L_DI(DI'range) <= DI;`
179
180			`GL: for i in dw_mem/9-1 downto 0 generate`
181			`MEM : RAMB16_S9`
182			`generic map (`
183			`INIT => O"000",`
184			`SRVAL => O"000",`
185			`WRITE_MODE => WRITE_MODE)`
186			`port map (`
187			`DO => L_DO(9i+7 downto 9i),`
188			`DOP => L_DO(9i+8 downto 9i+8),`
189			`ADDR => ADDR,`
190			`CLK => CLK,`
191			`DI => L_DI(9i+7 downto 9i),`
192			`DIP => L_DI(9i+8 downto 9i+8),`
193			`EN => EN,`
194			`SSR => '0',`
195			`WE => WE`
196			`);`
197			`end generate GL;`
198
199			`DO <= L_DO(DO'range);`
200
201			`end generate AW_11_S9;`
202
203			`AW_11_S8: if AWIDTH=11 and ok_mod08 generate`
204			`GL: for i in DWIDTH/8-1 downto 0 generate`
205			`MEM : RAMB16_S9`
206			`generic map (`
207			`INIT => X"00",`
208			`SRVAL => X"00",`
209			`WRITE_MODE => WRITE_MODE)`
210			`port map (`
211			`DO => DO(8i+7 downto 8i),`
212			`DOP => open,`
213			`ADDR => ADDR,`
214			`CLK => CLK,`
215			`DI => DI(8i+7 downto 8i),`
216			`DIP => "0",`
217			`EN => EN,`
218			`SSR => '0',`
219			`WE => WE`
220			`);`
221			`end generate GL;`
222			`end generate AW_11_S8;`
223
224			`AW_12_S4: if AWIDTH = 12 generate`
225			`constant dw_mem : positive := ((DWIDTH+3)/4)*4;`
226			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
227			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
228			`begin`
229
230			`L_DI(DI'range) <= DI;`
231
232			`GL: for i in dw_mem/4-1 downto 0 generate`
233			`MEM : RAMB16_S4`
234			`generic map (`
235			`INIT => X"0",`
236			`SRVAL => X"0",`
237			`WRITE_MODE => WRITE_MODE)`
238			`port map (`
239			`DO => L_DO(4i+3 downto 4i),`
240			`ADDR => ADDR,`
241			`CLK => CLK,`
242			`DI => L_DI(4i+3 downto 4i),`
243			`EN => EN,`
244			`SSR => '0',`
245			`WE => WE`
246			`);`
247			`end generate GL;`
248
249			`DO <= L_DO(DO'range);`
250
251			`end generate AW_12_S4;`
252
253			`AW_13_S2: if AWIDTH = 13 generate`
254			`constant dw_mem : positive := ((DWIDTH+1)/2)*2;`
255			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
256			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
257			`begin`
258
259			`L_DI(DI'range) <= DI;`
260
261			`GL: for i in dw_mem/2-1 downto 0 generate`
262			`MEM : RAMB16_S2`
263			`generic map (`
264			`INIT => "00",`
265			`SRVAL => "00",`
266			`WRITE_MODE => WRITE_MODE)`
267			`port map (`
268			`DO => L_DO(2i+1 downto 2i),`
269			`ADDR => ADDR,`
270			`CLK => CLK,`
271			`DI => L_DI(2i+1 downto 2i),`
272			`EN => EN,`
273			`SSR => '0',`
274			`WE => WE`
275			`);`
276			`end generate GL;`
277
278			`DO <= L_DO(DO'range);`
279
280			`end generate AW_13_S2;`
281
282			`AW_14_S1: if AWIDTH = 14 generate`
283			`GL: for i in DWIDTH-1 downto 0 generate`
284			`MEM : RAMB16_S1`
285			`generic map (`
286			`INIT => "0",`
287			`SRVAL => "0",`
288			`WRITE_MODE => WRITE_MODE)`
289			`port map (`
290			`DO => DO(i downto i),`
291			`ADDR => ADDR,`
292			`CLK => CLK,`
293			`DI => DI(i downto i),`
294			`EN => EN,`
295			`SSR => '0',`
296			`WE => WE`
297			`);`
298			`end generate GL;`
299			`end generate AW_14_S1;`
300
301
302			`end syn;`
303
304			`-- Note: in XST 8.2 the defaults for INIT_(A\|B) and SRVAL_(A\|B) are`
305			`-- nonsense: INIT_A : bit_vector := X"000";`
306			`-- This is a 12 bit value, while a 9 bit one is needed. Thus the`
307			`-- explicit definition above.`