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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [memlib/] [ram_1swsr_xfirst_gen_unisim.vhd] - Blame information for rev 12

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-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name:    ram_1swsr_xfirst_gen_unisim - syn
-- Description:    Single-Port RAM with with one synchronous read/write port
--                 Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies:   -
-- Test bench:     -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History: 
-- Date         Rev Version  Comment
-- 2011-08-14   406   1.0.2  cleaner code for L_DI initialization
-- 2008-04-13   135   1.0.1  fix range error for AW_14_S1
-- 2008-03-08   123   1.0    Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_1swsr_xfirst_gen_unisim is   -- RAM, 1 sync r/w ports
  generic (
    AWIDTH : positive := 11;            -- address port width
    DWIDTH : positive :=  9;            -- data port width
    WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
  port(
    CLK   : in slbit;                   -- clock
    EN    : in slbit;                   -- enable
    WE    : in slbit;                   -- write enable
    ADDR  : in slv(AWIDTH-1 downto 0);  -- address
    DI    : in slv(DWIDTH-1 downto 0);  -- data in
    DO    : out slv(DWIDTH-1 downto 0)  -- data out
  );
end ram_1swsr_xfirst_gen_unisim;
 
 
architecture syn of ram_1swsr_xfirst_gen_unisim is
 
  constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+35)/36)=((DWIDTH+31)/32);
  constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
                                 ((DWIDTH+17)/18)=((DWIDTH+16)/16);
  constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+8)/9)=((DWIDTH+7)/8);
 
begin
 
  assert AWIDTH>=9 and AWIDTH<=14
    report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
    severity failure;
 
  AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
    constant dw_mem : positive := ((DWIDTH+35)/36)*36;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DI(DI'range) <= DI;
 
   GL: for i in dw_mem/36-1 downto 0 generate
      MEM : RAMB16_S36
        generic map (
          INIT       => O"000000000000",
          SRVAL      => O"000000000000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(36*i+31 downto 36*i),
          DOP  => L_DO(36*i+35 downto 36*i+32),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(36*i+31 downto 36*i),
          DIP  => L_DI(36*i+35 downto 36*i+32),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_09_S36;
 
  AW_09_S32: if AWIDTH=9 and ok_mod32 generate
    GL: for i in DWIDTH/32-1 downto 0 generate
      MEM : RAMB16_S36
        generic map (
          INIT       => X"00000000",
          SRVAL      => X"00000000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(32*i+31 downto 32*i),
          DOP  => open,
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(32*i+31 downto 32*i),
          DIP  => "0000",
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_09_S32;
 
  AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
    constant dw_mem : positive := ((DWIDTH+17)/18)*18;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/18-1 downto 0 generate
      MEM : RAMB16_S18
        generic map (
          INIT       => O"000000",
          SRVAL      => O"000000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(18*i+15 downto 18*i),
          DOP  => L_DO(18*i+17 downto 18*i+16),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(18*i+15 downto 18*i),
          DIP  => L_DI(18*i+17 downto 18*i+16),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_10_S18;
 
  AW_10_S16: if AWIDTH=10 and ok_mod16 generate
    GL: for i in DWIDTH/16-1 downto 0 generate
      MEM : RAMB16_S18
        generic map (
          INIT       => X"0000",
          SRVAL      => X"0000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(16*i+15 downto 16*i),
          DOP  => open,
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(16*i+15 downto 16*i),
          DIP  => "00",
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_10_S16;
 
  AW_11_S9: if AWIDTH=11  and not ok_mod08 generate
    constant dw_mem : positive := ((DWIDTH+8)/9)*9;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/9-1 downto 0 generate
      MEM : RAMB16_S9
        generic map (
          INIT       => O"000",
          SRVAL      => O"000",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(9*i+7 downto 9*i),
          DOP  => L_DO(9*i+8 downto 9*i+8),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(9*i+7 downto 9*i),
          DIP  => L_DI(9*i+8 downto 9*i+8),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_11_S9;
 
  AW_11_S8: if AWIDTH=11 and ok_mod08 generate
    GL: for i in DWIDTH/8-1 downto 0 generate
      MEM : RAMB16_S9
        generic map (
          INIT       => X"00",
          SRVAL      => X"00",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(8*i+7 downto 8*i),
          DOP  => open,
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(8*i+7 downto 8*i),
          DIP  => "0",
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_11_S8;
 
  AW_12_S4: if AWIDTH = 12 generate
    constant dw_mem : positive := ((DWIDTH+3)/4)*4;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/4-1 downto 0 generate
      MEM : RAMB16_S4
        generic map (
          INIT       => X"0",
          SRVAL      => X"0",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(4*i+3 downto 4*i),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(4*i+3 downto 4*i),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_12_S4;
 
  AW_13_S2: if AWIDTH = 13 generate
    constant dw_mem : positive := ((DWIDTH+1)/2)*2;
    signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DI(DI'range) <= DI;
 
    GL: for i in dw_mem/2-1 downto 0 generate
      MEM : RAMB16_S2
        generic map (
          INIT       => "00",
          SRVAL      => "00",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => L_DO(2*i+1 downto 2*i),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => L_DI(2*i+1 downto 2*i),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
 
    DO <= L_DO(DO'range);
 
  end generate AW_13_S2;
 
  AW_14_S1: if AWIDTH = 14 generate
    GL: for i in DWIDTH-1 downto 0 generate
      MEM : RAMB16_S1
        generic map (
          INIT       => "0",
          SRVAL      => "0",
          WRITE_MODE => WRITE_MODE)
        port map (
          DO   => DO(i downto i),
          ADDR => ADDR,
          CLK  => CLK,
          DI   => DI(i downto i),
          EN   => EN,
          SSR  => '0',
          WE   => WE
        );
    end generate GL;
  end generate AW_14_S1;
 
 
end syn;
 
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
--       nonsense:  INIT_A : bit_vector := X"000";
--       This is a 12 bit value, while a 9 bit one is needed. Thus the
--       explicit definition above.

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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [memlib/] [ram_1swsr_xfirst_gen_unisim.vhd] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	wfjm	`-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $`
2	10	wfjm	`--`
3	12	wfjm	`-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4	10	wfjm	`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Module Name: ram_1swsr_xfirst_gen_unisim - syn`
16			`-- Description: Single-Port RAM with with one synchronous read/write port`
17			`-- Direct instantiation of Xilinx UNISIM primitives`
18			`--`
19			`-- Dependencies: -`
20			`-- Test bench: -`
21			`-- Target Devices: Spartan-3, Virtex-2,-4`
22	12	wfjm	`-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25`
23	10	wfjm	`-- Revision History:`
24			`-- Date Rev Version Comment`
25	12	wfjm	`-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization`
26	10	wfjm	`-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1`
27			`-- 2008-03-08 123 1.0 Initial version`
28			`------------------------------------------------------------------------------`
29
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32
33			`library unisim;`
34			`use unisim.vcomponents.ALL;`
35
36			`use work.slvtypes.all;`
37
38			`entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports`
39			`generic (`
40			`AWIDTH : positive := 11; -- address port width`
41			`DWIDTH : positive := 9; -- data port width`
42			`WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ\|WRITE)_FIRST`
43			`port(`
44			`CLK : in slbit; -- clock`
45			`EN : in slbit; -- enable`
46			`WE : in slbit; -- write enable`
47			`ADDR : in slv(AWIDTH-1 downto 0); -- address`
48			`DI : in slv(DWIDTH-1 downto 0); -- data in`
49			`DO : out slv(DWIDTH-1 downto 0) -- data out`
50			`);`
51			`end ram_1swsr_xfirst_gen_unisim;`
52
53
54			`architecture syn of ram_1swsr_xfirst_gen_unisim is`
55
56			`constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and`
57			`((DWIDTH+35)/36)=((DWIDTH+31)/32);`
58			`constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and`
59			`((DWIDTH+17)/18)=((DWIDTH+16)/16);`
60			`constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and`
61			`((DWIDTH+8)/9)=((DWIDTH+7)/8);`
62
63			`begin`
64
65			`assert AWIDTH>=9 and AWIDTH<=14`
66			`report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"`
67			`severity failure;`
68
69			`AW_09_S36: if AWIDTH=9 and not ok_mod32 generate`
70			`constant dw_mem : positive := ((DWIDTH+35)/36)*36;`
71			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
72			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
73			`begin`
74
75	12	wfjm	`DI_PAD: if dw_mem>DWIDTH generate`
76			`L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');`
77			`end generate DI_PAD;`
78	10	wfjm	`L_DI(DI'range) <= DI;`
79
80			`GL: for i in dw_mem/36-1 downto 0 generate`
81			`MEM : RAMB16_S36`
82			`generic map (`
83			`INIT => O"000000000000",`
84			`SRVAL => O"000000000000",`
85			`WRITE_MODE => WRITE_MODE)`
86			`port map (`
87			`DO => L_DO(36i+31 downto 36i),`
88			`DOP => L_DO(36i+35 downto 36i+32),`
89			`ADDR => ADDR,`
90			`CLK => CLK,`
91			`DI => L_DI(36i+31 downto 36i),`
92			`DIP => L_DI(36i+35 downto 36i+32),`
93			`EN => EN,`
94			`SSR => '0',`
95			`WE => WE`
96			`);`
97			`end generate GL;`
98
99			`DO <= L_DO(DO'range);`
100
101			`end generate AW_09_S36;`
102
103			`AW_09_S32: if AWIDTH=9 and ok_mod32 generate`
104			`GL: for i in DWIDTH/32-1 downto 0 generate`
105			`MEM : RAMB16_S36`
106			`generic map (`
107			`INIT => X"00000000",`
108			`SRVAL => X"00000000",`
109			`WRITE_MODE => WRITE_MODE)`
110			`port map (`
111			`DO => DO(32i+31 downto 32i),`
112			`DOP => open,`
113			`ADDR => ADDR,`
114			`CLK => CLK,`
115			`DI => DI(32i+31 downto 32i),`
116			`DIP => "0000",`
117			`EN => EN,`
118			`SSR => '0',`
119			`WE => WE`
120			`);`
121			`end generate GL;`
122			`end generate AW_09_S32;`
123
124			`AW_10_S18: if AWIDTH=10 and not ok_mod16 generate`
125			`constant dw_mem : positive := ((DWIDTH+17)/18)*18;`
126			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
127			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
128			`begin`
129	12	wfjm
130			`DI_PAD: if dw_mem>DWIDTH generate`
131			`L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');`
132			`end generate DI_PAD;`
133	10	wfjm	`L_DI(DI'range) <= DI;`
134
135			`GL: for i in dw_mem/18-1 downto 0 generate`
136			`MEM : RAMB16_S18`
137			`generic map (`
138			`INIT => O"000000",`
139			`SRVAL => O"000000",`
140			`WRITE_MODE => WRITE_MODE)`
141			`port map (`
142			`DO => L_DO(18i+15 downto 18i),`
143			`DOP => L_DO(18i+17 downto 18i+16),`
144			`ADDR => ADDR,`
145			`CLK => CLK,`
146			`DI => L_DI(18i+15 downto 18i),`
147			`DIP => L_DI(18i+17 downto 18i+16),`
148			`EN => EN,`
149			`SSR => '0',`
150			`WE => WE`
151			`);`
152			`end generate GL;`
153
154			`DO <= L_DO(DO'range);`
155
156			`end generate AW_10_S18;`
157
158			`AW_10_S16: if AWIDTH=10 and ok_mod16 generate`
159			`GL: for i in DWIDTH/16-1 downto 0 generate`
160			`MEM : RAMB16_S18`
161			`generic map (`
162			`INIT => X"0000",`
163			`SRVAL => X"0000",`
164			`WRITE_MODE => WRITE_MODE)`
165			`port map (`
166			`DO => DO(16i+15 downto 16i),`
167			`DOP => open,`
168			`ADDR => ADDR,`
169			`CLK => CLK,`
170			`DI => DI(16i+15 downto 16i),`
171			`DIP => "00",`
172			`EN => EN,`
173			`SSR => '0',`
174			`WE => WE`
175			`);`
176			`end generate GL;`
177			`end generate AW_10_S16;`
178
179			`AW_11_S9: if AWIDTH=11 and not ok_mod08 generate`
180			`constant dw_mem : positive := ((DWIDTH+8)/9)*9;`
181			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
182			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
183			`begin`
184
185	12	wfjm	`DI_PAD: if dw_mem>DWIDTH generate`
186			`L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');`
187			`end generate DI_PAD;`
188	10	wfjm	`L_DI(DI'range) <= DI;`
189
190			`GL: for i in dw_mem/9-1 downto 0 generate`
191			`MEM : RAMB16_S9`
192			`generic map (`
193			`INIT => O"000",`
194			`SRVAL => O"000",`
195			`WRITE_MODE => WRITE_MODE)`
196			`port map (`
197			`DO => L_DO(9i+7 downto 9i),`
198			`DOP => L_DO(9i+8 downto 9i+8),`
199			`ADDR => ADDR,`
200			`CLK => CLK,`
201			`DI => L_DI(9i+7 downto 9i),`
202			`DIP => L_DI(9i+8 downto 9i+8),`
203			`EN => EN,`
204			`SSR => '0',`
205			`WE => WE`
206			`);`
207			`end generate GL;`
208
209			`DO <= L_DO(DO'range);`
210
211			`end generate AW_11_S9;`
212
213			`AW_11_S8: if AWIDTH=11 and ok_mod08 generate`
214			`GL: for i in DWIDTH/8-1 downto 0 generate`
215			`MEM : RAMB16_S9`
216			`generic map (`
217			`INIT => X"00",`
218			`SRVAL => X"00",`
219			`WRITE_MODE => WRITE_MODE)`
220			`port map (`
221			`DO => DO(8i+7 downto 8i),`
222			`DOP => open,`
223			`ADDR => ADDR,`
224			`CLK => CLK,`
225			`DI => DI(8i+7 downto 8i),`
226			`DIP => "0",`
227			`EN => EN,`
228			`SSR => '0',`
229			`WE => WE`
230			`);`
231			`end generate GL;`
232			`end generate AW_11_S8;`
233
234			`AW_12_S4: if AWIDTH = 12 generate`
235			`constant dw_mem : positive := ((DWIDTH+3)/4)*4;`
236			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
237			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
238			`begin`
239
240	12	wfjm	`DI_PAD: if dw_mem>DWIDTH generate`
241			`L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');`
242			`end generate DI_PAD;`
243	10	wfjm	`L_DI(DI'range) <= DI;`
244
245			`GL: for i in dw_mem/4-1 downto 0 generate`
246			`MEM : RAMB16_S4`
247			`generic map (`
248			`INIT => X"0",`
249			`SRVAL => X"0",`
250			`WRITE_MODE => WRITE_MODE)`
251			`port map (`
252			`DO => L_DO(4i+3 downto 4i),`
253			`ADDR => ADDR,`
254			`CLK => CLK,`
255			`DI => L_DI(4i+3 downto 4i),`
256			`EN => EN,`
257			`SSR => '0',`
258			`WE => WE`
259			`);`
260			`end generate GL;`
261
262			`DO <= L_DO(DO'range);`
263
264			`end generate AW_12_S4;`
265
266			`AW_13_S2: if AWIDTH = 13 generate`
267			`constant dw_mem : positive := ((DWIDTH+1)/2)*2;`
268			`signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');`
269			`signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');`
270			`begin`
271
272	12	wfjm	`DI_PAD: if dw_mem>DWIDTH generate`
273			`L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');`
274			`end generate DI_PAD;`
275	10	wfjm	`L_DI(DI'range) <= DI;`
276
277			`GL: for i in dw_mem/2-1 downto 0 generate`
278			`MEM : RAMB16_S2`
279			`generic map (`
280			`INIT => "00",`
281			`SRVAL => "00",`
282			`WRITE_MODE => WRITE_MODE)`
283			`port map (`
284			`DO => L_DO(2i+1 downto 2i),`
285			`ADDR => ADDR,`
286			`CLK => CLK,`
287			`DI => L_DI(2i+1 downto 2i),`
288			`EN => EN,`
289			`SSR => '0',`
290			`WE => WE`
291			`);`
292			`end generate GL;`
293
294			`DO <= L_DO(DO'range);`
295
296			`end generate AW_13_S2;`
297
298			`AW_14_S1: if AWIDTH = 14 generate`
299			`GL: for i in DWIDTH-1 downto 0 generate`
300			`MEM : RAMB16_S1`
301			`generic map (`
302			`INIT => "0",`
303			`SRVAL => "0",`
304			`WRITE_MODE => WRITE_MODE)`
305			`port map (`
306			`DO => DO(i downto i),`
307			`ADDR => ADDR,`
308			`CLK => CLK,`
309			`DI => DI(i downto i),`
310			`EN => EN,`
311			`SSR => '0',`
312			`WE => WE`
313			`);`
314			`end generate GL;`
315			`end generate AW_14_S1;`
316
317
318			`end syn;`
319
320			`-- Note: in XST 8.2 the defaults for INIT_(A\|B) and SRVAL_(A\|B) are`
321			`-- nonsense: INIT_A : bit_vector := X"000";`
322			`-- This is a 12 bit value, while a 9 bit one is needed. Thus the`
323			`-- explicit definition above.`