OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [rlink/] [rlinklib.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 wfjm 
-- $Id: rrilib.vhd 314 2010-07-09 17:38:41Z mueller $
2 
--
3 
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 
--
5 
-- This program is free software; you may redistribute and/or modify it under
6 
-- the terms of the GNU General Public License as published by the Free
7 
-- Software Foundation, either version 2, or at your option any later version.
8 
--
9 
-- This program is distributed in the hope that it will be useful, but
10 
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11 
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12 
-- for complete details.
13 
--
14 
------------------------------------------------------------------------------
15 
-- Package Name:   rrilib
16 
-- Description:    Remote Register Interface components
17 
--
18 
-- Dependencies:   -
19 
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
20 
-- Revision History:
21 
-- Date         Rev Version  Comment
22 
-- 2010-06-18   306   2.5.1  rename rbus data fields to _rbf_
23 
-- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
24 
-- 2010-06-03   300   2.1.5  use FAWIDTH=5 for rri_serport
25 
-- 2010-05-02   287   2.1.4  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
26 
--                           drop RP_IINT from interfaces; drop RTSFLUSH generic
27 
-- 2010-05-01   285   2.1.3  remove rri_rb_rpcompat, now obsolete
28 
-- 2010-04-18   279   2.1.2  rri_core_serport: drop RTSFBUF generic
29 
-- 2010-04-10   275   2.1.1  add rri_core_serport
30 
-- 2010-04-03   274   2.1    add CP_FLUSH for rri_core, rri_serport;
31 
--                           CE_USEC, RTSFLUSH, CTS_N, RTS_N  for rri_serport
32 
-- 2008-08-24   162   2.0    all with new rb_mreq/rb_sres interface
33 
-- 2008-08-22   161   1.3    renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
34 
-- 2008-02-16   116   1.2.1  added rri_wreg(rw|w|r)_3
35 
-- 2008-01-20   113   1.2    added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
36 
-- 2007-11-24    98   1.1    added RP_IINT for rri_core.
37 
-- 2007-09-09    81   1.0    Initial version
38 
------------------------------------------------------------------------------
39 
 
40 
library ieee;
41 
use ieee.std_logic_1164.all;
42 
 
43 
use work.slvtypes.all;
44 
 
45 
package rrilib is
46 
 
47 
constant c_rri_dat_idle : slv9 := "100000000";
48 
constant c_rri_dat_sop  : slv9 := "100000001";
49 
constant c_rri_dat_eop  : slv9 := "100000010";
50 
constant c_rri_dat_nak  : slv9 := "100000011";
51 
constant c_rri_dat_attn : slv9 := "100000100";
52 
 
53 
constant c_rri_cmd_rreg : slv3 := "000";
54 
constant c_rri_cmd_rblk : slv3 := "001";
55 
constant c_rri_cmd_wreg : slv3 := "010";
56 
constant c_rri_cmd_wblk : slv3 := "011";
57 
constant c_rri_cmd_stat : slv3 := "100";
58 
constant c_rri_cmd_attn : slv3 := "101";
59 
constant c_rri_cmd_init : slv3 := "110";
60 
 
61 
constant c_rri_iint_rbf_anena:    integer := 15;         -- anena flag
62 
constant c_rri_iint_rbf_itoena:   integer := 14;         -- itoena flag
63 
subtype  c_rri_iint_rbf_itoval is integer range 7 downto 0; -- command code
64 
 
65 
subtype  c_rri_cmd_rbf_seq is  integer range 7 downto 3; -- sequence number
66 
subtype  c_rri_cmd_rbf_code is integer range 2 downto 0; -- command code
67 
 
68 
subtype  c_rri_stat_rbf_stat is integer range 7 downto 5;  -- ext status bits
69 
constant c_rri_stat_rbf_attn:   integer := 4;  -- attention flags set
70 
constant c_rri_stat_rbf_ccrc:   integer := 3;  -- command crc error
71 
constant c_rri_stat_rbf_dcrc:   integer := 2;  -- data crc error
72 
constant c_rri_stat_rbf_ioto:   integer := 1;  -- i/o time out
73 
constant c_rri_stat_rbf_ioerr:  integer := 0;  -- i/o error
74 
 
75 
type rb_mreq_type is record             -- rribus - master request
76 
  req  : slbit;                         -- request
77 
  we   : slbit;                         -- write enable
78 
  init : slbit;                         -- init
79 
  addr : slv8;                          -- address
80 
  din  : slv16;                         -- data (input to slave)
81 
end record rb_mreq_type;
82 
 
83 
constant rb_mreq_init : rb_mreq_type :=
84 
  ('0','0','0',                         -- req, we, init
85 
   (others=>'0'),                       -- addr
86 
   (others=>'0'));                      -- din
87 
 
88 
type rb_sres_type is record             -- rribus - slave response
89 
  ack  : slbit;                         -- acknowledge
90 
  busy : slbit;                         -- busy
91 
  err  : slbit;                         -- error
92 
  dout : slv16;                         -- data (output from slave)
93 
end record rb_sres_type;
94 
 
95 
constant rb_sres_init : rb_sres_type :=
96 
  ('0','0','0',                         -- ack, busy, err
97 
   (others=>'0'));                      -- dout
98 
 
99 
component rri_core is                   -- rri, core interface
100 
  generic (
101 
    ATOWIDTH : positive :=  5;          -- access timeout counter width
102 
    ITOWIDTH : positive :=  6);         -- idle timeout counter width
103 
  port (
104 
    CLK  : in slbit;                    -- clock
105 
    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
106 
    RESET  : in slbit;                  -- reset
107 
    CP_DI : in slv9;                    -- comm port: data in
108 
    CP_ENA : in slbit;                  -- comm port: data enable
109 
    CP_BUSY : out slbit;                -- comm port: data busy
110 
    CP_DO : out slv9;                   -- comm port: data out
111 
    CP_VAL : out slbit;                 -- comm port: data valid
112 
    CP_HOLD : in slbit;                 -- comm port: data hold
113 
    CP_FLUSH : out slbit;               -- comm port: data flush
114 
    RB_MREQ : out rb_mreq_type;         -- rbus: request
115 
    RB_SRES : in rb_sres_type;          -- rbus: response
116 
    RB_LAM : in slv16;                  -- rbus: look at me
117 
    RB_STAT : in slv3                   -- rbus: status flags
118 
  );
119 
end component;
120 
 
121 
component rricp_aif is                  -- rri comm port, abstract interface
122 
  port (
123 
    CLK  : in slbit;                    -- clock
124 
    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
125 
    RESET  : in slbit :='0';            -- reset
126 
    CP_DI : in slv9;                    -- comm port: data in
127 
    CP_ENA : in slbit;                  -- comm port: data enable
128 
    CP_BUSY : out slbit;                -- comm port: data busy
129 
    CP_DO : out slv9;                   -- comm port: data out
130 
    CP_VAL : out slbit;                 -- comm port: data valid
131 
    CP_HOLD : in slbit := '0'           -- comm port: data hold
132 
  );
133 
end component;
134 
 
135 
component rrirp_aif is                  -- rri reg port, abstract interface
136 
  port (
137 
    CLK  : in slbit;                    -- clock
138 
    RESET  : in slbit := '0';           -- reset
139 
    RB_MREQ : in rb_mreq_type;          -- rbus: request
140 
    RB_SRES : out rb_sres_type;         -- rbus: response
141 
    RB_LAM : out slv16;                 -- rbus: look at me
142 
    RB_STAT : out slv3                  -- rbus: status flags
143 
  );
144 
end component;
145 
 
146 
component rri_serport is                -- rri serport adapter
147 
  generic (
148 
    CPREF : slv4 :=  "1000";            -- comma prefix
149 
    FAWIDTH : positive :=  5;           -- rx fifo address port width
150 
    CDWIDTH : positive := 13;           -- clk divider width
151 
    CDINIT : natural   := 15);          -- clk divider initial/reset setting
152 
  port (
153 
    CLK  : in slbit;                    -- clock
154 
    CE_USEC : in slbit;                 -- 1 usec clock enable
155 
    CE_MSEC : in slbit;                 -- 1 msec clock enable
156 
    RESET  : in slbit;                  -- reset
157 
    RXSD : in slbit;                    -- receive serial data      (board view)
158 
    TXSD : out slbit;                   -- transmit serial data     (board view)
159 
    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
160 
    RTS_N : out slbit;                  -- request to send (act.low, board view)
161 
    CP_DI : out slv9;                   -- comm port: data in
162 
    CP_ENA : out slbit;                 -- comm port: data enable
163 
    CP_BUSY : in slbit;                 -- comm port: data busy
164 
    CP_DO : in slv9;                    -- comm port: data out
165 
    CP_VAL : in slbit;                  -- comm port: data valid
166 
    CP_HOLD : out slbit;                -- comm port: data hold
167 
    CP_FLUSH : in slbit := '0'          -- comm port: data flush
168 
  );
169 
end component;
170 
 
171 
component rri_core_serport is           -- rri, core+serport with cpmon+rbmon
172 
  generic (
173 
    ATOWIDTH : positive :=  5;          -- access timeout counter width
174 
    ITOWIDTH : positive :=  6;          -- idle timeout counter width
175 
    FAWIDTH : positive :=  5;           -- rx fifo address port width
176 
    CDWIDTH : positive := 13;           -- clk divider width
177 
    CDINIT : natural   := 15);          -- clk divider initial/reset setting
178 
  port (
179 
    CLK  : in slbit;                    -- clock
180 
    CE_USEC : in slbit;                 -- 1 usec clock enable
181 
    CE_MSEC : in slbit;                 -- 1 msec clock enable
182 
    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
183 
    RESET  : in slbit;                  -- reset
184 
    RXSD : in slbit;                    -- receive serial data      (board view)
185 
    TXSD : out slbit;                   -- transmit serial data     (board view)
186 
    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
187 
    RTS_N : out slbit;                  -- request to send (act.low, board view)
188 
    RB_MREQ : out rb_mreq_type;         -- rbus: request
189 
    RB_SRES : in rb_sres_type;          -- rbus: response
190 
    RB_LAM : in slv16;                  -- rbus: look at me
191 
    RB_STAT : in slv3                   -- rbus: status flags
192 
  );
193 
end component;
194 
 
195 
component rb_sres_or_2 is               -- rribus result or, 2 input
196 
  port (
197 
    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
198 
    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
199 
    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
200 
  );
201 
end component;
202 
component rb_sres_or_3 is               -- rribus result or, 3 input
203 
  port (
204 
    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
205 
    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
206 
    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
207 
    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
208 
  );
209 
end component;
210 
component rb_sres_or_4 is               -- rribus result or, 4 input
211 
  port (
212 
    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
213 
    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
214 
    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
215 
    RB_SRES_4  :  in rb_sres_type := rb_sres_init; -- rb_sres input 4
216 
    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
217 
  );
218 
end component;
219 
 
220 
component rri_wreg_rw_3 is              -- rri: wide register r/w 3 bit select
221 
  generic (
222 
    DWIDTH : positive := 16);
223 
  port (
224 
    CLK  : in slbit;                    -- clock
225 
    RESET  : in slbit;                  -- reset
226 
    FADDR : slv3;                       -- field address
227 
    SEL : slbit;                        -- select
228 
    DATA : out slv(DWIDTH-1 downto 0);  -- data
229 
    RB_MREQ :  in rb_mreq_type;         -- rribus request
230 
    RB_SRES : out rb_sres_type          -- rribus response
231 
  );
232 
end component;
233 
 
234 
component rri_wreg_w_3 is               -- rri: wide register w-o 3 bit select
235 
  generic (
236 
    DWIDTH : positive := 16);
237 
  port (
238 
    CLK  : in slbit;                    -- clock
239 
    RESET  : in slbit;                  -- reset
240 
    FADDR : slv3;                       -- field address
241 
    SEL : slbit;                        -- select
242 
    DATA : out slv(DWIDTH-1 downto 0);  -- data
243 
    RB_MREQ :  in rb_mreq_type;         -- rribus request
244 
    RB_SRES : out rb_sres_type          -- rribus response
245 
  );
246 
end component;
247 
 
248 
component rri_wreg_r_3 is               -- rri: wide register r-o 3 bit select
249 
  generic (
250 
    DWIDTH : positive := 16);
251 
  port (
252 
    FADDR : slv3;                       -- field address
253 
    SEL : slbit;                        -- select
254 
    DATA : in slv(DWIDTH-1 downto 0);   -- data
255 
    RB_SRES : out rb_sres_type          -- rribus response
256 
  );
257 
end component;
258 
 
259 
end rrilib;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.