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-- $Id: rlinktblib.vhd 389 2011-07-07 21:59:00Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: rlinktblib
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-- Description: rlink test environment components
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--
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-- Dependencies: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-12-29 351 3.0.1 add rbtba_aif;
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-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
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-- many rri->rlink renames; drop rbus parts;
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-- 2010-11-13 338 2.5.2 add rritb_core_dcm
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-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
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-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon
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-- 2010-05-02 287 2.1.1 rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
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-- drop RP_IINT signal from interfaces
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-- add sbcntl_sbf_(cp|rp)mon defs
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-- 2010-04-24 282 2.1 add rritb_core
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-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
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-- 2008-03-24 129 1.1.5 CLK_CYCLE now 31 bits
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-- 2007-12-23 105 1.1.4 add AP_LAM for rritb_rpmon(_sb)
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-- 2007-11-24 98 1.1.3 add RP_IINT for rritb_rpmon(_sb)
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-- 2007-09-01 78 1.1.2 add rricp_rp
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-- 2007-08-25 75 1.1.1 add rritb_cpmon_sb, rritb_rpmon_sb
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-- 2007-08-16 74 1.1 remove rritb_tt* component; some interface changes
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-- 2007-08-03 71 1.0.2 use rrirp_acif; change generics for rritb_[cr]pmon
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-- 2007-07-22 68 1.0.1 add rritb_cpmon rritb_rpmon monitors
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-- 2007-07-15 66 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.rlinklib.all;
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package rlinktblib is
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type rlink_tba_cntl_type is record -- rlink_tba control
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cmd : slv3; -- command code
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ena : slbit; -- command enable
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addr : slv8; -- address
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cnt : slv8; -- block size
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eop : slbit; -- end packet after current command
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end record rlink_tba_cntl_type;
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constant rlink_tba_cntl_init : rlink_tba_cntl_type := (
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(others=>'0'), -- cmd
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'0', -- ena
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(others=>'0'), -- addr
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(others=>'0'), -- cnt
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'0'); -- eop
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type rlink_tba_stat_type is record -- rlink_tba status
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busy : slbit; -- command busy
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ack : slbit; -- command acknowledge
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err : slbit; -- command error flag
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stat : slv8; -- status flags
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braddr : slv8; -- block read address (for wblk)
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bre : slbit; -- block read enable (for wblk)
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bwaddr : slv8; -- block write address (for rblk)
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bwe : slbit; -- block write enable (for rblk)
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attnpend : slbit; -- attn pending
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attnint : slbit; -- attn interrupt
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end record rlink_tba_stat_type;
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constant rlink_tba_stat_init : rlink_tba_stat_type := (
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'0','0','0', -- busy, ack, err
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(others=>'0'), -- stat
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(others=>'0'), -- braddr
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'0', -- bre
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(others=>'0'), -- bwaddr
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'0', -- bwe
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'0','0'); -- attnpend, attnint
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component rlink_tba is -- rlink test bench adapter
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CNTL : in rlink_tba_cntl_type; -- control port
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DI : in slv16; -- input data
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STAT : out rlink_tba_stat_type; -- status port
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DO : out slv16; -- output data
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RL_DI : out slv9; -- rlink: data in
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RL_ENA : out slbit; -- rlink: data enable
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RL_BUSY : in slbit; -- rlink: data busy
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RL_DO : in slv9; -- rlink: data out
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RL_VAL : in slbit; -- rlink: data valid
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RL_HOLD : out slbit -- rlink: data hold
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);
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end component;
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component rbtba_aif is -- rbus tba, abstract interface
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-- no generics, no records
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RB_MREQ_aval : in slbit; -- rbus: request - aval
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RB_MREQ_re : in slbit; -- rbus: request - re
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RB_MREQ_we : in slbit; -- rbus: request - we
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RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
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RB_MREQ_addr : in slv8; -- rbus: request - addr
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RB_MREQ_din : in slv16; -- rbus: request - din
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RB_SRES_ack : out slbit; -- rbus: response - ack
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RB_SRES_busy : out slbit; -- rbus: response - busy
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RB_SRES_err : out slbit; -- rbus: response - err
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RB_SRES_dout : out slv16; -- rbus: response - dout
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RB_LAM : out slv16; -- rbus: look at me
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RB_STAT : out slv3 -- rbus: status flags
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);
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end component;
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component tbcore_rlink is -- core of vhpi_cext based test bench
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generic (
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CLK_PERIOD : time := 20 ns; -- clock period
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CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
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SETUP_TIME : time := 5 ns; -- setup time
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C2OUT_TIME : time := 10 ns); -- clock to output time
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port (
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CLK : out slbit; -- main clock
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RX_DATA : out slv8; -- read data (data ext->tb)
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RX_VAL : out slbit; -- read data valid (data ext->tb)
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RX_HOLD : in slbit; -- read data hold (data ext->tb)
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TX_DATA : in slv8; -- write data (data tb->ext)
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TX_ENA : in slbit -- write data enable (data tb->ext)
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);
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end component;
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component tbcore_rlink_dcm is -- dcm aware core of vhpi_cext based tb
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generic (
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CLKOSC_PERIOD : time := 20 ns; -- clock osc period
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CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
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SETUP_TIME : time := 5 ns; -- setup time
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C2OUT_TIME : time := 10 ns); -- clock to output time
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port (
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CLKOSC : out slbit; -- clock osc
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CLKSYS : in slbit; -- DCM derived system clock
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RX_DATA : out slv8; -- read data (data ext->tb)
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RX_VAL : out slbit; -- read data valid (data ext->tb)
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RX_HOLD : in slbit; -- read data hold (data ext->tb)
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TX_DATA : in slv8; -- write data (data tb->ext)
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TX_ENA : in slbit -- write data enable (data tb->ext)
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);
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end component;
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-- FIXME after this point !!
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component rricp_rp is -- rri comm->reg port aif forwarder
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-- implements rricp_aif, uses rrirp_aif
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port (
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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RESET : in slbit :='0'; -- reset
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RL_DI : in slv9; -- rlink: data in
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RL_ENA : in slbit; -- rlink: data enable
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RL_BUSY : out slbit; -- rlink: data busy
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RL_DO : out slv9; -- rlink: data out
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RL_VAL : out slbit; -- rlink: data valid
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RL_HOLD : in slbit := '0' -- rlink: data hold
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);
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end component;
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end package rlinktblib;
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