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wfjm |
-- $Id: serport_2clock.vhd 476 2013-01-26 22:23:53Z mueller $
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wfjm |
--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: serport_2clock - syn
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-- Description: serial port: serial port module, 2 clock domain
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--
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-- Dependencies: genlib/cdc_pulse
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-- serport_uart_rxtx_ab
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-- serport_xonrx
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-- serport_xontx
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-- memlib/fifo_2c_dram
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-12-10 438 1.0.2 internal reset on abact
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-- 2011-12-09 437 1.0.1 rename stat->moni port
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-- 2011-11-13 424 1.0 Initial version
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-- 2011-11-07 421 0.5 First draft
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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wfjm |
use work.serportlib.all;
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use work.genlib.all;
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use work.memlib.all;
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entity serport_2clock is -- serial port module, 2 clock domain
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15; -- clk divider initial/reset setting
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RXFAWIDTH : natural := 5; -- rx fifo address width
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TXFAWIDTH : natural := 5); -- tx fifo address width
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port (
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CLKU : in slbit; -- clock (backend:user)
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RESET : in slbit; -- reset
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CLKS : in slbit; -- clock (frontend:serial)
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CES_MSEC : in slbit; -- S|1 msec clock enable
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ENAXON : in slbit; -- U|enable xon/xoff handling
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ENAESC : in slbit; -- U|enable xon/xoff escaping
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RXDATA : out slv8; -- U|receiver data out
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RXVAL : out slbit; -- U|receiver data valid
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RXHOLD : in slbit; -- U|receiver data hold
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TXDATA : in slv8; -- U|transmit data in
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TXENA : in slbit; -- U|transmit data enable
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TXBUSY : out slbit; -- U|transmit busy
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MONI : out serport_moni_type; -- U|serport monitor port
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RXSD : in slbit; -- S|receive serial data (uart view)
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TXSD : out slbit; -- S|transmit serial data (uart view)
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RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
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TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
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);
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end serport_2clock;
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architecture syn of serport_2clock is
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type synu_type is record
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rxact_c : slbit; -- rxact (capt from CLKS->CLKU)
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rxact_s : slbit; -- rxact (sync in CLKU)
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txact_c : slbit; -- txact (capt from CLKS->CLKU)
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txact_s : slbit; -- txact (sync in CLKU)
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abact_c : slbit; -- abact (capt from CLKS->CLKU)
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abact_s : slbit; -- abact (sync in CLKU)
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rxok_c : slbit; -- rxok (capt from CLKS->CLKU)
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rxok_s : slbit; -- rxok (sync in CLKU)
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txok_c : slbit; -- txok (capt from CLKS->CLKU)
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txok_s : slbit; -- txok (sync in CLKU)
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abclkdiv_c : slv(CDWIDTH-1 downto 0); -- abclkdiv (capt from CLKS->CLKU)
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abclkdiv_s : slv(CDWIDTH-1 downto 0); -- abclkdiv (sync in CLKU)
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end record synu_type;
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constant synu_init : synu_type := (
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'0','0', -- rxact_c,_s
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'0','0', -- txact_c,_s
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'0','0', -- abact_c,_s
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'0','0', -- rxok_c,_s
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'0','0', -- txok_c,_s
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slv(to_unsigned(0,CDWIDTH)), -- abclkdiv_c
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slv(to_unsigned(0,CDWIDTH)) -- abclkdiv_s
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);
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type syns_type is record
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enaxon_c : slbit; -- enaxon (capt from CLKU->CLKS)
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enaxon_s : slbit; -- enaxon (sync in CLKS)
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enaesc_c : slbit; -- enaesc (capt from CLKU->CLKS)
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enaesc_s : slbit; -- enaesc (sync in CLKS)
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end record syns_type;
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constant syns_init : syns_type := (
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'0','0', -- enaxon_c,_s
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'0','0' -- enaxon_c,_s
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);
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signal R_SYNU : synu_type := synu_init; -- sync registers (clku)
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signal R_SYNS : syns_type := syns_init; -- sync registers (clks)
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signal R_RXOK : slbit := '1';
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signal RESET_INT : slbit := '0';
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signal RESET_CLKS : slbit := '0';
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signal UART_RXDATA : slv8 := (others=>'0');
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signal UART_RXVAL : slbit := '0';
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signal UART_TXDATA : slv8 := (others=>'0');
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signal UART_TXENA : slbit := '0';
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signal UART_TXBUSY : slbit := '0';
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signal XONTX_TXENA : slbit := '0';
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signal XONTX_TXBUSY : slbit := '0';
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signal RXFIFO_DI : slv8 := (others=>'0');
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signal RXFIFO_ENA : slbit := '0';
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signal RXFIFO_BUSY : slbit := '0';
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signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
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signal TXFIFO_DO : slv8 := (others=>'0');
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signal TXFIFO_VAL : slbit := '0';
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signal TXFIFO_HOLD : slbit := '0';
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signal RXERR : slbit := '0';
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signal RXOVR : slbit := '0';
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signal RXACT : slbit := '0';
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signal ABACT : slbit := '0';
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signal ABDONE : slbit := '0';
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signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
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signal TXOK : slbit := '0';
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signal RXOK : slbit := '0';
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signal RXERR_CLKU : slbit := '0';
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signal RXOVR_CLKU : slbit := '0';
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signal ABDONE_CLKU : slbit := '0';
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begin
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assert CDWIDTH<=16
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report "assert(CDWIDTH<=16): max width of UART clock divider"
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severity failure;
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CDC_RESET : cdc_pulse
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generic map (
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POUT_SINGLE => false,
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BUSY_WACK => false)
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port map (
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CLKM => CLKU,
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RESET => '0',
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CLKS => CLKS,
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PIN => RESET,
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BUSY => open,
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POUT => RESET_CLKS
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);
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UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
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generic map (
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CDWIDTH => CDWIDTH,
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CDINIT => CDINIT)
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port map (
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CLK => CLKS,
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CE_MSEC => CES_MSEC,
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RESET => RESET_CLKS,
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RXSD => RXSD,
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RXDATA => UART_RXDATA,
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RXVAL => UART_RXVAL,
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RXERR => RXERR,
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RXACT => RXACT,
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TXSD => TXSD,
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TXDATA => UART_TXDATA,
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TXENA => UART_TXENA,
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TXBUSY => UART_TXBUSY,
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ABACT => ABACT,
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ABDONE => ABDONE,
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ABCLKDIV => ABCLKDIV
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);
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RESET_INT <= RESET_CLKS or ABACT;
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XONRX : serport_xonrx -- xon/xoff logic rx path
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port map (
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CLK => CLKS,
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RESET => RESET_INT,
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ENAXON => R_SYNS.enaxon_s,
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ENAESC => R_SYNS.enaesc_s,
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UART_RXDATA => UART_RXDATA,
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UART_RXVAL => UART_RXVAL,
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RXDATA => RXFIFO_DI,
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RXVAL => RXFIFO_ENA,
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RXHOLD => RXFIFO_BUSY,
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RXOVR => RXOVR,
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TXOK => TXOK
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);
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XONTX : serport_xontx -- xon/xoff logic tx path
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port map (
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CLK => CLKS,
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RESET => RESET_INT,
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ENAXON => R_SYNS.enaxon_s,
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ENAESC => R_SYNS.enaesc_s,
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UART_TXDATA => UART_TXDATA,
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UART_TXENA => XONTX_TXENA,
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UART_TXBUSY => XONTX_TXBUSY,
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TXDATA => TXFIFO_DO,
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TXENA => TXFIFO_VAL,
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TXBUSY => TXFIFO_HOLD,
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RXOK => RXOK,
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TXOK => TXOK
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);
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RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
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generic map (
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AWIDTH => RXFAWIDTH,
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DWIDTH => 8)
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port map (
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CLKW => CLKS,
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CLKR => CLKU,
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RESETW => ABACT, -- clear fifo on abact
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RESETR => RESET,
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DI => RXFIFO_DI,
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ENA => RXFIFO_ENA,
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BUSY => RXFIFO_BUSY,
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DO => RXDATA,
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VAL => RXVAL,
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HOLD => RXHOLD,
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SIZEW => RXFIFO_SIZEW,
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SIZER => open
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);
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TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
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generic map (
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AWIDTH => TXFAWIDTH,
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DWIDTH => 8)
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port map (
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CLKW => CLKU,
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CLKR => CLKS,
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RESETW => RESET,
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RESETR => ABACT, -- clear fifo on abact
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DI => TXDATA,
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ENA => TXENA,
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BUSY => TXBUSY,
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DO => TXFIFO_DO,
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VAL => TXFIFO_VAL,
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HOLD => TXFIFO_HOLD,
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SIZEW => open,
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SIZER => open
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);
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-- receive back preasure
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-- on if fifo more than 3/4 full (less than 1/4 free)
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-- off if fifo less than 1/2 full (more than 1/2 free)
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proc_rxok: process (CLKS)
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constant rxsize_rxok_off : slv2 := "01";
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constant rxsize_rxok_on : slv2 := "10";
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variable rxsize_msb : slv2 := "00";
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begin
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if rising_edge(CLKS) then
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if RESET_INT = '1' then
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R_RXOK <= '1';
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else
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rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
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if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
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R_RXOK <= '0';
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elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
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R_RXOK <= '1';
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end if;
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end if;
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end if;
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end process proc_rxok;
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RXOK <= R_RXOK;
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RXRTS_N <= not R_RXOK;
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proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
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begin
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if TXCTS_N = '0' then -- transmit cts asserted
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UART_TXENA <= XONTX_TXENA;
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XONTX_TXBUSY <= UART_TXBUSY;
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else -- transmit cts not asserted
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UART_TXENA <= '0';
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XONTX_TXBUSY <= '1';
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end if;
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end process proc_cts;
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| 301 |
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proc_synu: process (CLKU)
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begin
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if rising_edge(CLKU) then
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R_SYNU.rxact_c <= RXACT;
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R_SYNU.rxact_s <= R_SYNU.rxact_c;
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R_SYNU.txact_c <= UART_TXBUSY;
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| 308 |
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R_SYNU.txact_s <= R_SYNU.txact_c;
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R_SYNU.abact_c <= ABACT;
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| 310 |
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R_SYNU.abact_s <= R_SYNU.abact_c;
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| 311 |
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R_SYNU.rxok_c <= RXOK;
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| 312 |
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R_SYNU.rxok_s <= R_SYNU.rxok_c;
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R_SYNU.txok_c <= TXOK;
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R_SYNU.txok_s <= R_SYNU.txok_c;
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| 315 |
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R_SYNU.abclkdiv_c <= ABCLKDIV;
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| 316 |
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R_SYNU.abclkdiv_s <= R_SYNU.abclkdiv_c;
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| 317 |
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end if;
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| 318 |
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end process proc_synu;
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| 319 |
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|
|
proc_syns: process (CLKS)
|
| 321 |
|
|
begin
|
| 322 |
|
|
if rising_edge(CLKS) then
|
| 323 |
|
|
R_SYNS.enaxon_c <= ENAXON;
|
| 324 |
|
|
R_SYNS.enaxon_s <= R_SYNS.enaxon_c;
|
| 325 |
|
|
R_SYNS.enaesc_c <= ENAESC;
|
| 326 |
|
|
R_SYNS.enaesc_s <= R_SYNS.enaesc_c;
|
| 327 |
|
|
end if;
|
| 328 |
|
|
end process proc_syns;
|
| 329 |
|
|
|
| 330 |
|
|
CDC_RXERR : cdc_pulse
|
| 331 |
|
|
generic map (
|
| 332 |
|
|
POUT_SINGLE => true,
|
| 333 |
|
|
BUSY_WACK => false)
|
| 334 |
|
|
port map (
|
| 335 |
|
|
CLKM => CLKS,
|
| 336 |
|
|
RESET => '0',
|
| 337 |
|
|
CLKS => CLKU,
|
| 338 |
|
|
PIN => RXERR,
|
| 339 |
|
|
BUSY => open,
|
| 340 |
|
|
POUT => RXERR_CLKU
|
| 341 |
|
|
);
|
| 342 |
|
|
|
| 343 |
|
|
CDC_RXOVR : cdc_pulse
|
| 344 |
|
|
generic map (
|
| 345 |
|
|
POUT_SINGLE => true,
|
| 346 |
|
|
BUSY_WACK => false)
|
| 347 |
|
|
port map (
|
| 348 |
|
|
CLKM => CLKS,
|
| 349 |
|
|
RESET => '0',
|
| 350 |
|
|
CLKS => CLKU,
|
| 351 |
|
|
PIN => RXOVR,
|
| 352 |
|
|
BUSY => open,
|
| 353 |
|
|
POUT => RXOVR_CLKU
|
| 354 |
|
|
);
|
| 355 |
|
|
|
| 356 |
|
|
CDC_ABDONE : cdc_pulse
|
| 357 |
|
|
generic map (
|
| 358 |
|
|
POUT_SINGLE => true,
|
| 359 |
|
|
BUSY_WACK => false)
|
| 360 |
|
|
port map (
|
| 361 |
|
|
CLKM => CLKS,
|
| 362 |
|
|
RESET => '0',
|
| 363 |
|
|
CLKS => CLKU,
|
| 364 |
|
|
PIN => ABDONE,
|
| 365 |
|
|
BUSY => open,
|
| 366 |
|
|
POUT => ABDONE_CLKU
|
| 367 |
|
|
);
|
| 368 |
|
|
|
| 369 |
|
|
MONI.rxerr <= RXERR_CLKU;
|
| 370 |
|
|
MONI.rxovr <= RXOVR_CLKU;
|
| 371 |
|
|
MONI.rxact <= R_SYNU.rxact_s;
|
| 372 |
|
|
MONI.txact <= R_SYNU.txact_s;
|
| 373 |
|
|
MONI.abact <= R_SYNU.abact_s;
|
| 374 |
|
|
MONI.abdone <= ABDONE_CLKU;
|
| 375 |
|
|
MONI.rxok <= R_SYNU.rxok_s;
|
| 376 |
|
|
MONI.txok <= R_SYNU.txok_s;
|
| 377 |
|
|
|
| 378 |
|
|
proc_abclkdiv: process (R_SYNU.abclkdiv_s)
|
| 379 |
|
|
begin
|
| 380 |
|
|
MONI.abclkdiv <= (others=>'0');
|
| 381 |
|
|
MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s;
|
| 382 |
|
|
end process proc_abclkdiv;
|
| 383 |
|
|
|
| 384 |
|
|
end syn;
|
