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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [serport/] [serportlib.vhd] - Blame information for rev 2

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-- $Id: serport.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name:   serport
-- Description:    serial port interface components
--
-- Dependencies:   -
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History: 
-- Date         Rev Version  Comment
-- 2010-04-10   276   1.2    add clock divider constant defs
-- 2007-10-22    88   1.1    renames (in prev revs); remove std_logic_unsigned
-- 2007-06-03    45   1.0    Initial version 
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package serport is
 
-- clock divider constants assume 50 MHz clock
 
  constant serport_clkdiv_009600 : integer := 5208-1; -- 50000000/  9600=5208.33
  constant serport_clkdiv_019200 : integer := 2604-1; -- 50000000/ 19200=2604.16
  constant serport_clkdiv_038400 : integer := 1302-1; -- 50000000/ 38400=1302.08
  constant serport_clkdiv_057600 : integer :=  868-1; -- 50000000/ 57600= 868.05
  constant serport_clkdiv_115200 : integer :=  434-1; -- 50000000/115200= 434.02
  constant serport_clkdiv_230400 : integer :=  217-1; -- 50000000/230400= 217.01
  constant serport_clkdiv_460800 : integer :=  109-1; -- 50000000/460800= 108.51
  constant serport_clkdiv_500000 : integer :=  100-1; -- 50000000/500000= 100
  constant serport_clkdiv_576000 : integer :=   87-1; -- 50000000/576000=  86.80
  constant serport_clkdiv_921600 : integer :=   54-1; -- 50000000/921600=  54.25
  constant serport_clkdiv_1M     : integer :=   50-1; -- 50000000/1M    =  50
  constant serport_clkdiv_2M     : integer :=   24-1; -- 50000000/2M    =  25
 
component serport_uart_rxtx is          -- serial port uart: rx+tx combo
  generic (
    CDWIDTH : positive := 13);          -- clk divider width
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
    RXSD : in slbit;                    -- receive serial data (uart view)
    RXDATA : out slv8;                  -- receiver data out
    RXVAL : out slbit;                  -- receiver data valid
    RXERR : out slbit;                  -- receiver data error (frame error)
    RXACT : out slbit;                  -- receiver active
    TXSD : out slbit;                   -- transmit serial data (uart view)
    TXDATA : in slv8;                   -- transmit data in
    TXENA : in slbit;                   -- transmit data enable
    TXBUSY : out slbit                  -- transmit busy
  );
end component;
 
component serport_uart_rx is            -- serial port uart: receive part
  generic (
    CDWIDTH : positive := 13);          -- clk divider width
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
    RXSD : in slbit;                    -- receive serial data (uart view)
    RXDATA : out slv8;                  -- receiver data out
    RXVAL : out slbit;                  -- receiver data valid
    RXERR : out slbit;                  -- receiver data error (frame error)
    RXACT : out slbit                   -- receiver active
  );
end component;
 
component serport_uart_tx is            -- serial port uart: transmit part
  generic (
    CDWIDTH : positive := 13);          -- clk divider width
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
    TXSD : out slbit;                   -- transmit serial data (uart view)
    TXDATA : in slv8;                   -- transmit data in
    TXENA : in slbit;                   -- transmit data enable
    TXBUSY : out slbit                  -- transmit busy
  );
end component;
 
component serport_uart_rxtx_ab is       -- serial port uart: rx+tx+autobaud
  generic (
    CDWIDTH : positive := 13;           -- clk divider width
    CDINIT: natural := 15);             -- clk divider initial/reset setting
  port (
    CLK : in slbit;                     -- clock
    CE_MSEC : in slbit;                 -- 1 msec clock enable
    RESET : in slbit;                   -- reset
    RXSD : in slbit;                    -- receive serial data (uart view)
    RXDATA : out slv8;                  -- receiver data out
    RXVAL : out slbit;                  -- receiver data valid
    RXERR : out slbit;                  -- receiver data error (frame error)
    RXACT : out slbit;                  -- receiver active
    TXSD : out slbit;                   -- transmit serial data (uart view)
    TXDATA : in slv8;                   -- transmit data in
    TXENA : in slbit;                   -- transmit data enable
    TXBUSY : out slbit;                 -- transmit busy
    ABACT : out slbit;                  -- autobaud active; if 1 clkdiv invalid
    ABDONE : out slbit                  -- autobaud resync done
  );
end component;
 
component serport_uart_autobaud is      -- serial port uart: autobauder
  generic (
    CDWIDTH : positive := 13;           -- clk divider width
    CDINIT: natural := 15);             -- clk divider initial/reset setting
  port (
    CLK : in slbit;                     -- clock
    CE_MSEC : in slbit;                 -- 1 msec clock enable
    RESET : in slbit;                   -- reset
    RXSD : in slbit;                    -- receive serial data (uart view)
    CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
    ACT : out slbit;                    -- active; if 1 clkdiv is invalid
    DONE : out slbit                    -- resync done
  );
end component;
 
end serport;

Line No.	Rev	Author	Line
1	2	wfjm	`-- $Id: serport.vhd 314 2010-07-09 17:38:41Z mueller $`
2			`--`
3			`-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Package Name: serport`
16			`-- Description: serial port interface components`
17			`--`
18			`-- Dependencies: -`
19			`-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26`
20			`-- Revision History:`
21			`-- Date Rev Version Comment`
22			`-- 2010-04-10 276 1.2 add clock divider constant defs`
23			`-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned`
24			`-- 2007-06-03 45 1.0 Initial version`
25			`------------------------------------------------------------------------------`
26
27			`library ieee;`
28			`use ieee.std_logic_1164.all;`
29
30			`use work.slvtypes.all;`
31
32			`package serport is`
33
34			`-- clock divider constants assume 50 MHz clock`
35
36			`constant serport_clkdiv_009600 : integer := 5208-1; -- 50000000/ 9600=5208.33`
37			`constant serport_clkdiv_019200 : integer := 2604-1; -- 50000000/ 19200=2604.16`
38			`constant serport_clkdiv_038400 : integer := 1302-1; -- 50000000/ 38400=1302.08`
39			`constant serport_clkdiv_057600 : integer := 868-1; -- 50000000/ 57600= 868.05`
40			`constant serport_clkdiv_115200 : integer := 434-1; -- 50000000/115200= 434.02`
41			`constant serport_clkdiv_230400 : integer := 217-1; -- 50000000/230400= 217.01`
42			`constant serport_clkdiv_460800 : integer := 109-1; -- 50000000/460800= 108.51`
43			`constant serport_clkdiv_500000 : integer := 100-1; -- 50000000/500000= 100`
44			`constant serport_clkdiv_576000 : integer := 87-1; -- 50000000/576000= 86.80`
45			`constant serport_clkdiv_921600 : integer := 54-1; -- 50000000/921600= 54.25`
46			`constant serport_clkdiv_1M : integer := 50-1; -- 50000000/1M = 50`
47			`constant serport_clkdiv_2M : integer := 24-1; -- 50000000/2M = 25`
48
49			`component serport_uart_rxtx is -- serial port uart: rx+tx combo`
50			`generic (`
51			`CDWIDTH : positive := 13); -- clk divider width`
52			`port (`
53			`CLK : in slbit; -- clock`
54			`RESET : in slbit; -- reset`
55			`CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting`
56			`RXSD : in slbit; -- receive serial data (uart view)`
57			`RXDATA : out slv8; -- receiver data out`
58			`RXVAL : out slbit; -- receiver data valid`
59			`RXERR : out slbit; -- receiver data error (frame error)`
60			`RXACT : out slbit; -- receiver active`
61			`TXSD : out slbit; -- transmit serial data (uart view)`
62			`TXDATA : in slv8; -- transmit data in`
63			`TXENA : in slbit; -- transmit data enable`
64			`TXBUSY : out slbit -- transmit busy`
65			`);`
66			`end component;`
67
68			`component serport_uart_rx is -- serial port uart: receive part`
69			`generic (`
70			`CDWIDTH : positive := 13); -- clk divider width`
71			`port (`
72			`CLK : in slbit; -- clock`
73			`RESET : in slbit; -- reset`
74			`CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting`
75			`RXSD : in slbit; -- receive serial data (uart view)`
76			`RXDATA : out slv8; -- receiver data out`
77			`RXVAL : out slbit; -- receiver data valid`
78			`RXERR : out slbit; -- receiver data error (frame error)`
79			`RXACT : out slbit -- receiver active`
80			`);`
81			`end component;`
82
83			`component serport_uart_tx is -- serial port uart: transmit part`
84			`generic (`
85			`CDWIDTH : positive := 13); -- clk divider width`
86			`port (`
87			`CLK : in slbit; -- clock`
88			`RESET : in slbit; -- reset`
89			`CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting`
90			`TXSD : out slbit; -- transmit serial data (uart view)`
91			`TXDATA : in slv8; -- transmit data in`
92			`TXENA : in slbit; -- transmit data enable`
93			`TXBUSY : out slbit -- transmit busy`
94			`);`
95			`end component;`
96
97			`component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud`
98			`generic (`
99			`CDWIDTH : positive := 13; -- clk divider width`
100			`CDINIT: natural := 15); -- clk divider initial/reset setting`
101			`port (`
102			`CLK : in slbit; -- clock`
103			`CE_MSEC : in slbit; -- 1 msec clock enable`
104			`RESET : in slbit; -- reset`
105			`RXSD : in slbit; -- receive serial data (uart view)`
106			`RXDATA : out slv8; -- receiver data out`
107			`RXVAL : out slbit; -- receiver data valid`
108			`RXERR : out slbit; -- receiver data error (frame error)`
109			`RXACT : out slbit; -- receiver active`
110			`TXSD : out slbit; -- transmit serial data (uart view)`
111			`TXDATA : in slv8; -- transmit data in`
112			`TXENA : in slbit; -- transmit data enable`
113			`TXBUSY : out slbit; -- transmit busy`
114			`ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid`
115			`ABDONE : out slbit -- autobaud resync done`
116			`);`
117			`end component;`
118
119			`component serport_uart_autobaud is -- serial port uart: autobauder`
120			`generic (`
121			`CDWIDTH : positive := 13; -- clk divider width`
122			`CDINIT: natural := 15); -- clk divider initial/reset setting`
123			`port (`
124			`CLK : in slbit; -- clock`
125			`CE_MSEC : in slbit; -- 1 msec clock enable`
126			`RESET : in slbit; -- reset`
127			`RXSD : in slbit; -- receive serial data (uart view)`
128			`CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting`
129			`ACT : out slbit; -- active; if 1 clkdiv is invalid`
130			`DONE : out slbit -- resync done`
131			`);`
132			`end component;`
133
134			`end serport;`

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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [serport/] [serportlib.vhd] - Blame information for rev 2