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-- $Id: serportlib.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name:   serportlib
-- Description:    serial port interface components
--
-- Dependencies:   -
-- Tool versions:  xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History: 
-- Date         Rev Version  Comment
-- 2013-01-26   476   1.2.6  renamed package to serportlib
-- 2011-12-09   437   1.2.5  rename stat->moni port
-- 2011-10-23   419   1.2.4  remove serport_clkdiv_ consts;
-- 2011-10-22   417   1.2.3  add serport_xon(rx|tx) defs
-- 2011-10-14   416   1.2.2  add c_serport defs
-- 2010-12-26   348   1.2.1  add ABCLKDIV to serport_uart_rxtx_ab
-- 2010-04-10   276   1.2    add clock divider constant defs
-- 2007-10-22    88   1.1    renames (in prev revs); remove std_logic_unsigned
-- 2007-06-03    45   1.0    Initial version 
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package serportlib is
 
  constant c_serport_xon  : slv8 := "00010001"; -- char xon:  ^Q = hex 11
  constant c_serport_xoff : slv8 := "00010011"; -- char xoff  ^S = hex 13
  constant c_serport_xesc : slv8 := "00011011"; -- char xesc  ^[ = ESC = hex 1B
 
component serport_uart_rxtx is          -- serial port uart: rx+tx combo
  generic (
    CDWIDTH : positive := 13);          -- clk divider width
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
    RXSD : in slbit;                    -- receive serial data (uart view)
    RXDATA : out slv8;                  -- receiver data out
    RXVAL : out slbit;                  -- receiver data valid
    RXERR : out slbit;                  -- receiver data error (frame error)
    RXACT : out slbit;                  -- receiver active
    TXSD : out slbit;                   -- transmit serial data (uart view)
    TXDATA : in slv8;                   -- transmit data in
    TXENA : in slbit;                   -- transmit data enable
    TXBUSY : out slbit                  -- transmit busy
  );
end component;
 
component serport_uart_rx is            -- serial port uart: receive part
  generic (
    CDWIDTH : positive := 13);          -- clk divider width
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
    RXSD : in slbit;                    -- receive serial data (uart view)
    RXDATA : out slv8;                  -- receiver data out
    RXVAL : out slbit;                  -- receiver data valid
    RXERR : out slbit;                  -- receiver data error (frame error)
    RXACT : out slbit                   -- receiver active
  );
end component;
 
component serport_uart_tx is            -- serial port uart: transmit part
  generic (
    CDWIDTH : positive := 13);          -- clk divider width
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
    TXSD : out slbit;                   -- transmit serial data (uart view)
    TXDATA : in slv8;                   -- transmit data in
    TXENA : in slbit;                   -- transmit data enable
    TXBUSY : out slbit                  -- transmit busy
  );
end component;
 
component serport_uart_rxtx_ab is       -- serial port uart: rx+tx+autobaud
  generic (
    CDWIDTH : positive := 13;           -- clk divider width
    CDINIT: natural := 15);             -- clk divider initial/reset setting
  port (
    CLK : in slbit;                     -- clock
    CE_MSEC : in slbit;                 -- 1 msec clock enable
    RESET : in slbit;                   -- reset
    RXSD : in slbit;                    -- receive serial data (uart view)
    RXDATA : out slv8;                  -- receiver data out
    RXVAL : out slbit;                  -- receiver data valid
    RXERR : out slbit;                  -- receiver data error (frame error)
    RXACT : out slbit;                  -- receiver active
    TXSD : out slbit;                   -- transmit serial data (uart view)
    TXDATA : in slv8;                   -- transmit data in
    TXENA : in slbit;                   -- transmit data enable
    TXBUSY : out slbit;                 -- transmit busy
    ABACT : out slbit;                  -- autobaud active; if 1 clkdiv invalid
    ABDONE : out slbit;                 -- autobaud resync done
    ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
  );
end component;
 
component serport_uart_autobaud is      -- serial port uart: autobauder
  generic (
    CDWIDTH : positive := 13;           -- clk divider width
    CDINIT: natural := 15);             -- clk divider initial/reset setting
  port (
    CLK : in slbit;                     -- clock
    CE_MSEC : in slbit;                 -- 1 msec clock enable
    RESET : in slbit;                   -- reset
    RXSD : in slbit;                    -- receive serial data (uart view)
    CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
    ACT : out slbit;                    -- active; if 1 clkdiv is invalid
    DONE : out slbit                    -- resync done
  );
end component;
 
component serport_xonrx is              -- serial port: xon/xoff logic rx path
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    ENAXON : in slbit;                  -- enable xon/xoff handling
    ENAESC : in slbit;                  -- enable xon/xoff escaping
    UART_RXDATA : in slv8;              -- uart data out
    UART_RXVAL : in slbit;              -- uart data valid
    RXDATA : out slv8;                  -- user data out
    RXVAL : out slbit;                  -- user data valid
    RXHOLD : in slbit;                  -- user data hold
    RXOVR : out slbit;                  -- user data overrun
    TXOK : out slbit                    -- tx channel ok
  );
end component;
 
component serport_xontx is              -- serial port: xon/xoff logic tx path
  port (
    CLK : in slbit;                     -- clock
    RESET : in slbit;                   -- reset
    ENAXON : in slbit;                  -- enable xon/xoff handling
    ENAESC : in slbit;                  -- enable xon/xoff escaping
    UART_TXDATA : out slv8;             -- uart data in
    UART_TXENA : out slbit;             -- uart data enable
    UART_TXBUSY : in slbit;             -- uart data busy
    TXDATA : in slv8;                   -- user data in
    TXENA : in slbit;                   -- user data enable
    TXBUSY : out slbit;                 -- user data busy
    RXOK : in slbit;                    -- rx channel ok
    TXOK : in slbit                     -- tx channel ok
  );
end component;
 
type serport_moni_type is record        -- serport monitor port
  rxerr : slbit;                        -- receiver data error (frame error)
  rxovr : slbit;                        -- receiver data overrun
  rxact : slbit;                        -- receiver active
  txact : slbit;                        -- transceiver active
  abact : slbit;                        -- autobauder active;if 1 clkdiv invalid
  abdone : slbit;                       -- autobauder resync done
  abclkdiv : slv16;                     -- autobauder clock divider
  rxok : slbit;                         -- rx channel ok
  txok : slbit;                         -- tx channel ok
end record serport_moni_type;
 
constant serport_moni_init : serport_moni_type := (
  '0','0',                              -- rxerr,rxovr
  '0','0',                              -- rxact,txact
  '0','0',                              -- abact,abdone
  (others=>'0'),                        -- abclkdiv
  '0','0'                               -- rxok,txok
);
 
component serport_1clock is             -- serial port module, 1 clock domain
  generic (
    CDWIDTH : positive := 13;           -- clk divider width
    CDINIT : natural   := 15;           -- clk divider initial/reset setting
    RXFAWIDTH : natural :=  5;          -- rx fifo address width
    TXFAWIDTH : natural :=  5);         -- tx fifo address width
  port (
    CLK : in slbit;                     -- clock
    CE_MSEC : in slbit;                 -- 1 msec clock enable
    RESET : in slbit;                   -- reset
    ENAXON : in slbit;                  -- enable xon/xoff handling
    ENAESC : in slbit;                  -- enable xon/xoff escaping
    RXDATA : out slv8;                  -- receiver data out
    RXVAL : out slbit;                  -- receiver data valid
    RXHOLD : in slbit;                  -- receiver data hold
    TXDATA : in slv8;                   -- transmit data in
    TXENA : in slbit;                   -- transmit data enable
    TXBUSY : out slbit;                 -- transmit busy
    MONI : out serport_moni_type;       -- serport monitor port
    RXSD : in slbit;                    -- receive serial data (uart view)
    TXSD : out slbit;                   -- transmit serial data (uart view)
    RXRTS_N : out slbit;                -- receive rts (uart view, act.low)
    TXCTS_N : in slbit                  -- transmit cts (uart view, act.low)
  );
end component;
 
component serport_2clock is             -- serial port module, 2 clock domain
  generic (
    CDWIDTH : positive := 13;           -- clk divider width
    CDINIT : natural   := 15;           -- clk divider initial/reset setting
    RXFAWIDTH : natural :=  5;          -- rx fifo address width
    TXFAWIDTH : natural :=  5);         -- tx fifo address width
  port (
    CLKU : in slbit;                    -- clock (backend:user)
    RESET : in slbit;                   -- reset
    CLKS : in slbit;                    -- clock (frontend:serial)
    CES_MSEC : in slbit;                -- S|1 msec clock enable
    ENAXON : in slbit;                  -- U|enable xon/xoff handling
    ENAESC : in slbit;                  -- U|enable xon/xoff escaping
    RXDATA : out slv8;                  -- U|receiver data out
    RXVAL : out slbit;                  -- U|receiver data valid
    RXHOLD : in slbit;                  -- U|receiver data hold
    TXDATA : in slv8;                   -- U|transmit data in
    TXENA : in slbit;                   -- U|transmit data enable
    TXBUSY : out slbit;                 -- U|transmit busy
    MONI : out serport_moni_type;       -- U|serport monitor port
    RXSD : in slbit;                    -- S|receive serial data (uart view)
    TXSD : out slbit;                   -- S|transmit serial data (uart view)
    RXRTS_N : out slbit;                -- S|receive rts (uart view, act.low)
    TXCTS_N : in slbit                  -- S|transmit cts (uart view, act.low)
  );
end component;
 
end package serportlib;

Line No.	Rev	Author	Line
1	19	wfjm	`-- $Id: serportlib.vhd 476 2013-01-26 22:23:53Z mueller $`
2	2	wfjm	`--`
3	19	wfjm	`-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4	2	wfjm	`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15	19	wfjm	`-- Package Name: serportlib`
16	2	wfjm	`-- Description: serial port interface components`
17			`--`
18			`-- Dependencies: -`
19	13	wfjm	`-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29`
20	9	wfjm	`--`
21	2	wfjm	`-- Revision History:`
22			`-- Date Rev Version Comment`
23	19	wfjm	`-- 2013-01-26 476 1.2.6 renamed package to serportlib`
24	16	wfjm	`-- 2011-12-09 437 1.2.5 rename stat->moni port`
25	13	wfjm	`-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts;`
26			`-- 2011-10-22 417 1.2.3 add serport_xon(rx\|tx) defs`
27			`-- 2011-10-14 416 1.2.2 add c_serport defs`
28	9	wfjm	`-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab`
29	2	wfjm	`-- 2010-04-10 276 1.2 add clock divider constant defs`
30			`-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned`
31			`-- 2007-06-03 45 1.0 Initial version`
32			`------------------------------------------------------------------------------`
33
34			`library ieee;`
35			`use ieee.std_logic_1164.all;`
36
37			`use work.slvtypes.all;`
38
39	19	wfjm	`package serportlib is`
40	2	wfjm
41	13	wfjm	`constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11`
42			`constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13`
43			`constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B`
44
45	2	wfjm	`component serport_uart_rxtx is -- serial port uart: rx+tx combo`
46			`generic (`
47			`CDWIDTH : positive := 13); -- clk divider width`
48			`port (`
49			`CLK : in slbit; -- clock`
50			`RESET : in slbit; -- reset`
51			`CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting`
52			`RXSD : in slbit; -- receive serial data (uart view)`
53			`RXDATA : out slv8; -- receiver data out`
54			`RXVAL : out slbit; -- receiver data valid`
55			`RXERR : out slbit; -- receiver data error (frame error)`
56			`RXACT : out slbit; -- receiver active`
57			`TXSD : out slbit; -- transmit serial data (uart view)`
58			`TXDATA : in slv8; -- transmit data in`
59			`TXENA : in slbit; -- transmit data enable`
60			`TXBUSY : out slbit -- transmit busy`
61			`);`
62			`end component;`
63
64			`component serport_uart_rx is -- serial port uart: receive part`
65			`generic (`
66			`CDWIDTH : positive := 13); -- clk divider width`
67			`port (`
68			`CLK : in slbit; -- clock`
69			`RESET : in slbit; -- reset`
70			`CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting`
71			`RXSD : in slbit; -- receive serial data (uart view)`
72			`RXDATA : out slv8; -- receiver data out`
73			`RXVAL : out slbit; -- receiver data valid`
74			`RXERR : out slbit; -- receiver data error (frame error)`
75			`RXACT : out slbit -- receiver active`
76			`);`
77			`end component;`
78
79			`component serport_uart_tx is -- serial port uart: transmit part`
80			`generic (`
81			`CDWIDTH : positive := 13); -- clk divider width`
82			`port (`
83			`CLK : in slbit; -- clock`
84			`RESET : in slbit; -- reset`
85			`CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting`
86			`TXSD : out slbit; -- transmit serial data (uart view)`
87			`TXDATA : in slv8; -- transmit data in`
88			`TXENA : in slbit; -- transmit data enable`
89			`TXBUSY : out slbit -- transmit busy`
90			`);`
91			`end component;`
92
93			`component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud`
94			`generic (`
95			`CDWIDTH : positive := 13; -- clk divider width`
96			`CDINIT: natural := 15); -- clk divider initial/reset setting`
97			`port (`
98			`CLK : in slbit; -- clock`
99			`CE_MSEC : in slbit; -- 1 msec clock enable`
100			`RESET : in slbit; -- reset`
101			`RXSD : in slbit; -- receive serial data (uart view)`
102			`RXDATA : out slv8; -- receiver data out`
103			`RXVAL : out slbit; -- receiver data valid`
104			`RXERR : out slbit; -- receiver data error (frame error)`
105			`RXACT : out slbit; -- receiver active`
106			`TXSD : out slbit; -- transmit serial data (uart view)`
107			`TXDATA : in slv8; -- transmit data in`
108			`TXENA : in slbit; -- transmit data enable`
109			`TXBUSY : out slbit; -- transmit busy`
110			`ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid`
111	9	wfjm	`ABDONE : out slbit; -- autobaud resync done`
112			`ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting`
113	2	wfjm	`);`
114			`end component;`
115
116			`component serport_uart_autobaud is -- serial port uart: autobauder`
117			`generic (`
118			`CDWIDTH : positive := 13; -- clk divider width`
119			`CDINIT: natural := 15); -- clk divider initial/reset setting`
120			`port (`
121			`CLK : in slbit; -- clock`
122			`CE_MSEC : in slbit; -- 1 msec clock enable`
123			`RESET : in slbit; -- reset`
124			`RXSD : in slbit; -- receive serial data (uart view)`
125			`CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting`
126			`ACT : out slbit; -- active; if 1 clkdiv is invalid`
127			`DONE : out slbit -- resync done`
128			`);`
129			`end component;`
130
131	13	wfjm	`component serport_xonrx is -- serial port: xon/xoff logic rx path`
132			`port (`
133			`CLK : in slbit; -- clock`
134			`RESET : in slbit; -- reset`
135			`ENAXON : in slbit; -- enable xon/xoff handling`
136			`ENAESC : in slbit; -- enable xon/xoff escaping`
137			`UART_RXDATA : in slv8; -- uart data out`
138			`UART_RXVAL : in slbit; -- uart data valid`
139			`RXDATA : out slv8; -- user data out`
140			`RXVAL : out slbit; -- user data valid`
141			`RXHOLD : in slbit; -- user data hold`
142			`RXOVR : out slbit; -- user data overrun`
143			`TXOK : out slbit -- tx channel ok`
144			`);`
145			`end component;`
146
147			`component serport_xontx is -- serial port: xon/xoff logic tx path`
148			`port (`
149			`CLK : in slbit; -- clock`
150			`RESET : in slbit; -- reset`
151			`ENAXON : in slbit; -- enable xon/xoff handling`
152			`ENAESC : in slbit; -- enable xon/xoff escaping`
153			`UART_TXDATA : out slv8; -- uart data in`
154			`UART_TXENA : out slbit; -- uart data enable`
155			`UART_TXBUSY : in slbit; -- uart data busy`
156			`TXDATA : in slv8; -- user data in`
157			`TXENA : in slbit; -- user data enable`
158			`TXBUSY : out slbit; -- user data busy`
159			`RXOK : in slbit; -- rx channel ok`
160			`TXOK : in slbit -- tx channel ok`
161			`);`
162			`end component;`
163
164	16	wfjm	`type serport_moni_type is record -- serport monitor port`
165	13	wfjm	`rxerr : slbit; -- receiver data error (frame error)`
166			`rxovr : slbit; -- receiver data overrun`
167			`rxact : slbit; -- receiver active`
168			`txact : slbit; -- transceiver active`
169			`abact : slbit; -- autobauder active;if 1 clkdiv invalid`
170			`abdone : slbit; -- autobauder resync done`
171			`abclkdiv : slv16; -- autobauder clock divider`
172			`rxok : slbit; -- rx channel ok`
173			`txok : slbit; -- tx channel ok`
174	16	wfjm	`end record serport_moni_type;`
175	13	wfjm
176	16	wfjm	`constant serport_moni_init : serport_moni_type := (`
177	13	wfjm	`'0','0', -- rxerr,rxovr`
178			`'0','0', -- rxact,txact`
179			`'0','0', -- abact,abdone`
180			`(others=>'0'), -- abclkdiv`
181			`'0','0' -- rxok,txok`
182			`);`
183
184			`component serport_1clock is -- serial port module, 1 clock domain`
185			`generic (`
186			`CDWIDTH : positive := 13; -- clk divider width`
187			`CDINIT : natural := 15; -- clk divider initial/reset setting`
188			`RXFAWIDTH : natural := 5; -- rx fifo address width`
189			`TXFAWIDTH : natural := 5); -- tx fifo address width`
190			`port (`
191			`CLK : in slbit; -- clock`
192			`CE_MSEC : in slbit; -- 1 msec clock enable`
193			`RESET : in slbit; -- reset`
194			`ENAXON : in slbit; -- enable xon/xoff handling`
195			`ENAESC : in slbit; -- enable xon/xoff escaping`
196			`RXDATA : out slv8; -- receiver data out`
197			`RXVAL : out slbit; -- receiver data valid`
198			`RXHOLD : in slbit; -- receiver data hold`
199			`TXDATA : in slv8; -- transmit data in`
200			`TXENA : in slbit; -- transmit data enable`
201			`TXBUSY : out slbit; -- transmit busy`
202	16	wfjm	`MONI : out serport_moni_type; -- serport monitor port`
203	13	wfjm	`RXSD : in slbit; -- receive serial data (uart view)`
204			`TXSD : out slbit; -- transmit serial data (uart view)`
205			`RXRTS_N : out slbit; -- receive rts (uart view, act.low)`
206			`TXCTS_N : in slbit -- transmit cts (uart view, act.low)`
207			`);`
208			`end component;`
209
210			`component serport_2clock is -- serial port module, 2 clock domain`
211			`generic (`
212			`CDWIDTH : positive := 13; -- clk divider width`
213			`CDINIT : natural := 15; -- clk divider initial/reset setting`
214			`RXFAWIDTH : natural := 5; -- rx fifo address width`
215			`TXFAWIDTH : natural := 5); -- tx fifo address width`
216			`port (`
217			`CLKU : in slbit; -- clock (backend:user)`
218			`RESET : in slbit; -- reset`
219			`CLKS : in slbit; -- clock (frontend:serial)`
220			`CES_MSEC : in slbit; -- S\|1 msec clock enable`
221			`ENAXON : in slbit; -- U\|enable xon/xoff handling`
222			`ENAESC : in slbit; -- U\|enable xon/xoff escaping`
223			`RXDATA : out slv8; -- U\|receiver data out`
224			`RXVAL : out slbit; -- U\|receiver data valid`
225			`RXHOLD : in slbit; -- U\|receiver data hold`
226			`TXDATA : in slv8; -- U\|transmit data in`
227			`TXENA : in slbit; -- U\|transmit data enable`
228			`TXBUSY : out slbit; -- U\|transmit busy`
229	16	wfjm	`MONI : out serport_moni_type; -- U\|serport monitor port`
230	13	wfjm	`RXSD : in slbit; -- S\|receive serial data (uart view)`
231			`TXSD : out slbit; -- S\|transmit serial data (uart view)`
232			`RXRTS_N : out slbit; -- S\|receive rts (uart view, act.low)`
233			`TXCTS_N : in slbit -- S\|transmit cts (uart view, act.low)`
234			`);`
235			`end component;`
236
237	19	wfjm	`end package serportlib;`

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