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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [xlib/] [xlib.vhd] - Blame information for rev 12

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1 12 wfjm 
-- $Id: xlib.vhd 389 2011-07-07 21:59:00Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name:   xlib
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-- Description:    Xilinx specific components
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--
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-- Dependencies:   -
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-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date         Rev Version  Comment
22 8 wfjm 
-- 2010-11-07   337   1.0.5  add dcm_sp_sfs
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-- 2008-05-23   149   1.0.4  add iob_io(_gen)
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-- 2008-05-22   148   1.0.3  add iob_keeper(_gen);
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-- 2008-05-18   147   1.0.2  add PULL generic to iob_reg_io(_gen)
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-- 2007-12-16   101   1.0.1  add INIT generic ports
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-- 2007-12-08   100   1.0    Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package xlib is
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component iob_reg_i is                  -- registered IOB, input
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  generic (
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    INIT : slbit := '0');               -- initial state
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  port (
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    CLK  : in slbit;                    -- clock
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    CE   : in slbit := '1';             -- clock enable
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    DI   : out slbit;                   -- input data
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    PAD  : in slbit                     -- i/o pad
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  );
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end component;
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component iob_reg_i_gen is              -- registered IOB, input, vector
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  generic (
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    DWIDTH : positive := 16;            -- data port width
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    INIT : slbit := '0');               -- initial state
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  port (
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    CLK  : in slbit;                    -- clock
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    CE   : in slbit := '1';             -- clock enable
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    DI   : out slv(DWIDTH-1 downto 0);  -- input data
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    PAD  : in slv(DWIDTH-1 downto 0)    -- i/o pad
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  );
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end component;
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component iob_reg_o is                  -- registered IOB, output
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  generic (
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    INIT : slbit := '0');               -- initial state
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  port (
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    CLK  : in slbit;                    -- clock
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    CE   : in slbit := '1';             -- clock enable
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    DO   : in slbit;                    -- output data
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    PAD  : out slbit                    -- i/o pad
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  );
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end component;
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component iob_reg_o_gen is              -- registered IOB, output, vector
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  generic (
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    DWIDTH : positive := 16;            -- data port width
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    INIT : slbit := '0');               -- initial state
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  port (
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    CLK  : in slbit;                    -- clock
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    CE   : in slbit := '1';             -- clock enable
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    DO   : in slv(DWIDTH-1 downto 0);   -- output data
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    PAD  : out slv(DWIDTH-1 downto 0)   -- i/o pad
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  );
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end component;
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component iob_reg_io is                 -- registered IOB, in/output
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  generic (
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    INITI : slbit := '0';               -- initial state ( in flop)
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    INITO : slbit := '0';               -- initial state (out flop)
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    INITE : slbit := '0';               -- initial state ( oe flop)
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    PULL : string := "NONE");           -- pull-up,-down or keeper
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  port (
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    CLK  : in slbit;                    -- clock
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    CEI  : in slbit := '1';             -- clock enable ( in flops)
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    CEO  : in slbit := '1';             -- clock enable (out flops)
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    OE   : in slbit;                    -- output enable
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    DI   : out slbit;                   -- input data   (read from pad)
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    DO   : in slbit;                    -- output data  (write  to pad)
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    PAD  : inout slbit                  -- i/o pad
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  );
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end component;
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component iob_reg_io_gen is             -- registered IOB, in/output, vector
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  generic (
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    DWIDTH : positive := 16;            -- data port width
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    INITI : slbit := '0';               -- initial state ( in flop)
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    INITO : slbit := '0';               -- initial state (out flop)
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    INITE : slbit := '0';               -- initial state ( oe flop)
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    PULL : string := "NONE");           -- pull-up,-down or keeper
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  port (
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    CLK  : in slbit;                    -- clock
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    CEI  : in slbit := '1';             -- clock enable ( in flops)
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    CEO  : in slbit := '1';             -- clock enable (out flops)
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    OE   : in slbit;                    -- output enable
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    DI   : out slv(DWIDTH-1 downto 0);  -- input data   (read from pad)
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    DO   : in slv(DWIDTH-1 downto 0);   -- output data  (write  to pad)
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    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
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  );
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end component;
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component iob_io is                     -- un-registered IOB, in/output
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  generic (
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    PULL : string := "NONE");           -- pull-up,-down or keeper
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  port (
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    OE   : in slbit;                    -- output enable
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    DI   : out slbit;                   -- input data   (read from pad)
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    DO   : in slbit;                    -- output data  (write  to pad)
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    PAD  : inout slbit                  -- i/o pad
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  );
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end component;
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component iob_io_gen is                 -- un-registered IOB, in/output, vector
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  generic (
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    DWIDTH : positive := 16;            -- data port width
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    PULL : string := "NONE");           -- pull-up,-down or keeper
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  port (
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    OE   : in slbit;                    -- output enable
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    DI   : out slv(DWIDTH-1 downto 0);  -- input data   (read from pad)
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    DO   : in slv(DWIDTH-1 downto 0);   -- output data  (write  to pad)
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    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
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  );
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end component;
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component iob_keeper is                 -- keeper for IOB
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  port (
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    PAD  : inout slbit                  -- i/o pad
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  );
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end component;
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component iob_keeper_gen is             -- keeper for IOB, vector
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  generic (
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    DWIDTH : positive := 16);           -- data port width
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  port (
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    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
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  );
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end component;
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component dcm_sp_sfs is                 -- DCM_SP as 'simple freq. synthesis'
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  generic (
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    CLKFX_DIVIDE : positive := 2;       -- FX clock divide (1-32)
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    CLKFX_MULTIPLY : positive := 2;     -- FX clock divide (2-32)
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    CLKIN_PERIOD : real := 20.0);       -- CLKIN period (def is 20.0 ns)
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  port (
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    CLKIN : in slbit;                   -- clock input
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    CLKFX : out slbit;                  -- clock output (synthesized freq.)
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    LOCKED : out slbit                  -- dcm locked
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  );
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end component;
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167 12 wfjm 
end package xlib;

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