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-- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name:   xlib
-- Description:    Xilinx specific components
--
-- Dependencies:   -
-- Tool versions:  xst 8.2, 9.1, 9.2, 13.1, 14.5, 14.6; ghdl 0.18-0.29
-- Revision History: 
-- Date         Rev Version  Comment
-- 2013-10-06   538   1.0.10 add s6_cmt_sfs
-- 2013-09-28   535   1.0.9  add s7_cmt_sfs
-- 2011-11-24   432   1.0.8  add iob_oddr2_simple
-- 2011-11-17   426   1.0.7  rename dcm_sp_sfs -> dcm_sfs; remove family generic
-- 2011-11-10   423   1.0.6  add family generic for dcm_sp_sfs
-- 2010-11-07   337   1.0.5  add dcm_sp_sfs
-- 2008-05-23   149   1.0.4  add iob_io(_gen)
-- 2008-05-22   148   1.0.3  add iob_keeper(_gen);
-- 2008-05-18   147   1.0.2  add PULL generic to iob_reg_io(_gen)
-- 2007-12-16   101   1.0.1  add INIT generic ports
-- 2007-12-08   100   1.0    Initial version 
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package xlib is
 
component iob_reg_i is                  -- registered IOB, input
  generic (
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DI   : out slbit;                   -- input data
    PAD  : in slbit                     -- i/o pad
  );
end component;
 
component iob_reg_i_gen is              -- registered IOB, input, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DI   : out slv(DWIDTH-1 downto 0);  -- input data
    PAD  : in slv(DWIDTH-1 downto 0)    -- i/o pad
  );
end component;
 
component iob_reg_o is                  -- registered IOB, output
  generic (
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DO   : in slbit;                    -- output data
    PAD  : out slbit                    -- i/o pad
  );
end component;
 
component iob_reg_o_gen is              -- registered IOB, output, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DO   : in slv(DWIDTH-1 downto 0);   -- output data
    PAD  : out slv(DWIDTH-1 downto 0)   -- i/o pad
  );
end component;
 
component iob_reg_io is                 -- registered IOB, in/output
  generic (
    INITI : slbit := '0';               -- initial state ( in flop)
    INITO : slbit := '0';               -- initial state (out flop)
    INITE : slbit := '0';               -- initial state ( oe flop)
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    CLK  : in slbit;                    -- clock
    CEI  : in slbit := '1';             -- clock enable ( in flops)
    CEO  : in slbit := '1';             -- clock enable (out flops)
    OE   : in slbit;                    -- output enable
    DI   : out slbit;                   -- input data   (read from pad)
    DO   : in slbit;                    -- output data  (write  to pad)
    PAD  : inout slbit                  -- i/o pad
  );
end component;
 
component iob_reg_io_gen is             -- registered IOB, in/output, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    INITI : slbit := '0';               -- initial state ( in flop)
    INITO : slbit := '0';               -- initial state (out flop)
    INITE : slbit := '0';               -- initial state ( oe flop)
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    CLK  : in slbit;                    -- clock
    CEI  : in slbit := '1';             -- clock enable ( in flops)
    CEO  : in slbit := '1';             -- clock enable (out flops)
    OE   : in slbit;                    -- output enable
    DI   : out slv(DWIDTH-1 downto 0);  -- input data   (read from pad)
    DO   : in slv(DWIDTH-1 downto 0);   -- output data  (write  to pad)
    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
  );
end component;
 
component iob_io is                     -- un-registered IOB, in/output
  generic (
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    OE   : in slbit;                    -- output enable
    DI   : out slbit;                   -- input data   (read from pad)
    DO   : in slbit;                    -- output data  (write  to pad)
    PAD  : inout slbit                  -- i/o pad
  );
end component;
 
component iob_oddr2_simple is           -- DDR2 output I/O pad
  generic (
    ALIGN : string := "NONE";           -- ddr_alignment
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DO0  : in slbit;                    -- output data
    DO1  : in slbit;                    -- output data
    PAD  : out slbit                    -- i/o pad
  );
end component;
 
component iob_io_gen is                 -- un-registered IOB, in/output, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    OE   : in slbit;                    -- output enable
    DI   : out slv(DWIDTH-1 downto 0);  -- input data   (read from pad)
    DO   : in slv(DWIDTH-1 downto 0);   -- output data  (write  to pad)
    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
  );
end component;
 
component iob_keeper is                 -- keeper for IOB
  port (
    PAD  : inout slbit                  -- i/o pad
  );
end component;
 
component iob_keeper_gen is             -- keeper for IOB, vector
  generic (
    DWIDTH : positive := 16);           -- data port width
  port (
    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
  );
end component;
 
component dcm_sfs is                    -- DCM for simple frequency synthesis
  generic (
    CLKFX_DIVIDE : positive := 2;       -- FX clock divide (1-32)
    CLKFX_MULTIPLY : positive := 2;     -- FX clock multiply (2-32) (1->no DCM)
    CLKIN_PERIOD : real := 20.0);       -- CLKIN period (def is 20.0 ns)
  port (
    CLKIN : in slbit;                   -- clock input
    CLKFX : out slbit;                  -- clock output (synthesized freq.) 
    LOCKED : out slbit                  -- dcm locked
  );
end component;
 
component s7_cmt_sfs is                 -- 7-Series CMT for simple freq. synth.
  generic (
    VCO_DIVIDE : positive := 1;         -- vco clock divide
    VCO_MULTIPLY : positive := 1;       -- vco clock multiply 
    OUT_DIVIDE : positive := 1;         -- output divide
    CLKIN_PERIOD : real := 10.0;        -- CLKIN period (def is 10.0 ns)
    CLKIN_JITTER : real := 0.01;        -- CLKIN jitter (def is 10 ps)
    STARTUP_WAIT : boolean := false;    -- hold FPGA startup till LOCKED
    GEN_TYPE : string := "PLL");        -- PLL or MMCM
  port (
    CLKIN : in slbit;                   -- clock input
    CLKFX : out slbit;                  -- clock output (synthesized freq.) 
    LOCKED : out slbit                  -- pll/mmcm locked
  );
end component;
 
component s6_cmt_sfs is                 -- Spartan-6 CMT for simple freq. synth.
  generic (
    VCO_DIVIDE : positive := 1;         -- vco clock divide
    VCO_MULTIPLY : positive := 1;       -- vco clock multiply 
    OUT_DIVIDE : positive := 1;         -- output divide
    CLKIN_PERIOD : real := 10.0;        -- CLKIN period (def is 10.0 ns)
    CLKIN_JITTER : real := 0.01;        -- CLKIN jitter (def is 10 ps)
    STARTUP_WAIT : boolean := false;    -- hold FPGA startup till LOCKED
    GEN_TYPE : string := "PLL");        -- PLL or DCM
  port (
    CLKIN : in slbit;                   -- clock input
    CLKFX : out slbit;                  -- clock output (synthesized freq.) 
    LOCKED : out slbit                  -- pll/mmcm locked
  );
end component;
 
end package xlib;

Line No.	Rev	Author	Line
1	22	wfjm	`-- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $`
2	2	wfjm	`--`
3	22	wfjm	`-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4	2	wfjm	`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Package Name: xlib`
16			`-- Description: Xilinx specific components`
17			`--`
18			`-- Dependencies: -`
19	22	wfjm	`-- Tool versions: xst 8.2, 9.1, 9.2, 13.1, 14.5, 14.6; ghdl 0.18-0.29`
20	2	wfjm	`-- Revision History:`
21			`-- Date Rev Version Comment`
22	22	wfjm	`-- 2013-10-06 538 1.0.10 add s6_cmt_sfs`
23			`-- 2013-09-28 535 1.0.9 add s7_cmt_sfs`
24	15	wfjm	`-- 2011-11-24 432 1.0.8 add iob_oddr2_simple`
25	13	wfjm	`-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic`
26			`-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs`
27	8	wfjm	`-- 2010-11-07 337 1.0.5 add dcm_sp_sfs`
28	2	wfjm	`-- 2008-05-23 149 1.0.4 add iob_io(_gen)`
29			`-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);`
30			`-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)`
31			`-- 2007-12-16 101 1.0.1 add INIT generic ports`
32			`-- 2007-12-08 100 1.0 Initial version`
33			`------------------------------------------------------------------------------`
34
35			`library ieee;`
36			`use ieee.std_logic_1164.all;`
37
38			`use work.slvtypes.all;`
39
40			`package xlib is`
41
42			`component iob_reg_i is -- registered IOB, input`
43			`generic (`
44			`INIT : slbit := '0'); -- initial state`
45			`port (`
46			`CLK : in slbit; -- clock`
47			`CE : in slbit := '1'; -- clock enable`
48			`DI : out slbit; -- input data`
49			`PAD : in slbit -- i/o pad`
50			`);`
51			`end component;`
52
53			`component iob_reg_i_gen is -- registered IOB, input, vector`
54			`generic (`
55			`DWIDTH : positive := 16; -- data port width`
56			`INIT : slbit := '0'); -- initial state`
57			`port (`
58			`CLK : in slbit; -- clock`
59			`CE : in slbit := '1'; -- clock enable`
60			`DI : out slv(DWIDTH-1 downto 0); -- input data`
61			`PAD : in slv(DWIDTH-1 downto 0) -- i/o pad`
62			`);`
63			`end component;`
64
65			`component iob_reg_o is -- registered IOB, output`
66			`generic (`
67			`INIT : slbit := '0'); -- initial state`
68			`port (`
69			`CLK : in slbit; -- clock`
70			`CE : in slbit := '1'; -- clock enable`
71			`DO : in slbit; -- output data`
72			`PAD : out slbit -- i/o pad`
73			`);`
74			`end component;`
75
76			`component iob_reg_o_gen is -- registered IOB, output, vector`
77			`generic (`
78			`DWIDTH : positive := 16; -- data port width`
79			`INIT : slbit := '0'); -- initial state`
80			`port (`
81			`CLK : in slbit; -- clock`
82			`CE : in slbit := '1'; -- clock enable`
83			`DO : in slv(DWIDTH-1 downto 0); -- output data`
84			`PAD : out slv(DWIDTH-1 downto 0) -- i/o pad`
85			`);`
86			`end component;`
87
88			`component iob_reg_io is -- registered IOB, in/output`
89			`generic (`
90			`INITI : slbit := '0'; -- initial state ( in flop)`
91			`INITO : slbit := '0'; -- initial state (out flop)`
92			`INITE : slbit := '0'; -- initial state ( oe flop)`
93			`PULL : string := "NONE"); -- pull-up,-down or keeper`
94			`port (`
95			`CLK : in slbit; -- clock`
96			`CEI : in slbit := '1'; -- clock enable ( in flops)`
97			`CEO : in slbit := '1'; -- clock enable (out flops)`
98			`OE : in slbit; -- output enable`
99			`DI : out slbit; -- input data (read from pad)`
100			`DO : in slbit; -- output data (write to pad)`
101			`PAD : inout slbit -- i/o pad`
102			`);`
103			`end component;`
104
105			`component iob_reg_io_gen is -- registered IOB, in/output, vector`
106			`generic (`
107			`DWIDTH : positive := 16; -- data port width`
108			`INITI : slbit := '0'; -- initial state ( in flop)`
109			`INITO : slbit := '0'; -- initial state (out flop)`
110			`INITE : slbit := '0'; -- initial state ( oe flop)`
111			`PULL : string := "NONE"); -- pull-up,-down or keeper`
112			`port (`
113			`CLK : in slbit; -- clock`
114			`CEI : in slbit := '1'; -- clock enable ( in flops)`
115			`CEO : in slbit := '1'; -- clock enable (out flops)`
116			`OE : in slbit; -- output enable`
117			`DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)`
118			`DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)`
119			`PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad`
120			`);`
121			`end component;`
122
123			`component iob_io is -- un-registered IOB, in/output`
124			`generic (`
125			`PULL : string := "NONE"); -- pull-up,-down or keeper`
126			`port (`
127			`OE : in slbit; -- output enable`
128			`DI : out slbit; -- input data (read from pad)`
129			`DO : in slbit; -- output data (write to pad)`
130			`PAD : inout slbit -- i/o pad`
131			`);`
132			`end component;`
133
134	15	wfjm	`component iob_oddr2_simple is -- DDR2 output I/O pad`
135			`generic (`
136			`ALIGN : string := "NONE"; -- ddr_alignment`
137			`INIT : slbit := '0'); -- initial state`
138			`port (`
139			`CLK : in slbit; -- clock`
140			`CE : in slbit := '1'; -- clock enable`
141			`DO0 : in slbit; -- output data`
142			`DO1 : in slbit; -- output data`
143			`PAD : out slbit -- i/o pad`
144			`);`
145			`end component;`
146
147	2	wfjm	`component iob_io_gen is -- un-registered IOB, in/output, vector`
148			`generic (`
149			`DWIDTH : positive := 16; -- data port width`
150			`PULL : string := "NONE"); -- pull-up,-down or keeper`
151			`port (`
152			`OE : in slbit; -- output enable`
153			`DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)`
154			`DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)`
155			`PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad`
156			`);`
157			`end component;`
158
159			`component iob_keeper is -- keeper for IOB`
160			`port (`
161			`PAD : inout slbit -- i/o pad`
162			`);`
163			`end component;`
164
165			`component iob_keeper_gen is -- keeper for IOB, vector`
166			`generic (`
167			`DWIDTH : positive := 16); -- data port width`
168			`port (`
169			`PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad`
170			`);`
171			`end component;`
172
173	13	wfjm	`component dcm_sfs is -- DCM for simple frequency synthesis`
174	8	wfjm	`generic (`
175			`CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)`
176	22	wfjm	`CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)`
177	8	wfjm	`CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)`
178			`port (`
179			`CLKIN : in slbit; -- clock input`
180			`CLKFX : out slbit; -- clock output (synthesized freq.)`
181			`LOCKED : out slbit -- dcm locked`
182			`);`
183			`end component;`
184
185	22	wfjm	`component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.`
186			`generic (`
187			`VCO_DIVIDE : positive := 1; -- vco clock divide`
188			`VCO_MULTIPLY : positive := 1; -- vco clock multiply`
189			`OUT_DIVIDE : positive := 1; -- output divide`
190			`CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)`
191			`CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)`
192			`STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED`
193			`GEN_TYPE : string := "PLL"); -- PLL or MMCM`
194			`port (`
195			`CLKIN : in slbit; -- clock input`
196			`CLKFX : out slbit; -- clock output (synthesized freq.)`
197			`LOCKED : out slbit -- pll/mmcm locked`
198			`);`
199			`end component;`
200
201			`component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.`
202			`generic (`
203			`VCO_DIVIDE : positive := 1; -- vco clock divide`
204			`VCO_MULTIPLY : positive := 1; -- vco clock multiply`
205			`OUT_DIVIDE : positive := 1; -- output divide`
206			`CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)`
207			`CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)`
208			`STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED`
209			`GEN_TYPE : string := "PLL"); -- PLL or DCM`
210			`port (`
211			`CLKIN : in slbit; -- clock input`
212			`CLKFX : out slbit; -- clock output (synthesized freq.)`
213			`LOCKED : out slbit -- pll/mmcm locked`
214			`);`
215			`end component;`
216
217	12	wfjm	`end package xlib;`

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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [xlib/] [xlib.vhd] - Blame information for rev 26