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-- $Id: pdp11.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: pdp11
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-- Description: Definitions for pdp11 components
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--
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-- Dependencies: -
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.4.8 now numeric_std clean
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-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
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-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
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-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
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-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
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-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
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-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
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-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
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-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
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-- reassign cp command codes and rename: c_cp_func_...
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-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
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-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
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-- reassign rbus adresses and rename: c_rb_addr_...
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-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
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-- -> c_stat_rbf_...
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-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
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-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
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-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
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-- rename c_rp_addr_* -> c_rb_addr_*
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-- 2010-03-21 270 1.2.6 add pdp11_du_drv
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-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
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-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
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-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
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-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
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-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
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| 48 |
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-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
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-- move (and rename) intbus defs to iblib package;
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-- move intbus devices to ibdlib package;
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-- rename ubf_ --> ibf_;
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-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
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-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
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-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
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-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
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-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
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-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
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-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
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-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
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-- _vmbox,_mmu interface changed
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-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
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-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
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-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
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-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
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-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
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-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
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-- mod pdp11_intmap;
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-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
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-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- add ibdr_kw11l.
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-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
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-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
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-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
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-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
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-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
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-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
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-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
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-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.rblib.all;
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package pdp11 is
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type psw_type is record -- processor status
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cmode : slv2; -- current mode
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pmode : slv2; -- previous mode
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rset : slbit; -- register set
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pri : slv3; -- processor priority
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tflag : slbit; -- trace flag
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cc : slv4; -- condition codes (NZVC).
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end record psw_type;
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constant psw_init : psw_type := (
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"00","00", -- cmode, pmode (=kernel)
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'0',"111",'0', -- rset, pri (=7), tflag
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"0000" -- cc NZVC=0
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);
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constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
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constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
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constant c_psw_umode : slv2 := "11"; -- processor mode: user
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subtype psw_ibf_cmode is integer range 15 downto 14;
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subtype psw_ibf_pmode is integer range 13 downto 12;
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constant psw_ibf_rset: integer := 11;
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subtype psw_ibf_pri is integer range 7 downto 5;
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constant psw_ibf_tflag: integer := 4;
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subtype psw_ibf_cc is integer range 3 downto 0;
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type sarsdr_type is record -- combined SAR/SDR MMU status
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saf : slv16; -- segment address field
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slf : slv7; -- segment length field
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ed : slbit; -- expansion direction
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acf : slv3; -- access control field
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end record sarsdr_type;
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constant sarsdr_init : sarsdr_type := (
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(others=>'0'), -- saf
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"0000000",'0',"000" -- slf, ed, acf
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);
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type dpath_cntl_type is record -- data path control
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gpr_asrc : slv3; -- src register address
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gpr_adst : slv3; -- dst register address
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gpr_mode : slv2; -- psw mode for gpr access
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gpr_rset : slbit; -- register set
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gpr_we : slbit; -- gpr write enable
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gpr_bytop : slbit; -- gpr high byte enable
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gpr_pcinc : slbit; -- pc increment enable
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psr_ccwe : slbit; -- enable update cc
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psr_we: slbit; -- write enable psw (from DIN)
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psr_func : slv3; -- write function psw (from DIN)
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dsrc_sel : slbit; -- src data register source select
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dsrc_we : slbit; -- src data register write enable
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ddst_sel : slbit; -- dst data register source select
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ddst_we : slbit; -- dst data register write enable
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dtmp_sel : slv2; -- tmp data register source select
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dtmp_we : slbit; -- tmp data register write enable
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ounit_asel : slv2; -- ounit a port selector
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ounit_azero : slbit; -- ounit a port force zero
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ounit_const : slv9; -- ounit b port const
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ounit_bsel : slv2; -- ounit b port selector
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ounit_opsub : slbit; -- ounit operation
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aunit_srcmod : slv2; -- aunit src port modifier
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aunit_dstmod : slv2; -- aunit dst port modifier
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aunit_cimod : slv2; -- aunit ci port modifier
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aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
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aunit_ccmode : slv3; -- aunit cc port mode
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aunit_bytop : slbit; -- aunit byte operation
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lunit_func : slv4; -- lunit function
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lunit_bytop : slbit; -- lunit byte operation
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munit_func : slv2; -- munit function
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munit_s_div : slbit; -- munit s_opg_div state
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munit_s_div_cn : slbit; -- munit s_opg_div_cn state
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munit_s_div_cr : slbit; -- munit s_opg_div_cr state
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munit_s_ash : slbit; -- munit s_opg_ash state
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munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
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munit_s_ashc : slbit; -- munit s_opg_ashc state
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munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
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ireg_we : slbit; -- ireg register write enable
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cres_sel : slv3; -- result bus (cres) select
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dres_sel : slv3; -- result bus (dres) select
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vmaddr_sel : slv2; -- virtual address select
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cpdout_we : slbit; -- capture dres for cpdout
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end record dpath_cntl_type;
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constant dpath_cntl_init : dpath_cntl_type := (
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"000","000","00",'0','0','0','0', -- gpr
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'0','0',"000", -- psr
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'0','0','0','0',"00",'0', -- dsrc,..,dtmp
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"00",'0',"000000000","00",'0', -- ounit
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"00","00","00",'0',"000",'0', -- aunit
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"0000",'0', -- lunit
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"00",'0','0','0','0','0','0','0', -- munit
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'0',"000","000","00",'0' -- rest
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);
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| 187 |
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constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
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constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
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constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
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| 190 |
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constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
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| 191 |
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| 192 |
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constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
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constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
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constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
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constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
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| 197 |
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constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
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constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
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constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
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| 200 |
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constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
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constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
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| 202 |
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constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
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| 203 |
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constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
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| 204 |
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constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
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| 205 |
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| 206 |
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constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
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| 207 |
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constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
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| 208 |
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constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
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| 209 |
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constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
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| 210 |
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| 211 |
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type dpath_stat_type is record -- data path status
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| 212 |
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ccout_z : slbit; -- current effective Z cc flag
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| 213 |
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shc_tc : slbit; -- last shc cycle (shc==0)
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| 214 |
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div_cr : slbit; -- division: reminder correction needed
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| 215 |
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div_cq : slbit; -- division: quotient correction needed
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| 216 |
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div_zero : slbit; -- division: divident or divisor zero
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| 217 |
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div_ovfl : slbit; -- division: overflow
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| 218 |
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end record dpath_stat_type;
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| 219 |
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| 220 |
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constant dpath_stat_init : dpath_stat_type := (others=>'0');
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| 221 |
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| 222 |
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type decode_stat_type is record -- decode status
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| 223 |
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is_dstmode0 : slbit; -- dest. is register mode
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| 224 |
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is_srcpc : slbit; -- source is pc
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| 225 |
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is_srcpcmode1 : slbit; -- source is pc and mode=1
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| 226 |
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is_dstpc : slbit; -- dest. is pc
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| 227 |
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is_dstw_reg : slbit; -- dest. register to be written
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| 228 |
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is_dstw_pc : slbit; -- pc register to be written
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| 229 |
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is_rmwop : slbit; -- read-modify-write operation
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| 230 |
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is_bytop : slbit; -- byte operation
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| 231 |
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is_res : slbit; -- reserved operation code
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| 232 |
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op_rtt : slbit; -- RTT instruction
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| 233 |
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op_mov : slbit; -- MOV instruction
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| 234 |
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trap_vec : slv3; -- trap vector addr bits 4:2
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| 235 |
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force_srcsp : slbit; -- force src register to be sp
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| 236 |
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updt_dstadsrc : slbit; -- update dsrc in dsta flow
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| 237 |
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wfjm |
aunit_srcmod : slv2; -- aunit src port modifier
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| 238 |
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aunit_dstmod : slv2; -- aunit dst port modifier
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| 239 |
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aunit_cimod : slv2; -- aunit ci port modifier
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| 240 |
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aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
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| 241 |
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aunit_ccmode : slv3; -- aunit cc port mode
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| 242 |
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lunit_func : slv4; -- lunit function
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| 243 |
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munit_func : slv2; -- munit function
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| 244 |
2 |
wfjm |
res_sel : slv3; -- result bus (cres/dres) select
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| 245 |
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fork_op : slv4; -- op fork after idecode state
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| 246 |
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fork_srcr : slv2; -- src-read fork after idecode state
|
| 247 |
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fork_dstr : slv2; -- dst-read fork after src read state
|
| 248 |
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fork_dsta : slv2; -- dst-addr fork after idecode state
|
| 249 |
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fork_opg : slv4; -- opg fork
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| 250 |
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fork_opa : slv3; -- opa fork
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| 251 |
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do_fork_op : slbit; -- execute fork_op
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| 252 |
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do_fork_srcr : slbit; -- execute fork_srcr
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| 253 |
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do_fork_dstr : slbit; -- execute fork_dstr
|
| 254 |
|
|
do_fork_dsta : slbit; -- execute fork_dsta
|
| 255 |
|
|
do_fork_opg : slbit; -- execute fork_opg
|
| 256 |
|
|
do_pref_dec : slbit; -- can do prefetch at decode phase
|
| 257 |
|
|
end record decode_stat_type;
|
| 258 |
|
|
|
| 259 |
|
|
constant decode_stat_init : decode_stat_type := (
|
| 260 |
|
|
'0','0','0','0','0','0','0','0','0', -- is_
|
| 261 |
|
|
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
|
| 262 |
8 |
wfjm |
"00","00","00",'0',"000", -- aunit_
|
| 263 |
|
|
"0000","00","000", -- lunit_, munit_, res_
|
| 264 |
2 |
wfjm |
"0000","00","00","00","0000","000", -- fork_
|
| 265 |
|
|
'0','0','0','0','0', -- do_fork_
|
| 266 |
|
|
'0' -- do_pref_
|
| 267 |
|
|
);
|
| 268 |
|
|
|
| 269 |
|
|
constant c_fork_op_halt : slv4 := "0000";
|
| 270 |
|
|
constant c_fork_op_wait : slv4 := "0001";
|
| 271 |
|
|
constant c_fork_op_rtti : slv4 := "0010";
|
| 272 |
|
|
constant c_fork_op_trap : slv4 := "0011";
|
| 273 |
|
|
constant c_fork_op_reset: slv4 := "0100";
|
| 274 |
|
|
constant c_fork_op_rts : slv4 := "0101";
|
| 275 |
|
|
constant c_fork_op_spl : slv4 := "0110";
|
| 276 |
|
|
constant c_fork_op_mcc : slv4 := "0111";
|
| 277 |
|
|
constant c_fork_op_br : slv4 := "1000";
|
| 278 |
|
|
constant c_fork_op_mark : slv4 := "1001";
|
| 279 |
|
|
constant c_fork_op_sob : slv4 := "1010";
|
| 280 |
|
|
constant c_fork_op_mtp : slv4 := "1011";
|
| 281 |
|
|
|
| 282 |
|
|
constant c_fork_srcr_def : slv2:= "00";
|
| 283 |
|
|
constant c_fork_srcr_inc : slv2:= "01";
|
| 284 |
|
|
constant c_fork_srcr_dec : slv2:= "10";
|
| 285 |
|
|
constant c_fork_srcr_ind : slv2:= "11";
|
| 286 |
|
|
|
| 287 |
|
|
constant c_fork_dstr_def : slv2:= "00";
|
| 288 |
|
|
constant c_fork_dstr_inc : slv2:= "01";
|
| 289 |
|
|
constant c_fork_dstr_dec : slv2:= "10";
|
| 290 |
|
|
constant c_fork_dstr_ind : slv2:= "11";
|
| 291 |
|
|
|
| 292 |
|
|
constant c_fork_dsta_def : slv2:= "00";
|
| 293 |
|
|
constant c_fork_dsta_inc : slv2:= "01";
|
| 294 |
|
|
constant c_fork_dsta_dec : slv2:= "10";
|
| 295 |
|
|
constant c_fork_dsta_ind : slv2:= "11";
|
| 296 |
|
|
|
| 297 |
|
|
constant c_fork_opg_gen : slv4 := "0000";
|
| 298 |
|
|
constant c_fork_opg_wdef : slv4 := "0001";
|
| 299 |
|
|
constant c_fork_opg_winc : slv4 := "0010";
|
| 300 |
|
|
constant c_fork_opg_wdec : slv4 := "0011";
|
| 301 |
|
|
constant c_fork_opg_wind : slv4 := "0100";
|
| 302 |
|
|
constant c_fork_opg_mul : slv4 := "0101";
|
| 303 |
|
|
constant c_fork_opg_div : slv4 := "0110";
|
| 304 |
|
|
constant c_fork_opg_ash : slv4 := "0111";
|
| 305 |
|
|
constant c_fork_opg_ashc : slv4 := "1000";
|
| 306 |
|
|
|
| 307 |
|
|
constant c_fork_opa_jsr : slv3 := "000";
|
| 308 |
|
|
constant c_fork_opa_jmp : slv3 := "001";
|
| 309 |
|
|
constant c_fork_opa_mtp : slv3 := "010";
|
| 310 |
|
|
constant c_fork_opa_mfp_reg : slv3 := "011";
|
| 311 |
|
|
constant c_fork_opa_mfp_mem : slv3 := "100";
|
| 312 |
|
|
|
| 313 |
|
|
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
|
| 314 |
|
|
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
|
| 315 |
|
|
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
|
| 316 |
|
|
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
|
| 317 |
|
|
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
|
| 318 |
|
|
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
|
| 319 |
|
|
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
|
| 320 |
|
|
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
|
| 321 |
|
|
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
|
| 322 |
|
|
constant c_cpurust_recrsv : slv4 := "1001"; -- recursive red-stack halt
|
| 323 |
|
|
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
|
| 324 |
|
|
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
|
| 325 |
|
|
|
| 326 |
|
|
type cpustat_type is record -- CPU status
|
| 327 |
|
|
cmdbusy : slbit; -- command busy
|
| 328 |
|
|
cmdack : slbit; -- command acknowledge
|
| 329 |
|
|
cmderr : slbit; -- command error
|
| 330 |
|
|
cmdmerr : slbit; -- command memory access error
|
| 331 |
|
|
cpugo : slbit; -- CPU go state
|
| 332 |
|
|
cpustep : slbit; -- CPU step flag
|
| 333 |
|
|
cpuhalt : slbit; -- CPU halt flag
|
| 334 |
|
|
cpuwait : slbit; -- CPU wait flag
|
| 335 |
|
|
cpurust : slv4; -- CPU run status
|
| 336 |
|
|
cpfunc : slv5; -- current control port function
|
| 337 |
|
|
cprnum : slv3; -- current control port register number
|
| 338 |
|
|
waitsusp : slbit; -- WAIT instruction suspended
|
| 339 |
|
|
intvect : slv9_2; -- current interrupt vector
|
| 340 |
|
|
trap_mmu : slbit; -- mmu trace trap pending
|
| 341 |
|
|
trap_ysv : slbit; -- ysv trap pending
|
| 342 |
|
|
prefdone : slbit; -- prefetch done
|
| 343 |
|
|
do_gprwe : slbit; -- pending gpr_we
|
| 344 |
|
|
do_intrsv : slbit; -- active rsv interrupt sequence
|
| 345 |
|
|
end record cpustat_type;
|
| 346 |
|
|
|
| 347 |
|
|
constant cpustat_init : cpustat_type := (
|
| 348 |
|
|
'0','0','0','0', -- cmd..
|
| 349 |
|
|
'0','0','0','0', -- cpu..
|
| 350 |
|
|
c_cpurust_init, -- cpurust
|
| 351 |
|
|
"00000","000", -- cpfunc, cprnum
|
| 352 |
|
|
'0', -- waitsusp
|
| 353 |
|
|
(others=>'0'), -- intvect
|
| 354 |
|
|
'0','0','0', -- trap_(mmu|ysv), prefdone
|
| 355 |
|
|
'0','0' -- do_gprwe, do_intrsv
|
| 356 |
|
|
);
|
| 357 |
|
|
|
| 358 |
|
|
type cpuerr_type is record -- CPU error register
|
| 359 |
|
|
illhlt : slbit; -- illegal halt (in non-kernel mode)
|
| 360 |
|
|
adderr : slbit; -- address error (odd, jmp/jsr reg)
|
| 361 |
|
|
nxm : slbit; -- non-existent memory
|
| 362 |
|
|
iobto : slbit; -- I/O bus timeout (non-exist UB)
|
| 363 |
|
|
ysv : slbit; -- yellow stack violation
|
| 364 |
|
|
rsv : slbit; -- red stack violation
|
| 365 |
|
|
end record cpuerr_type;
|
| 366 |
|
|
|
| 367 |
|
|
constant cpuerr_init : cpuerr_type := (others=>'0');
|
| 368 |
|
|
|
| 369 |
|
|
type vm_cntl_type is record -- virt memory control port
|
| 370 |
|
|
req : slbit; -- request
|
| 371 |
|
|
wacc : slbit; -- write access
|
| 372 |
|
|
macc : slbit; -- modify access (r-m-w sequence)
|
| 373 |
|
|
cacc : slbit; -- console access
|
| 374 |
|
|
bytop : slbit; -- byte operation
|
| 375 |
|
|
dspace : slbit; -- dspace operation
|
| 376 |
|
|
kstack : slbit; -- access through kernel stack
|
| 377 |
|
|
intrsv : slbit; -- active rsv interrupt sequence
|
| 378 |
|
|
mode : slv2; -- mode
|
| 379 |
|
|
trap_done : slbit; -- mmu trap taken (to set ssr0 bit)
|
| 380 |
|
|
end record vm_cntl_type;
|
| 381 |
|
|
|
| 382 |
|
|
constant vm_cntl_init : vm_cntl_type := (
|
| 383 |
|
|
'0','0','0','0', -- req, wacc, macc,cacc
|
| 384 |
|
|
'0','0','0', -- bytop, dspace, kstack
|
| 385 |
|
|
'0',"00",'0' -- intrsv, mode, trap_done
|
| 386 |
|
|
);
|
| 387 |
|
|
|
| 388 |
|
|
type vm_stat_type is record -- virt memory status port
|
| 389 |
|
|
ack : slbit; -- acknowledge
|
| 390 |
|
|
err : slbit; -- error (see err_xxx for reason)
|
| 391 |
|
|
fail : slbit; -- failure (machine check)
|
| 392 |
|
|
err_odd : slbit; -- abort: odd address error
|
| 393 |
|
|
err_mmu : slbit; -- abort: mmu reject
|
| 394 |
|
|
err_nxm : slbit; -- abort: non-existing memory
|
| 395 |
|
|
err_iobto : slbit; -- abort: non-existing I/O resource
|
| 396 |
|
|
err_rsv : slbit; -- abort: red stack violation
|
| 397 |
|
|
trap_ysv : slbit; -- trap: yellow stack violation
|
| 398 |
|
|
trap_mmu : slbit; -- trap: mmu trace trap
|
| 399 |
|
|
end record vm_stat_type;
|
| 400 |
|
|
|
| 401 |
|
|
constant vm_stat_init : vm_stat_type := (others=>'0');
|
| 402 |
|
|
|
| 403 |
|
|
type em_mreq_type is record -- external memory - master request
|
| 404 |
|
|
req : slbit; -- request
|
| 405 |
|
|
we : slbit; -- write enable
|
| 406 |
|
|
be : slv2; -- byte enables
|
| 407 |
|
|
cancel : slbit; -- cancel request
|
| 408 |
|
|
addr : slv22_1; -- address
|
| 409 |
|
|
din : slv16; -- data in (input to memory)
|
| 410 |
|
|
end record em_mreq_type;
|
| 411 |
|
|
|
| 412 |
|
|
constant em_mreq_init : em_mreq_type := (
|
| 413 |
|
|
'0','0',"00",'0', -- req, we, be, cancel
|
| 414 |
|
|
(others=>'0'),(others=>'0') -- addr, din
|
| 415 |
|
|
);
|
| 416 |
|
|
|
| 417 |
|
|
type em_sres_type is record -- external memory - slave response
|
| 418 |
|
|
ack_r : slbit; -- acknowledge read
|
| 419 |
|
|
ack_w : slbit; -- acknowledge write
|
| 420 |
|
|
dout : slv16; -- data out (output from memory)
|
| 421 |
|
|
end record em_sres_type;
|
| 422 |
|
|
|
| 423 |
|
|
constant em_sres_init : em_sres_type := (
|
| 424 |
|
|
'0','0', -- ack_r, ack_w
|
| 425 |
|
|
(others=>'0') -- dout
|
| 426 |
|
|
);
|
| 427 |
|
|
|
| 428 |
|
|
type mmu_cntl_type is record -- mmu control port
|
| 429 |
|
|
req : slbit; -- translate request
|
| 430 |
|
|
wacc : slbit; -- write access
|
| 431 |
|
|
macc : slbit; -- modify access (r-m-w sequence)
|
| 432 |
|
|
cacc : slbit; -- console access (bypass mmu)
|
| 433 |
|
|
dspace : slbit; -- dspace access
|
| 434 |
|
|
mode : slv2; -- processor mode
|
| 435 |
|
|
trap_done : slbit; -- mmu trap taken (set ssr0 bit)
|
| 436 |
|
|
end record mmu_cntl_type;
|
| 437 |
|
|
|
| 438 |
|
|
constant mmu_cntl_init : mmu_cntl_type := (
|
| 439 |
|
|
'0','0','0','0', -- req, wacc, macc, cacc
|
| 440 |
|
|
'0',"00",'0' -- dspace, mode, trap_done
|
| 441 |
|
|
);
|
| 442 |
|
|
|
| 443 |
|
|
type mmu_stat_type is record -- mmu status port
|
| 444 |
|
|
vaok : slbit; -- virtual address valid
|
| 445 |
|
|
trap : slbit; -- mmu trap request
|
| 446 |
|
|
ena_mmu : slbit; -- mmu enable (ssr0 bit 0)
|
| 447 |
|
|
ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4)
|
| 448 |
|
|
ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5)
|
| 449 |
|
|
end record mmu_stat_type;
|
| 450 |
|
|
|
| 451 |
|
|
constant mmu_stat_init : mmu_stat_type := (others=>'0');
|
| 452 |
|
|
|
| 453 |
|
|
type mmu_moni_type is record -- mmu monitor port
|
| 454 |
|
|
istart : slbit; -- instruction start
|
| 455 |
|
|
idone : slbit; -- instruction done
|
| 456 |
|
|
pc : slv16; -- PC of new instruction
|
| 457 |
|
|
regmod : slbit; -- register modified
|
| 458 |
|
|
regnum : slv3; -- register number
|
| 459 |
|
|
delta : slv4; -- register offset
|
| 460 |
|
|
isdec : slbit; -- offset to be subtracted
|
| 461 |
|
|
trace_prev : slbit; -- use ssr12 trace state of prev. state
|
| 462 |
|
|
end record mmu_moni_type;
|
| 463 |
|
|
|
| 464 |
|
|
constant mmu_moni_init : mmu_moni_type := (
|
| 465 |
|
|
'0','0',(others=>'0'), -- istart, idone, pc
|
| 466 |
|
|
'0',"000","0000", -- regmod, regnum, delta
|
| 467 |
|
|
'0','0' -- isdec, trace_prev
|
| 468 |
|
|
);
|
| 469 |
|
|
|
| 470 |
|
|
type mmu_ssr0_type is record -- MMU ssr0
|
| 471 |
|
|
abo_nonres : slbit; -- abort non resident
|
| 472 |
|
|
abo_length : slbit; -- abort segment length
|
| 473 |
|
|
abo_rdonly : slbit; -- abort read-only
|
| 474 |
|
|
trap_mmu : slbit; -- trap management
|
| 475 |
|
|
ena_trap : slbit; -- enable traps
|
| 476 |
|
|
inst_compl : slbit; -- instruction complete
|
| 477 |
|
|
seg_mode : slv2; -- segement mode
|
| 478 |
|
|
dspace : slbit; -- address space (D=1, I=0)
|
| 479 |
|
|
seg_num : slv3; -- segment number
|
| 480 |
|
|
ena_mmu : slbit; -- enable memory management
|
| 481 |
|
|
trace_prev : slbit; -- ssr12 trace status in prev. state
|
| 482 |
|
|
end record mmu_ssr0_type;
|
| 483 |
|
|
|
| 484 |
|
|
constant mmu_ssr0_init : mmu_ssr0_type := (
|
| 485 |
|
|
inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
|
| 486 |
|
|
others=>'0'
|
| 487 |
|
|
);
|
| 488 |
|
|
|
| 489 |
|
|
type mmu_ssr1_type is record -- MMU ssr1
|
| 490 |
|
|
rb_delta : slv5; -- RB: amount change
|
| 491 |
|
|
rb_num : slv3; -- RB: register number
|
| 492 |
|
|
ra_delta : slv5; -- RA: amount change
|
| 493 |
|
|
ra_num : slv3; -- RA: register number
|
| 494 |
|
|
end record mmu_ssr1_type;
|
| 495 |
|
|
|
| 496 |
|
|
constant mmu_ssr1_init : mmu_ssr1_type := (
|
| 497 |
|
|
"00000","000", -- rb_...
|
| 498 |
|
|
"00000","000" -- ra_...
|
| 499 |
|
|
);
|
| 500 |
|
|
|
| 501 |
|
|
type mmu_ssr3_type is record -- MMU ssr3
|
| 502 |
|
|
ena_ubmap : slbit; -- enable unibus mapping
|
| 503 |
|
|
ena_22bit : slbit; -- enable 22 bit mapping
|
| 504 |
|
|
dspace_km : slbit; -- enable dspace kernel
|
| 505 |
|
|
dspace_sm : slbit; -- enable dspace supervisor
|
| 506 |
|
|
dspace_um : slbit; -- enable dspace user
|
| 507 |
|
|
end record mmu_ssr3_type;
|
| 508 |
|
|
|
| 509 |
|
|
constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
|
| 510 |
|
|
|
| 511 |
|
|
-- control port definitions --------------------------------------------------
|
| 512 |
|
|
|
| 513 |
|
|
type cp_cntl_type is record -- control port control
|
| 514 |
|
|
req : slbit; -- request
|
| 515 |
|
|
func : slv5; -- function
|
| 516 |
|
|
rnum : slv3; -- register number
|
| 517 |
|
|
end record cp_cntl_type;
|
| 518 |
|
|
|
| 519 |
|
|
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
|
| 520 |
|
|
constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start
|
| 521 |
|
|
constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop
|
| 522 |
|
|
constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue
|
| 523 |
|
|
constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step
|
| 524 |
|
|
constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft)
|
| 525 |
|
|
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
|
| 526 |
|
|
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
|
| 527 |
|
|
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
|
| 528 |
|
|
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
|
| 529 |
|
|
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
|
| 530 |
|
|
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
|
| 531 |
|
|
|
| 532 |
|
|
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
|
| 533 |
|
|
|
| 534 |
|
|
type cp_stat_type is record -- control port status
|
| 535 |
|
|
cmdbusy : slbit; -- command busy
|
| 536 |
|
|
cmdack : slbit; -- command acknowledge
|
| 537 |
|
|
cmderr : slbit; -- command error
|
| 538 |
|
|
cmdmerr : slbit; -- command memory access error
|
| 539 |
|
|
cpugo : slbit; -- CPU go state
|
| 540 |
|
|
cpustep : slbit; -- CPU step flag
|
| 541 |
|
|
cpuhalt : slbit; -- CPU halt flag
|
| 542 |
|
|
cpuwait : slbit; -- CPU wait flag
|
| 543 |
|
|
cpurust : slv4; -- CPU run status
|
| 544 |
|
|
end record cp_stat_type;
|
| 545 |
|
|
|
| 546 |
|
|
constant cp_stat_init : cp_stat_type := (
|
| 547 |
|
|
'0','0','0','0', -- cmd...
|
| 548 |
|
|
'0','0','0','0', -- cpu...
|
| 549 |
|
|
(others=>'0') -- cpurust
|
| 550 |
|
|
);
|
| 551 |
|
|
|
| 552 |
|
|
type cp_addr_type is record -- control port address
|
| 553 |
|
|
addr : slv22_1; -- address
|
| 554 |
|
|
racc : slbit; -- ibr access
|
| 555 |
|
|
be : slv2; -- byte enables
|
| 556 |
|
|
ena_22bit : slbit; -- enable 22 bit mode
|
| 557 |
|
|
ena_ubmap : slbit; -- enable unibus mapper
|
| 558 |
|
|
end record cp_addr_type;
|
| 559 |
|
|
|
| 560 |
|
|
constant cp_addr_init : cp_addr_type := (
|
| 561 |
|
|
(others=>'0'), -- addr
|
| 562 |
|
|
'0',"00", -- racc, be
|
| 563 |
|
|
'0','0' -- ena_...
|
| 564 |
|
|
);
|
| 565 |
|
|
|
| 566 |
|
|
-- debug and monitoring port definitions -------------------------------------
|
| 567 |
|
|
|
| 568 |
|
|
type dm_cntl_type is record -- debug and monitor control
|
| 569 |
|
|
dum1 : slbit; -- dummy 1
|
| 570 |
|
|
dum2 : slbit; -- dummy 2
|
| 571 |
|
|
end record dm_cntl_type;
|
| 572 |
|
|
|
| 573 |
|
|
constant dm_cntl_init : dm_cntl_type := (others=>'0');
|
| 574 |
|
|
|
| 575 |
|
|
type dm_stat_dp_type is record -- debug and monitor status - dpath
|
| 576 |
|
|
pc : slv16; -- pc
|
| 577 |
|
|
psw : psw_type; -- psw
|
| 578 |
|
|
ireg : slv16; -- ireg
|
| 579 |
|
|
ireg_we : slbit; -- ireg we
|
| 580 |
|
|
dsrc : slv16; -- dsrc register
|
| 581 |
|
|
ddst : slv16; -- ddst register
|
| 582 |
|
|
dtmp : slv16; -- dtmp register
|
| 583 |
|
|
dres : slv16; -- dres bus
|
| 584 |
|
|
gpr_adst : slv3; -- gpr dst regsiter
|
| 585 |
|
|
gpr_mode : slv2; -- gpr mode
|
| 586 |
|
|
gpr_bytop : slbit; -- gpr bytop
|
| 587 |
|
|
gpr_we : slbit; -- gpr we
|
| 588 |
|
|
end record dm_stat_dp_type;
|
| 589 |
|
|
|
| 590 |
|
|
constant dm_stat_dp_init : dm_stat_dp_type := (
|
| 591 |
|
|
(others=>'0'), -- pc
|
| 592 |
|
|
psw_init, -- psw
|
| 593 |
|
|
(others=>'0'),'0', -- ireg, ireg_we
|
| 594 |
|
|
(others=>'0'),(others=>'0'), -- dsrc, ddst
|
| 595 |
|
|
(others=>'0'),(others=>'0'), -- dtmp, dres
|
| 596 |
|
|
(others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
|
| 597 |
|
|
'0','0' -- gpr_bytop, gpr_we
|
| 598 |
|
|
);
|
| 599 |
|
|
|
| 600 |
|
|
type dm_stat_vm_type is record -- debug and monitor status - vmbox
|
| 601 |
|
|
ibmreq : ib_mreq_type; -- ibus master request
|
| 602 |
|
|
ibsres : ib_sres_type; -- ibus slave response
|
| 603 |
|
|
end record dm_stat_vm_type;
|
| 604 |
|
|
|
| 605 |
|
|
constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);
|
| 606 |
|
|
|
| 607 |
|
|
type dm_stat_co_type is record -- debug and monitor status - core
|
| 608 |
|
|
cpugo : slbit; -- cpugo state flag
|
| 609 |
|
|
cpuhalt : slbit; -- cpuhalt state flag
|
| 610 |
|
|
end record dm_stat_co_type;
|
| 611 |
|
|
|
| 612 |
|
|
constant dm_stat_co_init : dm_stat_co_type := ('0','0');
|
| 613 |
|
|
|
| 614 |
|
|
type dm_stat_sy_type is record -- debug and monitor status - system
|
| 615 |
|
|
emmreq : em_mreq_type; -- external memory: request
|
| 616 |
|
|
emsres : em_sres_type; -- external memory: response
|
| 617 |
|
|
chit : slbit; -- cache hit
|
| 618 |
|
|
end record dm_stat_sy_type;
|
| 619 |
|
|
|
| 620 |
|
|
constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0');
|
| 621 |
|
|
|
| 622 |
|
|
-- rbus interface definitions ------------------------------------------------
|
| 623 |
|
|
|
| 624 |
|
|
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
|
| 625 |
|
|
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
|
| 626 |
|
|
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
|
| 627 |
|
|
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
|
| 628 |
|
|
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
|
| 629 |
|
|
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
|
| 630 |
|
|
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
|
| 631 |
|
|
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
|
| 632 |
|
|
|
| 633 |
|
|
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
|
| 634 |
|
|
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
|
| 635 |
|
|
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
|
| 636 |
|
|
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
|
| 637 |
|
|
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
|
| 638 |
|
|
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
|
| 639 |
|
|
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
|
| 640 |
|
|
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
|
| 641 |
|
|
|
| 642 |
|
|
constant c_rbaddr_ibrb : slv5 := "10000"; -- R/W ibr base address
|
| 643 |
|
|
|
| 644 |
|
|
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
|
| 645 |
|
|
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
|
| 646 |
|
|
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
|
| 647 |
|
|
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
|
| 648 |
|
|
|
| 649 |
|
|
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
|
| 650 |
|
|
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
|
| 651 |
|
|
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
|
| 652 |
|
|
constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt
|
| 653 |
|
|
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
|
| 654 |
|
|
|
| 655 |
|
|
subtype c_ibrb_ibf_base is integer range 12 downto 6; -- ibrb: base addr
|
| 656 |
|
|
subtype c_ibrb_ibf_be is integer range 1 downto 0; -- ibrb: be's
|
| 657 |
|
|
|
| 658 |
|
|
-- -------------------------------------
|
| 659 |
|
|
|
| 660 |
|
|
component pdp11_gpr is -- general purpose registers
|
| 661 |
|
|
port (
|
| 662 |
|
|
CLK : in slbit; -- clock
|
| 663 |
|
|
DIN : in slv16; -- input data
|
| 664 |
|
|
ASRC : in slv3; -- source register number
|
| 665 |
|
|
ADST : in slv3; -- destination register number
|
| 666 |
|
|
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
|
| 667 |
|
|
RSET : in slbit; -- register set
|
| 668 |
|
|
WE : in slbit; -- write enable
|
| 669 |
|
|
BYTOP : in slbit; -- byte operation (write low byte only)
|
| 670 |
|
|
PCINC : in slbit; -- increment PC
|
| 671 |
|
|
DSRC : out slv16; -- source register data
|
| 672 |
|
|
DDST : out slv16; -- destination register data
|
| 673 |
|
|
PC : out slv16 -- current PC value
|
| 674 |
|
|
);
|
| 675 |
|
|
end component;
|
| 676 |
|
|
|
| 677 |
|
|
constant c_gpr_r5 : slv3 := "101"; -- register number of r5
|
| 678 |
|
|
constant c_gpr_sp : slv3 := "110"; -- register number of SP
|
| 679 |
|
|
constant c_gpr_pc : slv3 := "111"; -- register number of PC
|
| 680 |
|
|
|
| 681 |
|
|
component pdp11_psr is -- processor status word register
|
| 682 |
|
|
port (
|
| 683 |
|
|
CLK : in slbit; -- clock
|
| 684 |
|
|
CRESET : in slbit; -- console reset
|
| 685 |
|
|
DIN : in slv16; -- input data
|
| 686 |
|
|
CCIN : in slv4; -- cc input
|
| 687 |
|
|
CCWE : in slbit; -- enable update cc
|
| 688 |
|
|
WE : in slbit; -- write enable (from DIN)
|
| 689 |
|
|
FUNC : in slv3; -- write function (from DIN)
|
| 690 |
|
|
PSW : out psw_type; -- current psw
|
| 691 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 692 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 693 |
|
|
);
|
| 694 |
|
|
end component;
|
| 695 |
|
|
|
| 696 |
|
|
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
|
| 697 |
|
|
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
|
| 698 |
|
|
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
|
| 699 |
|
|
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
|
| 700 |
|
|
constant c_psr_func_wall : slv3 := "100"; -- write all fields
|
| 701 |
|
|
|
| 702 |
8 |
wfjm |
component pdp11_ounit is -- offset adder for addresses (ounit)
|
| 703 |
2 |
wfjm |
port (
|
| 704 |
|
|
DSRC : in slv16; -- 'src' data for port A
|
| 705 |
|
|
DDST : in slv16; -- 'dst' data for port A
|
| 706 |
|
|
DTMP : in slv16; -- 'tmp' data for port A
|
| 707 |
|
|
PC : in slv16; -- PC data for port A
|
| 708 |
|
|
ASEL : in slv2; -- selector for port A
|
| 709 |
|
|
AZERO : in slbit; -- force zero for port A
|
| 710 |
|
|
IREG8 : in slv8; -- 'ireg' data for port B
|
| 711 |
|
|
VMDOUT : in slv16; -- virt. memory data for port B
|
| 712 |
|
|
CONST : in slv9; -- sequencer const data for port B
|
| 713 |
|
|
BSEL : in slv2; -- selector for port B
|
| 714 |
|
|
OPSUB : in slbit; -- operation: 0 add, 1 sub
|
| 715 |
|
|
DOUT : out slv16; -- data output
|
| 716 |
|
|
NZOUT : out slv2 -- NZ condition codes out
|
| 717 |
|
|
);
|
| 718 |
|
|
end component;
|
| 719 |
|
|
|
| 720 |
8 |
wfjm |
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
|
| 721 |
|
|
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
|
| 722 |
|
|
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
|
| 723 |
|
|
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
|
| 724 |
2 |
wfjm |
|
| 725 |
8 |
wfjm |
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
|
| 726 |
|
|
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
|
| 727 |
|
|
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
|
| 728 |
|
|
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
|
| 729 |
2 |
wfjm |
|
| 730 |
8 |
wfjm |
component pdp11_aunit is -- arithmetic unit for data (aunit)
|
| 731 |
2 |
wfjm |
port (
|
| 732 |
|
|
DSRC : in slv16; -- 'src' data in
|
| 733 |
|
|
DDST : in slv16; -- 'dst' data in
|
| 734 |
|
|
CI : in slbit; -- carry flag in
|
| 735 |
|
|
SRCMOD : in slv2; -- src modifier mode
|
| 736 |
|
|
DSTMOD : in slv2; -- dst modifier mode
|
| 737 |
|
|
CIMOD : in slv2; -- ci modifier mode
|
| 738 |
|
|
CC1OP : in slbit; -- use cc modes (1 op instruction)
|
| 739 |
|
|
CCMODE : in slv3; -- cc mode
|
| 740 |
|
|
BYTOP : in slbit; -- byte operation
|
| 741 |
|
|
DOUT : out slv16; -- data output
|
| 742 |
|
|
CCOUT : out slv4 -- condition codes out
|
| 743 |
|
|
);
|
| 744 |
|
|
end component;
|
| 745 |
|
|
|
| 746 |
8 |
wfjm |
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
|
| 747 |
|
|
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
|
| 748 |
|
|
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
|
| 749 |
|
|
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
|
| 750 |
2 |
wfjm |
|
| 751 |
8 |
wfjm |
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
|
| 752 |
|
|
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
|
| 753 |
|
|
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
|
| 754 |
|
|
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
|
| 755 |
|
|
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
|
| 756 |
|
|
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
|
| 757 |
|
|
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
|
| 758 |
|
|
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
|
| 759 |
|
|
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
|
| 760 |
2 |
wfjm |
|
| 761 |
8 |
wfjm |
component pdp11_lunit is -- logic unit for data (lunit)
|
| 762 |
2 |
wfjm |
port (
|
| 763 |
|
|
DSRC : in slv16; -- 'src' data in
|
| 764 |
|
|
DDST : in slv16; -- 'dst' data in
|
| 765 |
|
|
CCIN : in slv4; -- condition codes in
|
| 766 |
|
|
FUNC : in slv4; -- function
|
| 767 |
|
|
BYTOP : in slbit; -- byte operation
|
| 768 |
|
|
DOUT : out slv16; -- data output
|
| 769 |
|
|
CCOUT : out slv4 -- condition codes out
|
| 770 |
|
|
);
|
| 771 |
|
|
end component;
|
| 772 |
|
|
|
| 773 |
8 |
wfjm |
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
|
| 774 |
|
|
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
|
| 775 |
|
|
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
|
| 776 |
|
|
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
|
| 777 |
|
|
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
|
| 778 |
|
|
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
|
| 779 |
|
|
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
|
| 780 |
|
|
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
|
| 781 |
|
|
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
|
| 782 |
|
|
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
|
| 783 |
|
|
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
|
| 784 |
2 |
wfjm |
|
| 785 |
8 |
wfjm |
component pdp11_munit is -- mul/div unit for data (munit)
|
| 786 |
2 |
wfjm |
port (
|
| 787 |
|
|
CLK : in slbit; -- clock
|
| 788 |
|
|
DSRC : in slv16; -- 'src' data in
|
| 789 |
|
|
DDST : in slv16; -- 'dst' data in
|
| 790 |
|
|
DTMP : in slv16; -- 'tmp' data in
|
| 791 |
|
|
GPR_DSRC : in slv16; -- 'src' data from GPR
|
| 792 |
|
|
FUNC : in slv2; -- function
|
| 793 |
|
|
S_DIV : in slbit; -- s_opg_div state
|
| 794 |
|
|
S_DIV_CN : in slbit; -- s_opg_div_cn state
|
| 795 |
|
|
S_DIV_CR : in slbit; -- s_opg_div_cr state
|
| 796 |
|
|
S_ASH : in slbit; -- s_opg_ash state
|
| 797 |
|
|
S_ASH_CN : in slbit; -- s_opg_ash_cn state
|
| 798 |
|
|
S_ASHC : in slbit; -- s_opg_ashc state
|
| 799 |
|
|
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
|
| 800 |
|
|
SHC_TC : out slbit; -- last shc cycle (shc==0)
|
| 801 |
|
|
DIV_CR : out slbit; -- division: reminder correction needed
|
| 802 |
|
|
DIV_CQ : out slbit; -- division: quotient correction needed
|
| 803 |
|
|
DIV_ZERO : out slbit; -- division: divident or divisor zero
|
| 804 |
|
|
DIV_OVFL : out slbit; -- division: overflow
|
| 805 |
|
|
DOUT : out slv16; -- data output
|
| 806 |
|
|
DOUTE : out slv16; -- data output extra
|
| 807 |
|
|
CCOUT : out slv4 -- condition codes out
|
| 808 |
|
|
);
|
| 809 |
|
|
end component;
|
| 810 |
|
|
|
| 811 |
8 |
wfjm |
constant c_munit_func_mul : slv2 := "00"; -- MUL
|
| 812 |
|
|
constant c_munit_func_div : slv2 := "01"; -- DIV
|
| 813 |
|
|
constant c_munit_func_ash : slv2 := "10"; -- ASH
|
| 814 |
|
|
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
|
| 815 |
2 |
wfjm |
|
| 816 |
|
|
component pdp11_mmu_sadr is -- mmu SAR/SDR register set
|
| 817 |
|
|
port (
|
| 818 |
|
|
CLK : in slbit; -- clock
|
| 819 |
|
|
MODE : in slv2; -- mode
|
| 820 |
|
|
ASN : in slv4; -- augmented segment number (1+3 bit)
|
| 821 |
|
|
AIB_WE : in slbit; -- update AIB
|
| 822 |
|
|
AIB_SETA : in slbit; -- set access AIB
|
| 823 |
|
|
AIB_SETW : in slbit; -- set write AIB
|
| 824 |
|
|
SARSDR : out sarsdr_type; -- combined SAR/SDR
|
| 825 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 826 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 827 |
|
|
);
|
| 828 |
|
|
end component;
|
| 829 |
|
|
|
| 830 |
|
|
component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
|
| 831 |
|
|
port (
|
| 832 |
|
|
CLK : in slbit; -- clock
|
| 833 |
|
|
CRESET : in slbit; -- console reset
|
| 834 |
|
|
TRACE : in slbit; -- trace enable
|
| 835 |
|
|
MONI : in mmu_moni_type; -- MMU monitor port data
|
| 836 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 837 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 838 |
|
|
);
|
| 839 |
|
|
end component;
|
| 840 |
|
|
|
| 841 |
|
|
component pdp11_mmu is -- mmu - memory management unit
|
| 842 |
|
|
port (
|
| 843 |
|
|
CLK : in slbit; -- clock
|
| 844 |
|
|
CRESET : in slbit; -- console reset
|
| 845 |
|
|
BRESET : in slbit; -- ibus reset
|
| 846 |
|
|
CNTL : in mmu_cntl_type; -- control port
|
| 847 |
|
|
VADDR : in slv16; -- virtual address
|
| 848 |
|
|
MONI : in mmu_moni_type; -- monitor port
|
| 849 |
|
|
STAT : out mmu_stat_type; -- status port
|
| 850 |
|
|
PADDRH : out slv16; -- physical address (upper 16 bit)
|
| 851 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 852 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 853 |
|
|
);
|
| 854 |
|
|
end component;
|
| 855 |
|
|
|
| 856 |
|
|
component pdp11_vmbox is -- virtual memory
|
| 857 |
|
|
port (
|
| 858 |
|
|
CLK : in slbit; -- clock
|
| 859 |
|
|
GRESET : in slbit; -- global reset
|
| 860 |
|
|
CRESET : in slbit; -- console reset
|
| 861 |
|
|
BRESET : in slbit; -- ibus reset
|
| 862 |
|
|
CP_ADDR : in cp_addr_type; -- console port address
|
| 863 |
|
|
VM_CNTL : in vm_cntl_type; -- vm control port
|
| 864 |
|
|
VM_ADDR : in slv16; -- vm address
|
| 865 |
|
|
VM_DIN : in slv16; -- vm data in
|
| 866 |
|
|
VM_STAT : out vm_stat_type; -- vm status port
|
| 867 |
|
|
VM_DOUT : out slv16; -- vm data out
|
| 868 |
|
|
EM_MREQ : out em_mreq_type; -- external memory: request
|
| 869 |
|
|
EM_SRES : in em_sres_type; -- external memory: response
|
| 870 |
|
|
MMU_MONI : in mmu_moni_type; -- mmu monitor port
|
| 871 |
|
|
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
|
| 872 |
|
|
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
|
| 873 |
|
|
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
|
| 874 |
|
|
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
|
| 875 |
|
|
);
|
| 876 |
|
|
end component;
|
| 877 |
|
|
|
| 878 |
|
|
component pdp11_dpath is -- CPU datapath
|
| 879 |
|
|
port (
|
| 880 |
|
|
CLK : in slbit; -- clock
|
| 881 |
|
|
CRESET : in slbit; -- console reset
|
| 882 |
|
|
CNTL : in dpath_cntl_type; -- control interface
|
| 883 |
|
|
STAT : out dpath_stat_type; -- status interface
|
| 884 |
|
|
CP_DIN : in slv16; -- console port data in
|
| 885 |
|
|
CP_DOUT : out slv16; -- console port data out
|
| 886 |
|
|
PSWOUT : out psw_type; -- current psw
|
| 887 |
|
|
PCOUT : out slv16; -- current pc
|
| 888 |
|
|
IREG : out slv16; -- ireg out
|
| 889 |
|
|
VM_ADDR : out slv16; -- virt. memory address
|
| 890 |
|
|
VM_DOUT : in slv16; -- virt. memory data out
|
| 891 |
|
|
VM_DIN : out slv16; -- virt. memory data in
|
| 892 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 893 |
|
|
IB_SRES : out ib_sres_type; -- ibus response
|
| 894 |
|
|
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
|
| 895 |
|
|
);
|
| 896 |
|
|
end component;
|
| 897 |
|
|
|
| 898 |
|
|
component pdp11_decode is -- instruction decoder
|
| 899 |
|
|
port (
|
| 900 |
|
|
IREG : in slv16; -- input instruction word
|
| 901 |
|
|
STAT : out decode_stat_type -- status output
|
| 902 |
|
|
);
|
| 903 |
|
|
end component;
|
| 904 |
|
|
|
| 905 |
|
|
component pdp11_sequencer is -- cpu sequencer
|
| 906 |
|
|
port (
|
| 907 |
|
|
CLK : in slbit; -- clock
|
| 908 |
|
|
GRESET : in slbit; -- global reset
|
| 909 |
|
|
PSW : in psw_type; -- processor status
|
| 910 |
|
|
PC : in slv16; -- program counter
|
| 911 |
|
|
IREG : in slv16; -- IREG
|
| 912 |
|
|
ID_STAT : in decode_stat_type; -- instr. decoder status
|
| 913 |
|
|
DP_STAT : in dpath_stat_type; -- data path status
|
| 914 |
|
|
CP_CNTL : in cp_cntl_type; -- console port control
|
| 915 |
|
|
VM_STAT : in vm_stat_type; -- virtual memory status port
|
| 916 |
|
|
INT_PRI : in slv3; -- interrupt priority
|
| 917 |
|
|
INT_VECT : in slv9_2; -- interrupt vector
|
| 918 |
|
|
CRESET : out slbit; -- console reset
|
| 919 |
|
|
BRESET : out slbit; -- ibus reset
|
| 920 |
|
|
MMU_MONI : out mmu_moni_type; -- mmu monitor port
|
| 921 |
|
|
DP_CNTL : out dpath_cntl_type; -- data path control
|
| 922 |
|
|
VM_CNTL : out vm_cntl_type; -- virtual memory control port
|
| 923 |
|
|
CP_STAT : out cp_stat_type; -- console port status
|
| 924 |
|
|
INT_ACK : out slbit; -- interrupt acknowledge
|
| 925 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 926 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 927 |
|
|
);
|
| 928 |
|
|
end component;
|
| 929 |
|
|
|
| 930 |
|
|
component pdp11_irq is -- interrupt requester
|
| 931 |
|
|
port (
|
| 932 |
|
|
CLK : in slbit; -- clock
|
| 933 |
|
|
BRESET : in slbit; -- ibus reset
|
| 934 |
|
|
INT_ACK : in slbit; -- interrupt acknowledge from CPU
|
| 935 |
|
|
EI_PRI : in slv3; -- external interrupt priority
|
| 936 |
|
|
EI_VECT : in slv9_2; -- external interrupt vector
|
| 937 |
|
|
EI_ACKM : out slbit; -- external interrupt acknowledge
|
| 938 |
|
|
PRI : out slv3; -- interrupt priority
|
| 939 |
|
|
VECT : out slv9_2; -- interrupt vector
|
| 940 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 941 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 942 |
|
|
);
|
| 943 |
|
|
end component;
|
| 944 |
|
|
|
| 945 |
|
|
component pdp11_ubmap is -- 11/70 unibus mapper
|
| 946 |
|
|
port (
|
| 947 |
|
|
CLK : in slbit; -- clock
|
| 948 |
|
|
MREQ : in slbit; -- request mapping
|
| 949 |
|
|
ADDR_UB : in slv18_1; -- UNIBUS address (in)
|
| 950 |
|
|
ADDR_PM : out slv22_1; -- physical memory address (out)
|
| 951 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 952 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 953 |
|
|
);
|
| 954 |
|
|
end component;
|
| 955 |
|
|
|
| 956 |
|
|
component pdp11_sys70 is -- 11/70 memory system registers
|
| 957 |
|
|
port (
|
| 958 |
|
|
CLK : in slbit; -- clock
|
| 959 |
|
|
CRESET : in slbit; -- console reset
|
| 960 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 961 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 962 |
|
|
);
|
| 963 |
|
|
end component;
|
| 964 |
|
|
|
| 965 |
|
|
component pdp11_mem70 is -- 11/70 memory system registers
|
| 966 |
|
|
port (
|
| 967 |
|
|
CLK : in slbit; -- clock
|
| 968 |
|
|
CRESET : in slbit; -- console reset
|
| 969 |
|
|
HM_ENA : in slbit; -- hit/miss enable
|
| 970 |
|
|
HM_VAL : in slbit; -- hit/miss value
|
| 971 |
|
|
CACHE_FMISS : out slbit; -- cache force miss
|
| 972 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
| 973 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
| 974 |
|
|
);
|
| 975 |
|
|
end component;
|
| 976 |
|
|
|
| 977 |
|
|
component pdp11_cache is -- cache
|
| 978 |
|
|
port (
|
| 979 |
|
|
CLK : in slbit; -- clock
|
| 980 |
|
|
GRESET : in slbit; -- global reset
|
| 981 |
|
|
EM_MREQ : in em_mreq_type; -- em request
|
| 982 |
|
|
EM_SRES : out em_sres_type; -- em response
|
| 983 |
|
|
FMISS : in slbit; -- force miss
|
| 984 |
|
|
CHIT : out slbit; -- cache hit flag
|
| 985 |
|
|
MEM_REQ : out slbit; -- memory: request
|
| 986 |
|
|
MEM_WE : out slbit; -- memory: write enable
|
| 987 |
|
|
MEM_BUSY : in slbit; -- memory: controller busy
|
| 988 |
|
|
MEM_ACK_R : in slbit; -- memory: acknowledge read
|
| 989 |
|
|
MEM_ADDR : out slv20; -- memory: address
|
| 990 |
|
|
MEM_BE : out slv4; -- memory: byte enable
|
| 991 |
|
|
MEM_DI : out slv32; -- memory: data in (memory view)
|
| 992 |
|
|
MEM_DO : in slv32 -- memory: data out (memory view)
|
| 993 |
|
|
);
|
| 994 |
|
|
end component;
|
| 995 |
|
|
|
| 996 |
|
|
component pdp11_core is -- full processor core
|
| 997 |
|
|
port (
|
| 998 |
|
|
CLK : in slbit; -- clock
|
| 999 |
|
|
RESET : in slbit; -- reset
|
| 1000 |
|
|
CP_CNTL : in cp_cntl_type; -- console control port
|
| 1001 |
|
|
CP_ADDR : in cp_addr_type; -- console address port
|
| 1002 |
|
|
CP_DIN : in slv16; -- console data in
|
| 1003 |
|
|
CP_STAT : out cp_stat_type; -- console status port
|
| 1004 |
|
|
CP_DOUT : out slv16; -- console data out
|
| 1005 |
|
|
EI_PRI : in slv3; -- external interrupt priority
|
| 1006 |
|
|
EI_VECT : in slv9_2; -- external interrupt vector
|
| 1007 |
|
|
EI_ACKM : out slbit; -- external interrupt acknowledge
|
| 1008 |
|
|
EM_MREQ : out em_mreq_type; -- external memory: request
|
| 1009 |
|
|
EM_SRES : in em_sres_type; -- external memory: response
|
| 1010 |
|
|
BRESET : out slbit; -- ibus reset
|
| 1011 |
|
|
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
|
| 1012 |
|
|
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
|
| 1013 |
|
|
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
|
| 1014 |
|
|
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
|
| 1015 |
|
|
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
|
| 1016 |
|
|
);
|
| 1017 |
|
|
end component;
|
| 1018 |
|
|
|
| 1019 |
|
|
component pdp11_tmu is -- trace and monitor unit
|
| 1020 |
|
|
port (
|
| 1021 |
|
|
CLK : in slbit; -- clock
|
| 1022 |
|
|
ENA : in slbit := '0'; -- enable trace output
|
| 1023 |
|
|
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
|
| 1024 |
|
|
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
|
| 1025 |
|
|
DM_STAT_CO : in dm_stat_co_type; -- DM core
|
| 1026 |
|
|
DM_STAT_SY : in dm_stat_sy_type -- DM system
|
| 1027 |
|
|
);
|
| 1028 |
|
|
end component;
|
| 1029 |
|
|
|
| 1030 |
|
|
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
|
| 1031 |
|
|
generic (
|
| 1032 |
|
|
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
|
| 1033 |
|
|
port (
|
| 1034 |
|
|
CLK : in slbit; -- clock
|
| 1035 |
|
|
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
|
| 1036 |
|
|
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
|
| 1037 |
|
|
DM_STAT_CO : in dm_stat_co_type; -- DM core
|
| 1038 |
|
|
DM_STAT_SY : in dm_stat_sy_type -- DM system
|
| 1039 |
|
|
);
|
| 1040 |
|
|
end component;
|
| 1041 |
|
|
|
| 1042 |
|
|
component pdp11_du_drv is -- display unit low level driver
|
| 1043 |
|
|
generic (
|
| 1044 |
|
|
CDWIDTH : positive := 3); -- clock divider width
|
| 1045 |
|
|
port (
|
| 1046 |
|
|
CLK : in slbit; -- clock
|
| 1047 |
|
|
GRESET : in slbit; -- global reset
|
| 1048 |
|
|
ROW0 : in slv22; -- led row 0 (22 leds, top)
|
| 1049 |
|
|
ROW1 : in slv16; -- led row 1 (16 leds)
|
| 1050 |
|
|
ROW2 : in slv16; -- led row 2 (16 leds)
|
| 1051 |
|
|
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
|
| 1052 |
|
|
SWOPT : out slv8; -- option pattern from du
|
| 1053 |
|
|
SWOPT_RDY : out slbit; -- marks update of swopt
|
| 1054 |
8 |
wfjm |
DU_SCLK : out slbit; -- DU: sclk
|
| 1055 |
|
|
DU_SS_N : out slbit; -- DU: ss_n
|
| 1056 |
2 |
wfjm |
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
|
| 1057 |
|
|
DU_MISO : in slbit -- DU: miso (master in, slave out)
|
| 1058 |
|
|
);
|
| 1059 |
|
|
end component;
|
| 1060 |
|
|
|
| 1061 |
|
|
component pdp11_bram is -- BRAM based ext. memory dummy
|
| 1062 |
|
|
generic (
|
| 1063 |
|
|
AWIDTH : positive := 14); -- address width
|
| 1064 |
|
|
port (
|
| 1065 |
|
|
CLK : in slbit; -- clock
|
| 1066 |
|
|
GRESET : in slbit; -- global reset
|
| 1067 |
|
|
EM_MREQ : in em_mreq_type; -- em request
|
| 1068 |
|
|
EM_SRES : out em_sres_type -- em response
|
| 1069 |
|
|
);
|
| 1070 |
|
|
end component;
|
| 1071 |
|
|
|
| 1072 |
9 |
wfjm |
component pdp11_core_rbus is -- core to rbus interface
|
| 1073 |
2 |
wfjm |
generic (
|
| 1074 |
13 |
wfjm |
RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
|
| 1075 |
|
|
RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
|
| 1076 |
2 |
wfjm |
port (
|
| 1077 |
|
|
CLK : in slbit; -- clock
|
| 1078 |
|
|
RESET : in slbit; -- reset
|
| 1079 |
|
|
RB_MREQ : in rb_mreq_type; -- rbus: request
|
| 1080 |
|
|
RB_SRES : out rb_sres_type; -- rbus: response
|
| 1081 |
|
|
RB_STAT : out slv3; -- rbus: status flags
|
| 1082 |
8 |
wfjm |
RB_LAM : out slbit; -- remote attention
|
| 1083 |
2 |
wfjm |
CPU_RESET : out slbit; -- cpu master reset
|
| 1084 |
|
|
CP_CNTL : out cp_cntl_type; -- console control port
|
| 1085 |
|
|
CP_ADDR : out cp_addr_type; -- console address port
|
| 1086 |
|
|
CP_DIN : out slv16; -- console data in
|
| 1087 |
|
|
CP_STAT : in cp_stat_type; -- console status port
|
| 1088 |
|
|
CP_DOUT : in slv16 -- console data out
|
| 1089 |
|
|
);
|
| 1090 |
|
|
end component;
|
| 1091 |
|
|
|
| 1092 |
|
|
-- ----- move later to pdp11_conf --------------------------------------------
|
| 1093 |
|
|
|
| 1094 |
|
|
constant conf_vect_pirq : integer := 8#240#;
|
| 1095 |
|
|
constant conf_pri_pirq_1 : integer := 1;
|
| 1096 |
|
|
constant conf_pri_pirq_2 : integer := 2;
|
| 1097 |
|
|
constant conf_pri_pirq_3 : integer := 3;
|
| 1098 |
|
|
constant conf_pri_pirq_4 : integer := 4;
|
| 1099 |
|
|
constant conf_pri_pirq_5 : integer := 5;
|
| 1100 |
|
|
constant conf_pri_pirq_6 : integer := 6;
|
| 1101 |
|
|
constant conf_pri_pirq_7 : integer := 7;
|
| 1102 |
|
|
|
| 1103 |
|
|
end package pdp11;
|
