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-- $Id: pdp11_mmu_ssr12.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2006-2009 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_mmu_ssr12 - syn
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-- Description: pdp11: mmu register ssr1 and ssr2
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
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-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
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-- 2008-03-02 121 1.1.2 remove snoopers
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-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
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port (
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CLK : in slbit; -- clock
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CRESET : in slbit; -- console reset
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TRACE : in slbit; -- trace enable
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MONI : in mmu_moni_type; -- MMU monitor port data
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type -- ibus response
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);
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end pdp11_mmu_ssr12;
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architecture syn of pdp11_mmu_ssr12 is
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constant ibaddr_ssr1 : slv16 := conv_std_logic_vector(8#177574#,16);
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constant ibaddr_ssr2 : slv16 := conv_std_logic_vector(8#177576#,16);
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subtype ssr1_ibf_rb_delta is integer range 15 downto 11;
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subtype ssr1_ibf_rb_num is integer range 10 downto 8;
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subtype ssr1_ibf_ra_delta is integer range 7 downto 3;
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subtype ssr1_ibf_ra_num is integer range 2 downto 0;
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signal IBSEL_SSR1 : slbit := '0';
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signal IBSEL_SSR2 : slbit := '0';
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signal R_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
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signal R_SSR2 : slv16 := (others=>'0');
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signal NEXT_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
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signal NEXT_SSR2 : slv16 := (others=>'0');
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begin
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proc_ibsel: process (IB_MREQ)
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variable issr1 : slbit := '0';
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variable issr2 : slbit := '0';
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begin
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issr1 := '0';
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issr2 := '0';
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if IB_MREQ.req = '1' then
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if IB_MREQ.addr = ibaddr_ssr1(12 downto 1) then issr1 := '1'; end if;
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if IB_MREQ.addr = ibaddr_ssr2(12 downto 1) then issr2 := '1'; end if;
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end if;
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IBSEL_SSR1 <= issr1;
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IBSEL_SSR2 <= issr2;
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IB_SRES.ack <= issr1 or issr2;
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IB_SRES.busy <= '0';
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end process proc_ibsel;
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proc_ubdout : process (IBSEL_SSR1, IBSEL_SSR2, R_SSR1, R_SSR2)
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variable ssr1out : slv16 := (others=>'0');
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variable ssr2out : slv16 := (others=>'0');
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begin
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ssr1out := (others=>'0');
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if IBSEL_SSR1 = '1' then
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ssr1out(ssr1_ibf_rb_delta) := R_SSR1.rb_delta;
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ssr1out(ssr1_ibf_rb_num) := R_SSR1.rb_num;
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ssr1out(ssr1_ibf_ra_delta) := R_SSR1.ra_delta;
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ssr1out(ssr1_ibf_ra_num) := R_SSR1.ra_num;
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end if;
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ssr2out := (others=>'0');
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if IBSEL_SSR2 = '1' then
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ssr2out := R_SSR2;
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end if;
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IB_SRES.dout <= ssr1out or ssr2out;
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end process proc_ubdout;
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proc_regs : process (CLK)
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begin
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if CLK'event and CLK='1' then
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R_SSR1 <= NEXT_SSR1;
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R_SSR2 <= NEXT_SSR2;
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end if;
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end process proc_regs;
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proc_comb : process (CRESET, IBSEL_SSR1, IB_MREQ,
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R_SSR1, R_SSR2, TRACE, MONI)
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variable nssr1 : mmu_ssr1_type := mmu_ssr1_init;
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variable nssr2 : slv16 := (others=>'0');
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variable delta : slv5 := (others=>'0');
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variable use_rb : slbit := '0';
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begin
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nssr1 := R_SSR1;
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nssr2 := R_SSR2;
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delta := "0" & MONI.delta;
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use_rb := '0';
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if MONI.regnum/=nssr1.ra_num and unsigned(nssr1.ra_delta)/=0 then
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use_rb := '1';
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end if;
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if CRESET = '1' then
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nssr1 := mmu_ssr1_init;
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nssr2 := (others=>'0');
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elsif IBSEL_SSR1='1' and IB_MREQ.we='1' then
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if IB_MREQ.be1 = '1' then
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nssr1.rb_delta := IB_MREQ.din(ssr1_ibf_rb_delta);
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nssr1.rb_num := IB_MREQ.din(ssr1_ibf_rb_num);
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end if;
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if IB_MREQ.be0 = '1' then
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nssr1.ra_delta := IB_MREQ.din(ssr1_ibf_ra_delta);
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nssr1.ra_num := IB_MREQ.din(ssr1_ibf_ra_num);
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end if;
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elsif TRACE = '1' then
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if MONI.istart = '1' then
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nssr1 := mmu_ssr1_init;
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nssr2 := MONI.pc;
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elsif MONI.regmod = '1' then
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if use_rb = '0' then
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nssr1.ra_num := MONI.regnum;
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if MONI.isdec = '0' then
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nssr1.ra_delta := signed(nssr1.ra_delta) + signed(delta);
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else
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nssr1.ra_delta := signed(nssr1.ra_delta) - signed(delta);
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end if;
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else
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nssr1.rb_num := MONI.regnum;
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if MONI.isdec = '0' then
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nssr1.rb_delta := signed(nssr1.rb_delta) + signed(delta);
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else
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nssr1.rb_delta := signed(nssr1.rb_delta) - signed(delta);
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end if;
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end if;
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end if;
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end if;
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NEXT_SSR1 <= nssr1;
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NEXT_SSR2 <= nssr2;
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end process proc_comb;
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end syn;
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