OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.6/] [tools/] [tbench/] [test_w11a_dsta_flow.tcl] - Blame information for rev 24

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 22 wfjm 
# $Id: test_w11a_dsta_flow.tcl 552 2014-03-02 23:02:00Z mueller $
2 19 wfjm 
#
3 22 wfjm 
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 19 wfjm 
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
5 
#
6 
# Revision History:
7 
# Date         Rev Version  Comment
8 22 wfjm 
# 2014-03-01   552   1.0.1  use stack:; check sp;
9 19 wfjm 
# 2013-03-31   502   1.0    Initial version
10 
#
11 
# Test dsta flow with jsr pc,... instructions
12 
#
13 
 
14 22 wfjm 
# ----------------------------------------------------------------------------
15 19 wfjm 
rlc log "test_w11a_dsta_flow: test dsta flow with jsr pc,..."
16 
rlc log "  (r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=1,2,3,4,5)"
17 22 wfjm 
 
18 
# code register pre/post conditions beyond defaults
19 
#   r0   #sub00   -> ..same
20 
#   r1   #sub10   -> #sub10+2
21 
#   r2   #psub2   -> #psub2+4
22 
#   r3   #sub30+2 -> #sub30
23 
#   r4   #psub4e  -> #psub4
24 
#   r5   #data    -> #data+7*2*2
25 19 wfjm 
$cpu ldasm -lst lst -sym sym {
26 
        . = 1000
27 22 wfjm 
stack:
28 19 wfjm 
start:  jsr     pc,(r0)
29 
100$:   jsr     pc,(r1)+
30 
110$:   jsr     pc,@(r2)+
31 
120$:   jsr     pc,@(r2)+
32 
121$:   jsr     pc,-(r3)
33 
130$:   jsr     pc,@-(r4)
34 
140$:   jsr     pc,@-(r4)
35 
141$:   halt
36 
stop:
37 22 wfjm 
;
38 19 wfjm 
psub2:  .word   sub20, sub21
39 
psub4:  .word   sub41, sub40
40 
psub4e:
41 
sub00:  mov     #100,(r5)+
42 
        mov     (sp),(r5)+
43 
        rts     pc
44 
sub10:  mov     #110,(r5)+
45 
        mov     (sp),(r5)+
46 
        rts     pc
47 
sub20:  mov     #120,(r5)+
48 
        mov     (sp),(r5)+
49 
        rts     pc
50 
sub21:  mov     #121,(r5)+
51 
        mov     (sp),(r5)+
52 
        rts     pc
53 
sub30:  mov     #130,(r5)+
54 
        mov     (sp),(r5)+
55 
        rts     pc
56 
sub40:  mov     #140,(r5)+
57 
        mov     (sp),(r5)+
58 
        rts     pc
59 
sub41:  mov     #141,(r5)+
60 
        mov     (sp),(r5)+
61 
        rts     pc
62 
data:   .blkw   2*7.
63 
        .word   177777
64 
}
65 
 
66 20 wfjm 
rw11::asmrun  $cpu sym [list r0 $sym(sub00) \
67 
                             r1 $sym(sub10) \
68 
                             r2 $sym(psub2) \
69 
                             r3 [expr {$sym(sub30)+2}] \
70 
                             r4 $sym(psub4e) \
71 
                             r5 $sym(data) ]
72 
rw11::asmwait $cpu sym 1.0
73 
rw11::asmtreg $cpu [list r0 $sym(sub00) \
74 22 wfjm 
                         r1 [expr {$sym(sub10)+2}] \
75 
                         r2 [expr {$sym(psub2)+4}]  \
76 
                         r3 $sym(sub30) \
77 
                         r4 $sym(psub4) \
78 
                         r5 [expr {$sym(data) + 7*2*2}] \
79 
                         sp $sym(stack) ]
80 20 wfjm 
rw11::asmtmem $cpu $sym(data) [list \
81 19 wfjm 
                                  0100 $sym(start:100$) \
82 
                                  0110 $sym(start:110$) \
83 
                                  0120 $sym(start:120$) \
84 
                                  0121 $sym(start:121$) \
85 
                                  0130 $sym(start:130$) \
86 
                                  0140 $sym(start:140$) \
87 
                                  0141 $sym(start:141$) \
88 
                                  0177777 ]
89 
 
90 22 wfjm 
# ----------------------------------------------------------------------------
91 19 wfjm 
rlc log "  nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
92 22 wfjm 
 
93 
# code register pre/post conditions beyond defaults
94 
#   r0   #sub00-020  -> ..same
95 
#   r1   #psub10-040 -> ..same
96 
#   r5   #data       -> #data+5*2*2
97 19 wfjm 
$cpu ldasm -lst lst -sym sym {
98 
        . = 1000
99 22 wfjm 
stack:
100 19 wfjm 
start:  jsr     pc,20(r0)
101 
1100$:  jsr     pc,@40(r1)
102 
1110$:  jsr     pc,sub20
103 
1120$:  jsr     pc,@psub30
104 
1130$:  jsr     pc,@#sub40
105 
1140$:  halt
106 
stop:
107 22 wfjm 
;
108 19 wfjm 
psub10: .word   sub10
109 
psub30: .word   sub30
110 
sub00:  mov     #1100,(r5)+
111 
        mov     (sp),(r5)+
112 
        rts     pc
113 
sub10:  mov     #1110,(r5)+
114 
        mov     (sp),(r5)+
115 
        rts     pc
116 
sub20:  mov     #1120,(r5)+
117 
        mov     (sp),(r5)+
118 
        rts     pc
119 
sub30:  mov     #1130,(r5)+
120 
        mov     (sp),(r5)+
121 
        rts     pc
122 
sub40:  mov     #1140,(r5)+
123 
        mov     (sp),(r5)+
124 
        rts     pc
125 
data:   .blkw   2*5.
126 
        .word   177777
127 
}
128 
 
129 20 wfjm 
rw11::asmrun  $cpu sym [list r0 [expr {$sym(sub00)-020}] \
130 22 wfjm 
                             r1 [expr {$sym(psub10)-040}] \
131 
                             r5 $sym(data) ]
132 20 wfjm 
rw11::asmwait $cpu sym 1.0
133 
rw11::asmtreg $cpu [list r0 [expr {$sym(sub00)-020}] \
134 
                         r1 [expr {$sym(psub10)-040}] \
135 
                         r2 0 \
136 
                         r3 0 \
137 
                         r4 0 \
138 22 wfjm 
                         r5 [expr {$sym(data) + 5*2*2}] \
139 
                         sp $sym(stack) ]
140 20 wfjm 
rw11::asmtmem $cpu $sym(data) [list \
141 19 wfjm 
                                  01100 $sym(start:1100$) \
142 
                                  01110 $sym(start:1110$) \
143 
                                  01120 $sym(start:1120$) \
144 
                                  01130 $sym(start:1130$) \
145 
                                  01140 $sym(start:1140$) \
146 
                                  0177777 ]

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.