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# $Id: README.txt 428 2011-11-20 12:19:31Z mueller $
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Release notes for w11a
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Table of content:
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1. Documentation
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2. Files
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3. Change Log
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1. Documentation -------------------------------------------------------------
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More detailed information on installation, build and test can be found
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in the doc directory, specifically
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* README.txt: release notes
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* INSTALL.txt: installation and building test benches and systems
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* w11a_tb_guide.txt: running test benches
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* w11a_os_guide.txt: booting operating systems
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* w11a_known_issues.txt: known differences, limitations and issues
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2. Files ---------------------------------------------------------------------
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doc Documentation
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rtl VHDL sources
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rtl/bplib - board and component support libs
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rtl/bplib/issi - for ISSI parts
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rtl/bplib/micron - for Micron parts
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rtl/bplib/nexys2 - for Digilent Nexsy2 board
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rtl/bplib/s3board - for Digilent S3BOARD
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rtl/ibus - ibus devices (UNIBUS peripherals)
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rtl/sys_gen - top level designs
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rtl/sys_gen/tst_rlink - top level designs for an rlink tester
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rtl/sys_gen/tst_rlink/nexys2 - rlink tester system for Digilent Nexsy2
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rtl/sys_gen/w11a - top level designs for w11a SoC
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rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2
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rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD
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rtl/vlib - VHDL component libs
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rtl/vlib/comlib - communication
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rtl/vlib/genlib - general
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rtl/vlib/memlib - memory
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rtl/vlib/rbus - rri: rbus
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rtl/vlib/rlink - rri: rlink
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rtl/vlib/serport - serial port (UART)
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rtl/vlib/simlib - simulation helper lib
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rtl/vlib/xlib - Xilinx specific components
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rtl/w11a - w11a core
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tools helper programs
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tools/bin - scripts and binaries
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tools/dox - Doxygen documentation configuration
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tools/make - make includes
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tools/src - C++ sources
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tools/src/librlink - basic rlink interface
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tools/src/librlinktpp - C++ to tcl binding for rlink interface
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tools/src/librtools - general support classes and methods
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tools/src/librtcltools - support classes to implement Tcl bindings
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tools/src/librutiltpp - Tcl support commands implemented in C++
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tools/tcl - Tcl scripts
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3. Change Log ----------------------------------------------------------------
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- trunk (2011-11-20: svn rev 13(oc) 428(wfjm); untagged w11a_V0.532) +++++++++
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- Summary
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- generalized the 'human I/O' interface for s3board,nexys2/3 and atlys
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- added test design for the 'human I/O' interface
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- no functional change of w11a CPU core or any existing test systems
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- New features
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- new modules
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- rtl/sys_gen/tst_snhumanio
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- sub-tree with test design for 'human I/O' interface modules
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- atlys, nexys2, and s3board directories contain the systems
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for the respectice Digilent boards
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- Changes
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- functional changes
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- use now 'a6' polynomial of Koopman et al for crc8 in rlink
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- with one exception all vhdl sources use now numeric_std
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- module renames:
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vlib/xlib/dcm_sp_sfs_gsim -> vlib/xlib/dcm_sfs_gsim
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vlib/xlib/dcm_sp_sfs_unisim -> vlib/xlib/dcm_sfs_unisim_s3e
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vlib/xlib/tb/tb_dcm_sp_sfs -> vlib/xlib/tb/tb_dcm_sfs
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- trunk (2011-09-11: svn rev 12(oc) 409(wfjm); untagged w11a_V0.531) +++++++++
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- Summary
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- Many small changes to prepare upcoming support for
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- Spartan-6 boards (nexys3 and atlys)
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- usage of Cypress FX2 USB interface on nexys2/3 and atlys boards
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- no functional change of w11a CPU core or any test systems
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- Changes
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- use boost libraries instead of custom coding:
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- boost/function and /bind for callbacks, retire RmethDscBase and RmethDsc
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- boost/foreach for some iterator loops
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Note: boost 1.35 and gcc 4.3 or newer is required, see INSTALL.txt
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- module renames:
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bplib/s3board/s3_rs232_iob_int -> bplib/bpgen/bp_rs232_2line_iob
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bplib/s3board/s3_rs232_iob_ext -> bplib/bpgen/bp_rs232_4line_iob
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bplib/s3board/s3_dispdrv -> bplib/bpgen/sn_4x7segctl
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bplib/s3board/s3_humanio -> bplib/bpgen/sn_humanio
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bplib/s3board/s3_humanio_rbus -> bplib/bpgen/sn_humanio_rbus
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- other renames:
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tools/bin/impact_wrapper -> tools/bin/config_wrapper
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- reorganize Makefile includes and xflow option files
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rtl/vlib/Makefile.ghdl -> rtl/make/generic_ghdl.mk
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rtl/vlib/Makefile.isim -> rtl/make/generic_isim.mk
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rtl/vlib/Makefile.xflow -> rtl/make/generic_xflow.mk
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rtl/vlib/xst_vhdl.opt -> rtl/make/syn_s3_speed.opt
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rtl/vlib/balanced.opt -> rtl/make/imp_s3_speed.opt
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- trunk (2011-04-17: svn rev 11(oc) 376(wfjm); untagged w11a_V0.53) ++++++++++
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- Summary
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- Introduce C++ and Tcl based backend server. A set of C++ classes provide
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the basic rlink communication promitives. Additional glue classes provide
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a Tcl binding. This first phase contains the basic functionality needed
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to control simple test benches.
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- add an 'rlink exerciser' (tst_rlink) and a top level design for a Nexys2
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board (sys_tst_rlink_n2) and a test suite implemented in Tcl.
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- Note: No functional changes in w11a core and I/O system at this point!
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The w11a demonstrator systems are still operated with the old
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backend code (pi_rri).
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- New features
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- new directory trees for
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- C++ sources of backend (plus make and doxygen documentation support)
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- tools/dox - Doxygen documentation configuration
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- tools/make - make includes
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- tools/src/librlink - basic rlink interface
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- tools/src/librlinktpp - C++ to tcl binding for rlink interface
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- tools/src/librtools - general support classes and methods
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- tools/src/librtcltools - support classes to implement Tcl bindings
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- tools/src/librutiltpp - Tcl support commands implemented in C++
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- VHDL sources of an 'rlink exerciser'
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- rtl/sys_gen/tst_rlink - top level designs for an rlink tester
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- rtl/sys_gen/tst_rlink/nexys2 - rlink tester system for Nexsy2 board
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- Tcl sources of 'rlink exerciser'
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- tools/tcl/rlink - defs and proc's for basic rlink functions
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- tools/tcl/rutil - general support procs
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- tools/tcl/rbtest - defs and proc's for rbd_tester
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- tools/tcl/rbbram - defs and proc's for rbd_bram
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- tools/tcl/rbmoni - defs and proc's for rbd_rbmon
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- tools/tcl/rbs3hio - defs and proc's for s3_humanio_rbus
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- tools/tcl/tst_rlink - defs and proc's for tst_rlink
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- new modules
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- rtl/vlib/rbus
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- rbd_bram - rbus bram test target
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- rbd_eyemon - eye monitor for serport's
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- rbd_rbmon - rbus monitor
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- rbd_tester - rbus tester
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- rbd_timer - usec precision timer
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- rtl/vlib/memlib
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- additional wrappers for distributed and block memories added
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- tools/bin
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- ti_rri: Tcl driver for rlink tests and servers (will replace pi_rri)
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- trunk (2011-01-02: svn rev 9(oc) 352(wfjm); untagged w11a_V0.52) +++++++++++
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- Summary
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- Introduce rbus protocol V3
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- reorganize rbus and rlink modules, many renames
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- Changes
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- module renames:
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- the rri (remote-register-interface) components were re-organized and
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cleanly separated into rbus and rlink components:
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rri/rb_sres_or_* -> rbus/rb_sres_or_*
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rri/rri_core -> rlink/rlink_core
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rri/rri_base_serport -> rlink/rlink_base_serport
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rri/rrilib -> rbus/rblib
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-> rlink/rlinklib
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rri/rri_serport -> rlink/rlink_serport
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rri/tb/rritb_sres_or_mon -> rbus/rb_sres_or_mon
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- the rri test bench monitors were reorganized and renamed
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rri/tb/rritb_cpmon -> rlink/rlink_mon
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rri/tb/rritb_cpmon_sb -> rlink/rlink_mon_sb
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rri/tb/rritb_rbmon -> rbus/rb_mon
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rri/tb/rritb_rbmon_sb -> rbus/rb_mon_sb
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- the rri low level test bench were also renamed
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rri/tb/tb_rri -> rlink/tb/tb_rlink
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rri/tb/tb_rri_core -> rlink/tb/tb_rlink_direct
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rri/tb/tb_rri_serport -> rlink/tb/tb_rlink_serport
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- the base modules for rlink+cext based test benches were renamed
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rri/tb/rritb_core_cm -> rlink/tb/tbcore_rlink_dcm
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rri/tb/rritb_core -> rlink/tb/tbcore_rlink
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rri/tb/vhpi_rriext -> rlink/tb/rlink_cext_vhpi
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rri/tb/cext_rriext.c -> rlink/tb/rlink_cext.c
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- other rri/rbus related renames
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bplib/s3board/s3_humanio_rri -> s3_humanio_rbus
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w11a/pdp11_core_rri -> pdp11_core_rbus
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- other renames
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w11a/tb/tb_pdp11_core -> tb_pdp11core
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- signal renames:
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- rlink interface (defined in rlink/rlinklib.vhd):
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- rename rlink port signals:
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CP_* -> RL_*
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- rename status bit names to better reflect their usage in v3:
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ccrc -> cerr - indicates cmd crc error or other cmd level abort
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dcrc -> derr - indicates data crc error or other data level abort
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ioto -> rbnak - indicates rbus abort, either no ack or timeout
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ioerr -> rberr - indicates that rbus err flag was set
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- migrate to rbus protocol verion 3
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- in rb_mreq use now aval,re,we instead of req,we
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- basic rbus transaction now takes 2 cycles, one for address select, one
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for data exchange. Same concept and reasoning behind as in ibus V2.
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- vlib/rlink/rlink_core
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- cerr and derr state flags now set on command or data crc errors as well
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as on eop/nak aborts when command or wblk data is received.
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- has now 'monitor port', RL_MONI.
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- RL_FLUSH port removed, the flush logic is now in rlink_serport
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- restructured rlink modules
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- rlink_core is the rlink protocol engine with a 9 bit wide interface
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- rlink_rlb2rl (new) is an adapter to a byte wide interface
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- rlink_base (new) combines rlink_core and rlink_rlb2rl
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- rlink_serport (re-written) is an adapter to a serial interface
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- rlink_base_serport (renamed) combines rlink_base and rlink_serport
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- New features
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- vlib/rbus
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- added several rbus devices useful for debugging
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- rbd_tester: test target, used for example in test benches
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- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) +++++++++++
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- Summary
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- Introduce ibus protocol V2
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- Nexys2 systems use DCM
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- sys_w11a_n2 now runs with 58 MHz
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- Changes
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- module renames:
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- in future 'box' is used for large autonomous blocks, therefore use
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the term unit for purely sequential logic modules:
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pdp11_abox -> pdp11_ounit
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pdp11_dbox -> pdp11_aunit
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pdp11_lbox -> pdp11_lunit
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pdp11_mbox -> pdp11_munit
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- signal renames:
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- renamed RRI_LAM -> RB_LAM in all ibus devices
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- renamed CLK -> I_CLK50 in all top level nexys2 and s3board designs
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- migrate to ibus protocol verion 2
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- in ib_mreq use now aval,re,we,rmw instead of req,we,dip
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- basic ibus transaction now takes 2 cycles, one for address select, one
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for data exchange. This avoids too long logic paths in the ibus logic.
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- New features
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- ibus
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- added ib_sres_or_mon to check for miss-behaving ibus devices
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- added ib_sel to encapsulate address select logic
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- nexys2 systems
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- now DCM derived system clock supported
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- sys_gen/w11a/nexys2
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- sys_w11a_n2 now runs with 58 MHz clksys
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- Bug fixes
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- rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
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- w11a_V0.5 (2010-07-23) +++++++++++++++++++++++++++++++++++++++++++++++++++++
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Initial release with
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- w11a CPU core
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- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
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- just for fun: iist (not fully implemented and tested yet)
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- two complete system configurations with
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- for a Digilent S3BOARD rtl/sys_gen/w11a/s3board/sys_w11a_s3
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- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2
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