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# $Id: w11a_tb_guide.txt 578 2014-08-05 21:28:19Z mueller $
 
Guide to running w11a test benches
 
  Table of content:
 
  1. Unit tests benches
  2. Available unit tests benches
  3. System tests benches
  4. Available system tests benches
 
 
1. Unit tests benches -----------------------------------------------------
 
   All unit test benches have the same simple structure:
 
   - a stimulus process reads test patterns as well as the expected
     responses from a stimulus file
 
   - the responses are checked in very simple cases by the stimulus process,
     in general by a monitoring process
 
   - the test bench produces a comprehensive log file. For each checked
     response the line contains the word "CHECK" and either an "OK" or a
     "FAIL", in the later case in general with an indication of whats wrong.
     Other unexpected behaviour, like timeouts, will also result in a line
     containing the word "FAIL".
 
   - at the end a line with the word "DONE" is printed.
 
   - the test bench is run like
 
       tbw  [stimfile] | tee  | egrep "(FAIL|DONE)"
 
     where
       - 'tbw' is a small perl script setting up a symbolic link to the
         stimulus file, the default extracted from the file tbw.dat, if
         an optional file name is give this one will be used instead.
       - 'tee' ensures that the full log is saved
       - 'egrep' filters FAIL and DONE lines, a successful run will
         produce a single DONE line
 
   - Most tests can be run against
       - the functional model
       - gate level models at three stages
         - the post-xst model   (produced by netgen from ngc xst output)
         - the post-map model   (produced by netgen from ncd ngdbuild output)
         - the post-par model   (produced by netgen from ncd par output)
     This is simply done using
        make _ssim       for post-xst
        make _fsim       for post-map
        make _tsim       for post-par
     all the rest is handled by the build environment.
     An example of a post-synthesis model is given for the w11a core test.
 
2. Available unit tests benches -------------------------------------------
 
   In the following the available tests are listed with
     - the 'make' command to build them
     - the pipe setup to run them
     - the expected output (the run time measured on a 3 GHz system)
 
   - serport receiver test
     cd $RETROBASE/rtl/vlib/serport/tb
     make tb_serport_uart_rx
     time tbw tb_serport_uart_rx |\
       tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
     -> 1269955.0 ns  63488: DONE
     -> real 0m01.178s   user 0m01.172s   sys 0m00.020s
 
   - serport receiver/transmitter test
     make tb_serport_uart_rxtx
     time tbw tb_serport_uart_rxtx |\
       tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
     ->  52335.0 ns   2607: DONE
     -> real 0m00.094s   user 0m00.092s   sys 0m00.008s
 
   - serport autobauder test
     make tb_serport_autobaud
     time tbw tb_serport_autobaud |\
       tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)"
     -> 367475.0 ns  18364: DONE
     -> real 0m00.610s   user 0m00.612s   sys 0m00.004s
 
   - rlink core test
 
     cd $RETROBASE/rtl/vlib/rlink/tb
     make tb_rlink_direct
     time tbw tb_rlink_direct |\
       tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
     ->  147755.0 ns   7378: DONE
     -> real 0m00.317s   user 0m00.324s   sys 0m00.028s
 
   - rlink core test via serial port interface
 
     cd $RETROBASE/rtl/vlib/rlink/tb
     make tb_rlink_sp1c
     time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat |\
       tee tb_rlink_sp1c_stim2_dsim.log | egrep "(FAIL|DONE)"
     ->   24695.0 ns   1225: DONE
     -> real 0m0.133s   user 0m0.104s   sys 0m0.008s
 
     time tbw tb_rlink_sp1c tb_rlink_stim.dat |\
       tee tb_rlink_sp1c_dsim.log | egrep "(FAIL|DONE)"
     -> 551935.0 ns  27587: DONE
     -> real  0m01.714s   user  0m01.704s   sys  0m00.044s
 
   - w11a core test (using behavioural model)
 
     cd $RETROBASE/rtl/w11a/tb
     make tb_pdp11core
     time tbw tb_pdp11core |\
       tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
     -> 1220255.0 ns  61073: DONE
     -> real 0m10.736s   user 0m10.713s   sys 0m00.060s
 
   - w11a core test (using post-synthesis model)
 
     make ghdl_tmp_clean && make tb_pdp11core_ssim
     time tbw tb_pdp11core_ssim |\
       tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
     ->  1220255.0 ns  61073: DONE
     -> real 1m09.738s   user 1m09.588s   sys 0m00.096s
 
   - s3board sram controller test
 
     cd $RETROBASE/rtl/bplib/s3board/tb
     make tb_s3_sram_memctl
     time tbw tb_s3_sram_memctl |\
       tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
     -> 5015.0 ns    241: DONE
     -> real 0m00.113s   user 0m00.068s   sys 0m00.016s
 
   - nexys2/nexys3 cram controller test
 
     cd $RETROBASE/rtl/bplib/nxcramlib/tb
     make tb_nx_cram_memctl_as
     time tbw tb_nx_cram_memctl_as |\
       tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
     -> 24272.5 ns   1204: DONE
     -> real 0m00.343s   user 0m00.248s   sys 0m00.100s
 
3. System tests benches ---------------------------------------------------
 
   The system tests allow to verify to verify a full system design.
   In this case vhdl test bench code contains
     - (simple) models of the memories used on the FPGA boards
     - drivers for the rlink connection (currently just serialport)
     - code to interface the rlink data stream to a UNIX 'named pipe',
       implemented with a C routine which is called via VHPI from VHDL.
   This way the whole ghdl simulation can be controlled via a di-directional
   byte stream.
 
   The rlink backend process can connect either via a named pipe to a ghdl
   simulation, or via a serial port to a FPGA board. This way the same tests
   can be executed in simulation and on real hardware.
 
4. Available system tests benches -----------------------------------------
 
4a. serport tester ---------------------------------------------------
 
   The sys_tst_serloop design is a test target for validating the serial
   link UART stack. Send and receive throughput as well as loop-back tests
   are supported
 
   - sys_tst_serloop_s3 test bench
 
     cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
     make tb_tst_serloop_s3
     time tbw tb_tst_serloop_s3 |\
       tee tb_tst_serloop_s3_dsim.log | egrep "(FAIL|DONE)"
     -> 301353.3 ns  18068: DONE
     -> real 0m1.422s   user 0m1.372s   sys 0m0.024s
 
   - sys_tst_serloop_n2 test bench
 
     cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
     make tb_tst_serloop1_n2
     time tbw tb_tst_serloop1_n2 |\
       tee tb_tst_serloop1_n2_dsim.log | egrep "(FAIL|DONE)"
     -> 361560.0 ns  18068: DONE
     -> real 0m1.341s   user 0m1.340s   sys 0m0.016s
 
     make tb_tst_serloop2_n2
     time tbw tb_tst_serloop2_n2 |\
       tee tb_tst_serloop2_n2_dsim.log | egrep "(FAIL|DONE)"
     -> 304353.3 ns  18248: DONE
     -> real 0m1.933s   user 0m1.924s   sys 0m0.024s
 
   - sys_tst_serloop_n3 test bench
 
     cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
     make tb_tst_serloop1_n3
     time tbw tb_tst_serloop1_n3 |\
       tee tb_tst_serloop1_n3_dsim.log | egrep "(FAIL|DONE)"
     -> 361560.0 ns  18068: DONE
     -> real 0m1.371s   user 0m1.372s   sys 0m0.016s
 
4b. rlink tester -----------------------------------------------------
 
   The sys_tst_rlink design is a test target for validating the rlink
   and rbus functionality at all levels.
 
   - sys_tst_rlink_s3 test bench
 
     cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
     make tb_tst_rlink_s3
     time ti_rri --run="tbw tb_tst_rlink_s3" --fifo --logl=3 -- \
       "package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
       tee tb_tst_rlink_s3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
     -> 960540.0 ns  48017: DONE
     -> real 0m4.470s
 
   - sys_tst_rlink_n2 test bench
 
     cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
     make tb_tst_rlink_n2
     time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
       "package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
       tee tb_tst_rlink_n2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
     -> 960560.0 ns  48017: DONE
     -> real 0m4.717s
 
   - sys_tst_rlink_n3 test bench
 
     cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
     make tb_tst_rlink_n3
     time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \
       "package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
       tee tb_tst_rlink_n3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
     -> 480380.0 ns  48017: DONE
     -> real 0m4.860s
 
4c. w11a systems -----------------------------------------------------
 
   The stimulus file used in the w11a core test can be executed in the
   full system context (both s3board and nexys2 versions) with the
   following commands. Note that the cycle number printed in the DONE
   line can now vary slightly because the response time of the rlink
   backend process and thus scheduling of backend vs. ghdl process
   can affect the result.
 
   - sys_w11a_s3 test bench
 
     cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
     make tb_w11a_s3
     time ti_rri --pack=rw11 --run="tbw tb_w11a_s3" --fifo --logl=3 -- \
         "rw11::setup_cpu" \
         "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
       tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
     ->  7328980.0 ns 366439: DONE
     -> real 0m45.225s   user 0m43.631s   sys 0m0.400s
 
   - sys_w11a_n2 test bench
 
     cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
     make tb_w11a_n2
     time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
         "rw11::setup_cpu" \
         "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
       tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
     ->  7372840.0 ns 368631: DONE
     -> real 0m55.536s   user 0m52.967s   sys 0m0.520s
 
   - sys_w11a_n3 test bench
 
     cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
     make tb_w11a_n3
     time ti_rri --pack=rw11 --run="tbw tb_w11a_n3" --fifo --logl=3 -- \
         "rw11::setup_cpu" \
         "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
       tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
     ->  5121571.1 ns 368738: DONE
     -> real 0m54.908s   user 0m51.831s   sys 0m0.512s
 
   A new, modular w11a test bench is under construction. So far it is very
   incomplete. This very preliminary version can be executed with
 
   - sys_w11a_n2 test bench
 
     cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
     make tb_w11a_n2
     time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
         "rw11::setup_cpu" "rw11::tbench @w11a_all.dat" | \
       tee w11a_tbench_dsim.log | egrep "(-[EFW]:|FAIL|PASS|DONE)"
     -> 5019660.0 ns 250972: DONE
     -> real 0m32.501s   user 0m31.082s   sys 0m0.500s
 

Line No.	Rev	Author	Line
1	25	wfjm	`# $Id: w11a_tb_guide.txt 578 2014-08-05 21:28:19Z mueller $`
2	4	wfjm
3	5	wfjm	`Guide to running w11a test benches`
4	4	wfjm
5	5	wfjm	`Table of content:`
6
7			`1. Unit tests benches`
8			`2. Available unit tests benches`
9			`3. System tests benches`
10			`4. Available system tests benches`
11
12
13	4	wfjm	`1. Unit tests benches -----------------------------------------------------`
14
15			`All unit test benches have the same simple structure:`
16
17			`- a stimulus process reads test patterns as well as the expected`
18			`responses from a stimulus file`
19
20			`- the responses are checked in very simple cases by the stimulus process,`
21			`in general by a monitoring process`
22
23			`- the test bench produces a comprehensive log file. For each checked`
24			`response the line contains the word "CHECK" and either an "OK" or a`
25			`"FAIL", in the later case in general with an indication of whats wrong.`
26			`Other unexpected behaviour, like timeouts, will also result in a line`
27			`containing the word "FAIL".`
28
29			`- at the end a line with the word "DONE" is printed.`
30
31			`- the test bench is run like`
32
33			`tbw [stimfile] \| tee \| egrep "(FAIL\|DONE)"`
34
35			`where`
36			`- 'tbw' is a small perl script setting up a symbolic link to the`
37			`stimulus file, the default extracted from the file tbw.dat, if`
38			`an optional file name is give this one will be used instead.`
39	22	wfjm	`- 'tee' ensures that the full log is saved`
40	4	wfjm	`- 'egrep' filters FAIL and DONE lines, a successful run will`
41			`produce a single DONE line`
42
43			`- Most tests can be run against`
44			`- the functional model`
45			`- gate level models at three stages`
46			`- the post-xst model (produced by netgen from ngc xst output)`
47			`- the post-map model (produced by netgen from ncd ngdbuild output)`
48			`- the post-par model (produced by netgen from ncd par output)`
49			`This is simply done using`
50			`make _ssim for post-xst`
51			`make _fsim for post-map`
52			`make _tsim for post-par`
53			`all the rest is handled by the build environment.`
54			`An example of a post-synthesis model is given for the w11a core test.`
55
56			`2. Available unit tests benches -------------------------------------------`
57
58			`In the following the available tests are listed with`
59			`- the 'make' command to build them`
60			`- the pipe setup to run them`
61			`- the expected output (the run time measured on a 3 GHz system)`
62
63			`- serport receiver test`
64			`cd $RETROBASE/rtl/vlib/serport/tb`
65			`make tb_serport_uart_rx`
66			`time tbw tb_serport_uart_rx \|\`
67			`tee tb_serport_uart_rx_dsim.log \| egrep "(FAIL\|DONE)"`
68	9	wfjm	`-> 1269955.0 ns 63488: DONE`
69	13	wfjm	`-> real 0m01.178s user 0m01.172s sys 0m00.020s`
70	4	wfjm
71			`- serport receiver/transmitter test`
72			`make tb_serport_uart_rxtx`
73			`time tbw tb_serport_uart_rxtx \|\`
74			`tee tb_serport_uart_rxtx_dsim.log \| egrep "(FAIL\|DONE)"`
75	9	wfjm	`-> 52335.0 ns 2607: DONE`
76	13	wfjm	`-> real 0m00.094s user 0m00.092s sys 0m00.008s`
77	4	wfjm
78			`- serport autobauder test`
79			`make tb_serport_autobaud`
80			`time tbw tb_serport_autobaud \|\`
81			`tee tb_serport_autobaud_dsim.log \| egrep "(FAIL\|DONE)"`
82	9	wfjm	`-> 367475.0 ns 18364: DONE`
83	13	wfjm	`-> real 0m00.610s user 0m00.612s sys 0m00.004s`
84	4	wfjm
85	9	wfjm	`- rlink core test`
86	4	wfjm
87	9	wfjm	`cd $RETROBASE/rtl/vlib/rlink/tb`
88			`make tb_rlink_direct`
89			`time tbw tb_rlink_direct \|\`
90			`tee tb_rlink_direct_dsim.log \| egrep "(FAIL\|DONE)"`
91	17	wfjm	`-> 147755.0 ns 7378: DONE`
92	13	wfjm	`-> real 0m00.317s user 0m00.324s sys 0m00.028s`
93	4	wfjm
94	9	wfjm	`- rlink core test via serial port interface`
95	4	wfjm
96	17	wfjm	`cd $RETROBASE/rtl/vlib/rlink/tb`
97			`make tb_rlink_sp1c`
98			`time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat \|\`
99			`tee tb_rlink_sp1c_stim2_dsim.log \| egrep "(FAIL\|DONE)"`
100			`-> 24695.0 ns 1225: DONE`
101			`-> real 0m0.133s user 0m0.104s sys 0m0.008s`
102	4	wfjm
103	17	wfjm	`time tbw tb_rlink_sp1c tb_rlink_stim.dat \|\`
104			`tee tb_rlink_sp1c_dsim.log \| egrep "(FAIL\|DONE)"`
105			`-> 551935.0 ns 27587: DONE`
106	13	wfjm	`-> real 0m01.714s user 0m01.704s sys 0m00.044s`
107	9	wfjm
108	4	wfjm	`- w11a core test (using behavioural model)`
109
110			`cd $RETROBASE/rtl/w11a/tb`
111	9	wfjm	`make tb_pdp11core`
112			`time tbw tb_pdp11core \|\`
113			`tee tb_pdp11core_dsim.log \| egrep "(FAIL\|DONE)"`
114	25	wfjm	`-> 1220255.0 ns 61073: DONE`
115	13	wfjm	`-> real 0m10.736s user 0m10.713s sys 0m00.060s`
116	4	wfjm
117			`- w11a core test (using post-synthesis model)`
118
119	25	wfjm	`make ghdl_tmp_clean && make tb_pdp11core_ssim`
120	9	wfjm	`time tbw tb_pdp11core_ssim \|\`
121			`tee tb_pdp11core_ssim.log \| egrep "(FAIL\|DONE)"`
122	25	wfjm	`-> 1220255.0 ns 61073: DONE`
123	13	wfjm	`-> real 1m09.738s user 1m09.588s sys 0m00.096s`
124	4	wfjm
125	16	wfjm	`- s3board sram controller test`
126
127			`cd $RETROBASE/rtl/bplib/s3board/tb`
128			`make tb_s3_sram_memctl`
129			`time tbw tb_s3_sram_memctl \|\`
130			`tee tb_s3_sram_memctl_dsim.log \| egrep "(FAIL\|DONE)"`
131			`-> 5015.0 ns 241: DONE`
132			`-> real 0m00.113s user 0m00.068s sys 0m00.016s`
133
134			`- nexys2/nexys3 cram controller test`
135
136			`cd $RETROBASE/rtl/bplib/nxcramlib/tb`
137			`make tb_nx_cram_memctl_as`
138			`time tbw tb_nx_cram_memctl_as \|\`
139			`tee tb_nx_cram_memctl_as_dsim.log \| egrep "(FAIL\|DONE)"`
140			`-> 24272.5 ns 1204: DONE`
141			`-> real 0m00.343s user 0m00.248s sys 0m00.100s`
142
143	4	wfjm	`3. System tests benches ---------------------------------------------------`
144
145	11	wfjm	`The system tests allow to verify to verify a full system design.`
146	4	wfjm	`In this case vhdl test bench code contains`
147			`- (simple) models of the memories used on the FPGA boards`
148	9	wfjm	`- drivers for the rlink connection (currently just serialport)`
149			`- code to interface the rlink data stream to a UNIX 'named pipe',`
150	4	wfjm	`implemented with a C routine which is called via VHPI from VHDL.`
151			`This way the whole ghdl simulation can be controlled via a di-directional`
152			`byte stream.`
153
154	11	wfjm	`The rlink backend process can connect either via a named pipe to a ghdl`
155			`simulation, or via a serial port to a FPGA board. This way the same tests`
156			`can be executed in simulation and on real hardware.`
157	4	wfjm
158			`4. Available system tests benches -----------------------------------------`
159
160	20	wfjm	`4a. serport tester ---------------------------------------------------`
161	11	wfjm
162	16	wfjm	`The sys_tst_serloop design is a test target for validating the serial`
163			`link UART stack. Send and receive throughput as well as loop-back tests`
164			`are supported`
165
166			`- sys_tst_serloop_s3 test bench`
167
168			`cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb`
169			`make tb_tst_serloop_s3`
170			`time tbw tb_tst_serloop_s3 \|\`
171			`tee tb_tst_serloop_s3_dsim.log \| egrep "(FAIL\|DONE)"`
172			`-> 301353.3 ns 18068: DONE`
173			`-> real 0m1.422s user 0m1.372s sys 0m0.024s`
174
175			`- sys_tst_serloop_n2 test bench`
176
177			`cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb`
178			`make tb_tst_serloop1_n2`
179			`time tbw tb_tst_serloop1_n2 \|\`
180			`tee tb_tst_serloop1_n2_dsim.log \| egrep "(FAIL\|DONE)"`
181			`-> 361560.0 ns 18068: DONE`
182			`-> real 0m1.341s user 0m1.340s sys 0m0.016s`
183
184			`make tb_tst_serloop2_n2`
185			`time tbw tb_tst_serloop2_n2 \|\`
186			`tee tb_tst_serloop2_n2_dsim.log \| egrep "(FAIL\|DONE)"`
187			`-> 304353.3 ns 18248: DONE`
188			`-> real 0m1.933s user 0m1.924s sys 0m0.024s`
189
190			`- sys_tst_serloop_n3 test bench`
191
192			`cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb`
193			`make tb_tst_serloop1_n3`
194			`time tbw tb_tst_serloop1_n3 \|\`
195			`tee tb_tst_serloop1_n3_dsim.log \| egrep "(FAIL\|DONE)"`
196			`-> 361560.0 ns 18068: DONE`
197			`-> real 0m1.371s user 0m1.372s sys 0m0.016s`
198
199			`4b. rlink tester -----------------------------------------------------`
200
201	11	wfjm	`The sys_tst_rlink design is a test target for validating the rlink`
202			`and rbus functionality at all levels.`
203
204	16	wfjm	`- sys_tst_rlink_s3 test bench`
205
206			`cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb`
207			`make tb_tst_rlink_s3`
208			`time ti_rri --run="tbw tb_tst_rlink_s3" --fifo --logl=3 -- \`
209			`"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" \|\`
210			`tee tb_tst_rlink_s3_dsim.log \| egrep "(-[EFW]:\|FAIL\|PEND\|DONE)"`
211	19	wfjm	`-> 960540.0 ns 48017: DONE`
212			`-> real 0m4.470s`
213	16	wfjm
214	11	wfjm	`- sys_tst_rlink_n2 test bench`
215
216			`cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb`
217			`make tb_tst_rlink_n2`
218			`time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \`
219			`"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" \|\`
220	16	wfjm	`tee tb_tst_rlink_n2_dsim.log \| egrep "(-[EFW]:\|FAIL\|PEND\|DONE)"`
221	19	wfjm	`-> 960560.0 ns 48017: DONE`
222			`-> real 0m4.717s`
223	11	wfjm
224	15	wfjm	`- sys_tst_rlink_n3 test bench`
225
226			`cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb`
227			`make tb_tst_rlink_n3`
228			`time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \`
229			`"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" \|\`
230	16	wfjm	`tee tb_tst_rlink_n3_dsim.log \| egrep "(-[EFW]:\|FAIL\|PEND\|DONE)"`
231	19	wfjm	`-> 480380.0 ns 48017: DONE`
232			`-> real 0m4.860s`
233	15	wfjm
234	16	wfjm	`4c. w11a systems -----------------------------------------------------`
235	11	wfjm
236	4	wfjm	`The stimulus file used in the w11a core test can be executed in the`
237			`full system context (both s3board and nexys2 versions) with the`
238			`following commands. Note that the cycle number printed in the DONE`
239	9	wfjm	`line can now vary slightly because the response time of the rlink`
240	4	wfjm	`backend process and thus scheduling of backend vs. ghdl process`
241			`can affect the result.`
242
243	11	wfjm	`- sys_w11a_s3 test bench`
244	4	wfjm
245			`cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb`
246			`make tb_w11a_s3`
247	20	wfjm	`time ti_rri --pack=rw11 --run="tbw tb_w11a_s3" --fifo --logl=3 -- \`
248			`"rw11::setup_cpu" \`
249			`"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" \|\`
250	16	wfjm	`tee tb_w11a_s3_stim2_dsim.log \| egrep "(-[EFW]:\|FAIL\|PEND\|DONE)"`
251	25	wfjm	`-> 7328980.0 ns 366439: DONE`
252			`-> real 0m45.225s user 0m43.631s sys 0m0.400s`
253	4	wfjm
254	11	wfjm	`- sys_w11a_n2 test bench`
255	4	wfjm
256			`cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb`
257			`make tb_w11a_n2`
258	20	wfjm	`time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \`
259			`"rw11::setup_cpu" \`
260			`"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" \|\`
261	16	wfjm	`tee tb_w11a_n2_stim2_dsim.log \| egrep "(-[EFW]:\|FAIL\|PEND\|DONE)"`
262	25	wfjm	`-> 7372840.0 ns 368631: DONE`
263			`-> real 0m55.536s user 0m52.967s sys 0m0.520s`
264	15	wfjm
265			`- sys_w11a_n3 test bench`
266
267			`cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb`
268			`make tb_w11a_n3`
269	20	wfjm	`time ti_rri --pack=rw11 --run="tbw tb_w11a_n3" --fifo --logl=3 -- \`
270			`"rw11::setup_cpu" \`
271			`"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" \|\`
272	16	wfjm	`tee tb_w11a_n3_stim2_dsim.log \| egrep "(-[EFW]:\|FAIL\|PEND\|DONE)"`
273	25	wfjm	`-> 5121571.1 ns 368738: DONE`
274			`-> real 0m54.908s user 0m51.831s sys 0m0.512s`
275	16	wfjm
276	19	wfjm	`A new, modular w11a test bench is under construction. So far it is very`
277			`incomplete. This very preliminary version can be executed with`
278
279			`- sys_w11a_n2 test bench`
280
281			`cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb`
282			`make tb_w11a_n2`
283	20	wfjm	`time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \`
284			`"rw11::setup_cpu" "rw11::tbench @w11a_all.dat" \| \`
285	19	wfjm	`tee w11a_tbench_dsim.log \| egrep "(-[EFW]:\|FAIL\|PASS\|DONE)"`
286	25	wfjm	`-> 5019660.0 ns 250972: DONE`
287			`-> real 0m32.501s user 0m31.082s sys 0m0.500s`
288	22	wfjm

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