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-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $
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--
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-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: fx2_2fifoctl_as - syn
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-- Description: Cypress EZ-USB FX2 driver (2 fifo; async)
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--
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-- Dependencies: vlib/xlib/iob_reg_o
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-- vlib/xlib/iob_reg_i_gen
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-- vlib/xlib/iob_reg_o_gen
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-- vlib/xlib/iob_reg_io_gen
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-- memlib/fifo_1c_dram
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--
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2
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-- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2
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-- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2
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-- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2
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-- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic
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-- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed)
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-- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's
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-- 2011-12-25 445 1.2 change pktend handling, now timer based
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-- 2011-11-25 433 1.1.1 now numeric_std clean
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-- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle
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-- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low
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-- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port
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-- 2011-07-08 390 1.0 Initial version
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.memlib.all;
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use work.fx2lib.all;
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entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
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generic (
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RXFAWIDTH : positive := 5; -- receive fifo address width
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TXFAWIDTH : positive := 5; -- transmit fifo address width
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PETOWIDTH : positive := 7; -- packet end time-out counter width
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CCWIDTH : positive := 5; -- chunk counter width
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RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
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TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
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RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
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RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
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WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
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WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
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FLAGDELAY : positive := 2); -- flag delay in clock cycles
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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RESET : in slbit := '0'; -- reset
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RXDATA : out slv8; -- receive data out
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RXVAL : out slbit; -- receive data valid
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RXHOLD : in slbit; -- receive data hold
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RXAEMPTY : out slbit; -- receive almost empty flag
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit data busy
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TXAFULL : out slbit; -- transmit almost full flag
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MONI : out fx2ctl_moni_type; -- monitor port data
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end fx2_2fifoctl_as;
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architecture syn of fx2_2fifoctl_as is
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constant c_rxfifo : slv2 := c_fifo_ep4;
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constant c_txfifo : slv2 := c_fifo_ep6;
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constant c_flag_prog : integer := 0;
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constant c_flag_tx_ff : integer := 1;
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constant c_flag_rx_ef : integer := 2;
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constant c_flag_tx2_ff : integer := 3;
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type state_type is (
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s_init, -- s_init: init state
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s_rdprep, -- s_rdprep: prepare read
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s_rdwait, -- s_rdwait: wait for data
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s_rdpwl, -- s_rdpwl: read, strobe low
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s_rdpwh, -- s_rdpwh: read, strobe high
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s_wrprep, -- s_wrprep: prepare write
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s_wrpwl, -- s_wrpwl: write, strobe low
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s_wrpwh, -- s_wrpwh: write, strobe high
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s_peprep, -- s_peprep: prepare pktend
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s_pepwl, -- s_pepwl: pktend, strobe low
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s_pepwh -- s_pepwh: pktend, strobe high
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);
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type regs_type is record
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state : state_type; -- state
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petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
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pepend : slbit; -- pktend pending
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dlycnt : slv4; -- wait delay counter
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moni_ep4_sel : slbit; -- ep4 (rx) select
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moni_ep6_sel : slbit; -- ep6 (tx) select
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moni_ep4_pf : slbit; -- ep4 (rx) prog flag
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moni_ep6_pf : slbit; -- ep6 (rx) prog flag
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end record regs_type;
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constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
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constant regs_init : regs_type := (
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s_init, -- state
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petocnt_init, -- petocnt
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'0', -- pepend
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(others=>'0'), -- cntdly
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'0','0', -- moni_ep(4|6)_sel
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'0','0' -- moni_ep(4|6)_pf
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal FX2_FIFO : slv2 := (others=>'0');
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signal FX2_FIFO_CE : slbit := '0';
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signal FX2_FLAG_N : slv4 := (others=>'0');
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signal FX2_SLRD_N : slbit := '1';
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signal FX2_SLWR_N : slbit := '1';
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signal FX2_SLOE_N : slbit := '1';
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signal FX2_PKTEND_N : slbit := '1';
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signal FX2_DATA_CEI : slbit := '0';
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signal FX2_DATA_CEO : slbit := '0';
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signal FX2_DATA_OE : slbit := '0';
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signal RXFIFO_DI : slv8 := (others=>'0');
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signal RXFIFO_ENA : slbit := '0';
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signal RXFIFO_BUSY : slbit := '0';
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signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
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signal TXFIFO_DO : slv8 := (others=>'0');
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signal TXFIFO_VAL : slbit := '0';
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signal TXFIFO_HOLD : slbit := '0';
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signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0');
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signal TXBUSY_L : slbit := '0';
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begin
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assert RDPWLDELAY<=2**R_REGS.dlycnt'length and
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RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and
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WRPWLDELAY<=2**R_REGS.dlycnt'length and
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WRPWHDELAY<=2**R_REGS.dlycnt'length and
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FLAGDELAY<=2**R_REGS.dlycnt'length
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report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)"
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severity failure;
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assert RXAEMPTY_THRES<=2**RXFAWIDTH and
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TXAFULL_THRES<=2**TXFAWIDTH
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report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)"
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severity failure;
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IOB_FX2_FIFO : iob_reg_o_gen
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generic map (
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DWIDTH => 2,
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INIT => '0')
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port map (
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CLK => CLK,
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CE => FX2_FIFO_CE,
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DO => FX2_FIFO,
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PAD => O_FX2_FIFO
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);
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IOB_FX2_FLAG : iob_reg_i_gen
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generic map (
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DWIDTH => 4,
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INIT => '0')
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port map (
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CLK => CLK,
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CE => '1',
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DI => FX2_FLAG_N,
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PAD => I_FX2_FLAG
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);
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IOB_FX2_SLRD : iob_reg_o
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generic map (
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INIT => '1')
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port map (
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CLK => CLK,
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CE => '1',
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DO => FX2_SLRD_N,
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PAD => O_FX2_SLRD_N
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);
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IOB_FX2_SLWR : iob_reg_o
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generic map (
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INIT => '1')
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port map (
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CLK => CLK,
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CE => '1',
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DO => FX2_SLWR_N,
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PAD => O_FX2_SLWR_N
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);
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IOB_FX2_SLOE : iob_reg_o
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generic map (
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INIT => '1')
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port map (
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CLK => CLK,
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CE => '1',
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DO => FX2_SLOE_N,
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PAD => O_FX2_SLOE_N
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);
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IOB_FX2_PKTEND : iob_reg_o
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generic map (
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INIT => '1')
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port map (
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CLK => CLK,
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CE => '1',
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DO => FX2_PKTEND_N,
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PAD => O_FX2_PKTEND_N
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);
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IOB_FX2_DATA : iob_reg_io_gen
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generic map (
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DWIDTH => 8,
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PULL => "KEEP")
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port map (
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CLK => CLK,
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CEI => FX2_DATA_CEI,
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CEO => FX2_DATA_CEO,
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OE => FX2_DATA_OE,
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DI => RXFIFO_DI, -- input data (read from pad)
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DO => TXFIFO_DO, -- output data (write to pad)
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PAD => IO_FX2_DATA
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);
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RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
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generic map (
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AWIDTH => RXFAWIDTH,
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DWIDTH => 8)
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port map (
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CLK => CLK,
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RESET => RESET,
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DI => RXFIFO_DI,
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ENA => RXFIFO_ENA,
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BUSY => RXFIFO_BUSY,
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DO => RXDATA,
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VAL => RXVAL,
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HOLD => RXHOLD,
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SIZE => RXSIZE
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);
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TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
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generic map (
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AWIDTH => TXFAWIDTH,
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DWIDTH => 8)
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port map (
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CLK => CLK,
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RESET => RESET,
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DI => TXDATA,
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ENA => TXENA,
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BUSY => TXBUSY_L,
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DO => TXFIFO_DO,
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VAL => TXFIFO_VAL,
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HOLD => TXFIFO_HOLD,
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SIZE => TXSIZE
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);
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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303 |
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proc_next: process (R_REGS, CE_USEC,
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FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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309 |
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310 |
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variable idly_ld : slbit := '0';
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311 |
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variable idly_val : slv(r.dlycnt'range) := (others=>'0');
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variable idly_end : slbit := '0';
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variable idly_end1 : slbit := '0';
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variable iflag_rdok : slbit := '0';
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variable iflag_wrok : slbit := '0';
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317 |
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variable ififo_ce : slbit := '0';
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variable ififo : slv2 := "00";
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320 |
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variable irxfifo_ena : slbit := '0';
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variable itxfifo_hold : slbit := '0';
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variable islrd : slbit := '0';
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325 |
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variable islwr : slbit := '0';
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326 |
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variable isloe : slbit := '0';
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variable ipktend : slbit := '0';
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328 |
|
|
|
329 |
|
|
variable idata_cei : slbit := '0';
|
330 |
|
|
variable idata_ceo : slbit := '0';
|
331 |
|
|
variable idata_oe : slbit := '0';
|
332 |
|
|
|
333 |
|
|
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
|
334 |
|
|
|
335 |
|
|
procedure go_rdprep(nstate : out state_type;
|
336 |
|
|
idly_ld : out slbit;
|
337 |
|
|
idly_val : out slv4;
|
338 |
|
|
ififo_ce : out slbit;
|
339 |
|
|
ififo : out slv2) is
|
340 |
|
|
begin
|
341 |
|
|
idly_ld := '1';
|
342 |
|
|
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
|
343 |
|
|
ififo_ce := '1';
|
344 |
|
|
ififo := c_rxfifo;
|
345 |
|
|
nstate := s_rdprep;
|
346 |
|
|
end procedure go_rdprep;
|
347 |
|
|
|
348 |
|
|
procedure go_wrprep(nstate : out state_type;
|
349 |
|
|
idly_ld : out slbit;
|
350 |
|
|
idly_val : out slv4;
|
351 |
|
|
ififo_ce : out slbit;
|
352 |
|
|
ififo : out slv2) is
|
353 |
|
|
begin
|
354 |
|
|
idly_ld := '1';
|
355 |
|
|
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
|
356 |
|
|
ififo_ce := '1';
|
357 |
|
|
ififo := c_txfifo;
|
358 |
|
|
nstate := s_wrprep;
|
359 |
|
|
end procedure go_wrprep;
|
360 |
|
|
|
361 |
|
|
procedure go_peprep(nstate : out state_type;
|
362 |
|
|
idly_ld : out slbit;
|
363 |
|
|
idly_val : out slv4;
|
364 |
|
|
ififo_ce : out slbit;
|
365 |
|
|
ififo : out slv2) is
|
366 |
|
|
begin
|
367 |
|
|
idly_ld := '1';
|
368 |
|
|
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
|
369 |
|
|
ififo_ce := '1';
|
370 |
|
|
ififo := c_txfifo;
|
371 |
|
|
nstate := s_peprep;
|
372 |
|
|
end procedure go_peprep;
|
373 |
|
|
|
374 |
|
|
procedure go_rdpwl(nstate : out state_type;
|
375 |
|
|
idly_ld : out slbit;
|
376 |
|
|
idly_val : out slv4;
|
377 |
|
|
islrd : out slbit) is
|
378 |
|
|
begin
|
379 |
|
|
idly_ld := '1';
|
380 |
|
|
idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length));
|
381 |
|
|
islrd := '1';
|
382 |
|
|
nstate := s_rdpwl;
|
383 |
|
|
end procedure go_rdpwl;
|
384 |
|
|
|
385 |
|
|
procedure go_wrpwl(nstate : out state_type;
|
386 |
|
|
idly_ld : out slbit;
|
387 |
|
|
idly_val : out slv4;
|
388 |
|
|
islwr : out slbit) is
|
389 |
|
|
begin
|
390 |
|
|
idly_ld := '1';
|
391 |
|
|
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
|
392 |
|
|
islwr := '1';
|
393 |
|
|
nstate := s_wrpwl;
|
394 |
|
|
end procedure go_wrpwl;
|
395 |
|
|
|
396 |
|
|
procedure go_pepwl(nstate : out state_type;
|
397 |
|
|
idly_ld : out slbit;
|
398 |
|
|
idly_val : out slv4;
|
399 |
|
|
ipktend : out slbit) is
|
400 |
|
|
begin
|
401 |
|
|
idly_ld := '1';
|
402 |
|
|
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
|
403 |
|
|
ipktend := '1';
|
404 |
|
|
nstate := s_pepwl;
|
405 |
|
|
end procedure go_pepwl;
|
406 |
|
|
|
407 |
|
|
begin
|
408 |
|
|
|
409 |
|
|
r := R_REGS;
|
410 |
|
|
n := R_REGS;
|
411 |
|
|
|
412 |
|
|
ififo_ce := '0';
|
413 |
|
|
ififo := "00";
|
414 |
|
|
|
415 |
|
|
irxfifo_ena := '0';
|
416 |
|
|
itxfifo_hold := '1';
|
417 |
|
|
|
418 |
|
|
islrd := '0';
|
419 |
|
|
islwr := '0';
|
420 |
|
|
isloe := '0';
|
421 |
|
|
ipktend := '0';
|
422 |
|
|
|
423 |
|
|
idata_cei := '0';
|
424 |
|
|
idata_ceo := '0';
|
425 |
|
|
idata_oe := '0';
|
426 |
|
|
|
427 |
|
|
imoni := fx2ctl_moni_init;
|
428 |
|
|
|
429 |
|
|
iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
|
430 |
|
|
iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
|
431 |
|
|
|
432 |
|
|
idly_ld := '0';
|
433 |
|
|
idly_val := (others=>'0');
|
434 |
|
|
idly_end := '1';
|
435 |
|
|
idly_end1 := '0';
|
436 |
|
|
if unsigned(r.dlycnt) /= 0 then
|
437 |
|
|
idly_end := '0';
|
438 |
|
|
end if;
|
439 |
|
|
if unsigned(r.dlycnt) = 1 then
|
440 |
|
|
idly_end1 := '1';
|
441 |
|
|
end if;
|
442 |
|
|
|
443 |
|
|
case r.state is
|
444 |
|
|
when s_init => -- s_init:
|
445 |
|
|
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
446 |
|
|
|
447 |
|
|
when s_rdprep => -- s_rdprep: prepare read
|
448 |
|
|
if idly_end = '1' then
|
449 |
|
|
n.state := s_rdwait;
|
450 |
|
|
end if;
|
451 |
|
|
|
452 |
|
|
when s_rdwait => -- s_rdwait: wait for data
|
453 |
|
|
if r.pepend='1' and TXFIFO_VAL='0' then
|
454 |
|
|
go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
455 |
|
|
|
456 |
|
|
elsif iflag_rdok='1' and
|
457 |
|
|
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
|
458 |
|
|
go_rdpwl(n.state, idly_ld, idly_val, islrd);
|
459 |
|
|
|
460 |
|
|
elsif TXFIFO_VAL = '1' then
|
461 |
|
|
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
462 |
|
|
end if;
|
463 |
|
|
|
464 |
|
|
when s_rdpwl => -- s_rdpwl: read, strobe low
|
465 |
|
|
idata_cei := '1';
|
466 |
|
|
isloe := '1';
|
467 |
|
|
if idly_end = '1' then
|
468 |
|
|
idly_ld := '1';
|
469 |
|
|
idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length));
|
470 |
|
|
n.state := s_rdpwh;
|
471 |
|
|
else
|
472 |
|
|
islrd := '1';
|
473 |
|
|
n.state := s_rdpwl;
|
474 |
|
|
end if;
|
475 |
|
|
|
476 |
|
|
-- Note: data is sampled and written into rxfifo in 2nd last cycle in the
|
477 |
|
|
-- last cycle the rxfifo busy reflects therefore last written byte
|
478 |
|
|
-- and safely indicates whether another byte will fit.
|
479 |
|
|
when s_rdpwh => -- s_rdpwh: read, strobe high
|
480 |
|
|
idata_cei := '1';
|
481 |
|
|
isloe := '1';
|
482 |
|
|
if idly_end1 = '1' then -- 2nd last cycle
|
483 |
|
|
irxfifo_ena := '1'; -- capture rxdata
|
484 |
|
|
end if;
|
485 |
|
|
if idly_end = '1' then -- last cycle
|
486 |
|
|
if iflag_rdok='1' and
|
487 |
|
|
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
|
488 |
|
|
go_rdpwl(n.state, idly_ld, idly_val, islrd);
|
489 |
|
|
|
490 |
|
|
elsif TXFIFO_VAL = '1' then
|
491 |
|
|
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
492 |
|
|
|
493 |
|
|
else
|
494 |
|
|
n.state := s_rdwait;
|
495 |
|
|
end if;
|
496 |
|
|
end if;
|
497 |
|
|
|
498 |
|
|
when s_wrprep => -- s_wrprep: prepare write
|
499 |
|
|
if idly_end = '1' then
|
500 |
|
|
if iflag_wrok = '1' then
|
501 |
|
|
go_wrpwl(n.state, idly_ld, idly_val, islwr);
|
502 |
|
|
else
|
503 |
|
|
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
504 |
|
|
end if;
|
505 |
|
|
end if;
|
506 |
|
|
|
507 |
|
|
when s_wrpwl => -- s_wrpwl: write, strobe low
|
508 |
|
|
idata_ceo := '1';
|
509 |
|
|
idata_oe := '1';
|
510 |
|
|
if idly_end = '1' then
|
511 |
|
|
idata_ceo := '0';
|
512 |
|
|
itxfifo_hold := '0';
|
513 |
|
|
idly_ld := '1';
|
514 |
|
|
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
|
515 |
|
|
n.state := s_wrpwh;
|
516 |
|
|
else
|
517 |
|
|
islwr := '1';
|
518 |
|
|
n.state := s_wrpwl;
|
519 |
|
|
end if;
|
520 |
|
|
|
521 |
|
|
when s_wrpwh => -- s_wrpwh: write, strobe high
|
522 |
|
|
idata_oe := '1';
|
523 |
|
|
if idly_end = '1' then
|
524 |
|
|
if iflag_wrok='1' and TXFIFO_VAL='1' then
|
525 |
|
|
go_wrpwl(n.state, idly_ld, idly_val, islwr);
|
526 |
|
|
elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then
|
527 |
|
|
go_pepwl(n.state, idly_ld, idly_val, ipktend);
|
528 |
|
|
else
|
529 |
|
|
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
530 |
|
|
end if;
|
531 |
|
|
end if;
|
532 |
|
|
|
533 |
|
|
when s_peprep => -- s_peprep: prepare pktend
|
534 |
|
|
if idly_end = '1' then
|
535 |
|
|
if iflag_wrok = '1' then
|
536 |
|
|
go_pepwl(n.state, idly_ld, idly_val, ipktend);
|
537 |
|
|
else
|
538 |
|
|
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
539 |
|
|
end if;
|
540 |
|
|
end if;
|
541 |
|
|
|
542 |
|
|
when s_pepwl => -- s_pepwl: pktend, strobe low
|
543 |
|
|
if idly_end = '1' then
|
544 |
|
|
idly_ld := '1';
|
545 |
|
|
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
|
546 |
|
|
n.state := s_pepwh;
|
547 |
|
|
else
|
548 |
|
|
ipktend := '1';
|
549 |
|
|
n.state := s_pepwl;
|
550 |
|
|
end if;
|
551 |
|
|
|
552 |
|
|
when s_pepwh => -- s_pepwh: pktend, strobe high
|
553 |
|
|
if idly_end = '1' then
|
554 |
|
|
n.pepend := '0';
|
555 |
|
|
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
|
556 |
|
|
end if;
|
557 |
|
|
|
558 |
|
|
when others => null;
|
559 |
|
|
end case;
|
560 |
|
|
|
561 |
|
|
if idly_ld = '1' then
|
562 |
|
|
n.dlycnt := idly_val;
|
563 |
|
|
elsif idly_end = '0' then
|
564 |
|
|
n.dlycnt := slv(unsigned(r.dlycnt) - 1);
|
565 |
|
|
end if;
|
566 |
|
|
|
567 |
|
|
-- pktend time-out handling:
|
568 |
|
|
-- if tx fifo is non-empty, set counter to max
|
569 |
|
|
-- if tx fifo is empty, count down every usec
|
570 |
|
|
-- on 1->0 transition queue pktend request
|
571 |
|
|
if TXFIFO_VAL = '1' then
|
572 |
|
|
n.petocnt := (others=>'1');
|
573 |
|
|
else
|
574 |
|
|
if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then
|
575 |
|
|
n.petocnt := slv(unsigned(r.petocnt) - 1);
|
576 |
|
|
if unsigned(r.petocnt) = 1 then
|
577 |
|
|
n.pepend := '1';
|
578 |
|
|
end if;
|
579 |
|
|
end if;
|
580 |
|
|
end if;
|
581 |
|
|
|
582 |
|
|
n.moni_ep4_sel := '0';
|
583 |
|
|
n.moni_ep6_sel := '0';
|
584 |
|
|
if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or
|
585 |
|
|
r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then
|
586 |
|
|
n.moni_ep6_sel := '1';
|
587 |
|
|
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
|
588 |
|
|
else
|
589 |
|
|
n.moni_ep4_sel := '1';
|
590 |
|
|
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
|
591 |
|
|
end if;
|
592 |
|
|
|
593 |
|
|
imoni.fifo_ep4 := r.moni_ep4_sel;
|
594 |
|
|
imoni.fifo_ep6 := r.moni_ep6_sel;
|
595 |
|
|
imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef);
|
596 |
|
|
imoni.flag_ep4_almost := r.moni_ep4_pf;
|
597 |
|
|
imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff);
|
598 |
|
|
imoni.flag_ep6_almost := r.moni_ep6_pf;
|
599 |
|
|
imoni.slrd := islrd;
|
600 |
|
|
imoni.slwr := islwr;
|
601 |
|
|
imoni.pktend := ipktend;
|
602 |
|
|
|
603 |
|
|
N_REGS <= n;
|
604 |
|
|
|
605 |
|
|
FX2_FIFO_CE <= ififo_ce;
|
606 |
|
|
FX2_FIFO <= ififo;
|
607 |
|
|
|
608 |
|
|
FX2_SLRD_N <= not islrd;
|
609 |
|
|
FX2_SLWR_N <= not islwr;
|
610 |
|
|
FX2_SLOE_N <= not isloe;
|
611 |
|
|
FX2_PKTEND_N <= not ipktend;
|
612 |
|
|
|
613 |
|
|
FX2_DATA_CEI <= idata_cei;
|
614 |
|
|
FX2_DATA_CEO <= idata_ceo;
|
615 |
|
|
FX2_DATA_OE <= idata_oe;
|
616 |
|
|
|
617 |
|
|
RXFIFO_ENA <= irxfifo_ena;
|
618 |
|
|
TXFIFO_HOLD <= itxfifo_hold;
|
619 |
|
|
|
620 |
|
|
MONI <= imoni;
|
621 |
|
|
|
622 |
|
|
end process proc_next;
|
623 |
|
|
|
624 |
|
|
proc_almost: process (RXSIZE, TXSIZE)
|
625 |
|
|
begin
|
626 |
|
|
|
627 |
|
|
-- (rx|tx)size is the number of bytes in fifo
|
628 |
|
|
-- --> rxsize is number of bytes which can be read
|
629 |
|
|
-- --> 2**txfawidth-txsize is is number of bytes which can be written
|
630 |
|
|
|
631 |
|
|
if unsigned(RXSIZE) <= RXAEMPTY_THRES then
|
632 |
|
|
RXAEMPTY <= '1';
|
633 |
|
|
else
|
634 |
|
|
RXAEMPTY <= '0';
|
635 |
|
|
end if;
|
636 |
|
|
|
637 |
|
|
if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then
|
638 |
|
|
TXAFULL <= '1';
|
639 |
|
|
else
|
640 |
|
|
TXAFULL <= '0';
|
641 |
|
|
end if;
|
642 |
|
|
|
643 |
|
|
end process proc_almost;
|
644 |
|
|
|
645 |
|
|
TXBUSY <= TXBUSY_L;
|
646 |
|
|
|
647 |
|
|
end syn;
|